1 /* $OpenBSD: ommmc.c,v 1.29 2016/08/12 03:22:41 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Dale Rahn <drahn@openbsd.org> 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* Omap SD/MMC support derived from /sys/dev/sdmmc/sdhc.c */ 21 22 23 #include <sys/param.h> 24 #include <sys/device.h> 25 #include <sys/kernel.h> 26 #include <sys/kthread.h> 27 #include <sys/malloc.h> 28 #include <sys/systm.h> 29 #include <machine/bus.h> 30 #include <machine/fdt.h> 31 32 #include <dev/sdmmc/sdmmcchip.h> 33 #include <dev/sdmmc/sdmmcvar.h> 34 35 #include <armv7/armv7/armv7var.h> 36 #include <armv7/omap/prcmvar.h> 37 38 #include <dev/ofw/openfirm.h> 39 #include <dev/ofw/ofw_pinctrl.h> 40 #include <dev/ofw/fdt.h> 41 42 /* 43 * NOTE: on OMAP4430/AM335x these registers skew by 0x100 44 * this is handled by mapping at base address + 0x100 45 */ 46 /* registers */ 47 #define MMCHS_SYSCONFIG 0x010 48 #define MMCHS_SYSSTATUS 0x014 49 #define MMCHS_CSRE 0x024 50 #define MMCHS_SYSTEST 0x028 51 #define MMCHS_SYSTEST_SDCD (1 << 15) 52 #define MMCHS_CON 0x02C 53 #define MMCHS_CON_INIT (1<<1) 54 #define MMCHS_CON_DW8 (1<<5) 55 #define MMCHS_CON_OD (1<<0) 56 #define MMCHS_PWCNT 0x030 57 #define MMCHS_BLK 0x104 58 #define MMCHS_BLK_NBLK_MAX 0xffff 59 #define MMCHS_BLK_NBLK_SHIFT 16 60 #define MMCHS_BLK_NBLK_MASK (MMCHS_BLK_NBLK_MAX<<MMCHS_BLK_NBLK_SHIFT) 61 #define MMCHS_BLK_BLEN_MAX 0x400 62 #define MMCHS_BLK_BLEN_SHIFT 0 63 #define MMCHS_BLK_BLEN_MASK (MMCHS_BLK_BLEN_MAX<<MMCHS_BLK_BLEN_SHIFT) 64 #define MMCHS_ARG 0x108 65 #define MMCHS_CMD 0x10C 66 #define MMCHS_CMD_INDX_SHIFT 24 67 #define MMCHS_CMD_INDX_SHIFT_MASK (0x3f << MMCHS_CMD_INDX_SHIFT) 68 #define MMCHS_CMD_CMD_TYPE_SHIFT 22 69 #define MMCHS_CMD_DP_SHIFT 21 70 #define MMCHS_CMD_DP (1 << MMCHS_CMD_DP_SHIFT) 71 #define MMCHS_CMD_CICE_SHIFT 20 72 #define MMCHS_CMD_CICE (1 << MMCHS_CMD_CICE_SHIFT) 73 #define MMCHS_CMD_CCCE_SHIFT 19 74 #define MMCHS_CMD_CCCE (1 << MMCHS_CMD_CCCE_SHIFT) 75 #define MMCHS_CMD_RSP_TYPE_SHIFT 16 76 #define MMCHS_CMD_RESP_NONE (0x0 << MMCHS_CMD_RSP_TYPE_SHIFT) 77 #define MMCHS_CMD_RESP136 (0x1 << MMCHS_CMD_RSP_TYPE_SHIFT) 78 #define MMCHS_CMD_RESP48 (0x2 << MMCHS_CMD_RSP_TYPE_SHIFT) 79 #define MMCHS_CMD_RESP48B (0x3 << MMCHS_CMD_RSP_TYPE_SHIFT) 80 #define MMCHS_CMD_MSBS (1 << 5) 81 #define MMCHS_CMD_DDIR (1 << 4) 82 #define MMCHS_CMD_ACEN (1 << 2) 83 #define MMCHS_CMD_BCE (1 << 1) 84 #define MMCHS_CMD_DE (1 << 0) 85 #define MMCHS_RSP10 0x110 86 #define MMCHS_RSP32 0x114 87 #define MMCHS_RSP54 0x118 88 #define MMCHS_RSP76 0x11C 89 #define MMCHS_DATA 0x120 90 #define MMCHS_PSTATE 0x124 91 #define MMCHS_PSTATE_CLEV (1<<24) 92 #define MMCHS_PSTATE_DLEV_SH 20 93 #define MMCHS_PSTATE_DLEV_M (0xf << MMCHS_PSTATE_DLEV_SH) 94 #define MMCHS_PSTATE_BRE (1<<11) 95 #define MMCHS_PSTATE_BWE (1<<10) 96 #define MMCHS_PSTATE_RTA (1<<9) 97 #define MMCHS_PSTATE_WTA (1<<8) 98 #define MMCHS_PSTATE_DLA (1<<2) 99 #define MMCHS_PSTATE_DATI (1<<1) 100 #define MMCHS_PSTATE_CMDI (1<<0) 101 #define MMCHS_PSTATE_FMT "\20" \ 102 "\x098_CLEV" \ 103 "\x08b_BRE" \ 104 "\x08a_BWE" \ 105 "\x089_RTA" \ 106 "\x088_WTA" \ 107 "\x082_DLA" \ 108 "\x081_DATI" \ 109 "\x080_CMDI" 110 #define MMCHS_HCTL 0x128 111 #define MMCHS_HCTL_SDVS_SHIFT 9 112 #define MMCHS_HCTL_SDVS_MASK (0x7<<MMCHS_HCTL_SDVS_SHIFT) 113 #define MMCHS_HCTL_SDVS_V18 (0x5<<MMCHS_HCTL_SDVS_SHIFT) 114 #define MMCHS_HCTL_SDVS_V30 (0x6<<MMCHS_HCTL_SDVS_SHIFT) 115 #define MMCHS_HCTL_SDVS_V33 (0x7<<MMCHS_HCTL_SDVS_SHIFT) 116 #define MMCHS_HCTL_SDBP (1<<8) 117 #define MMCHS_HCTL_HSPE (1<<2) 118 #define MMCHS_HCTL_DTW (1<<1) 119 #define MMCHS_SYSCTL 0x12C 120 #define MMCHS_SYSCTL_SRD (1<<26) 121 #define MMCHS_SYSCTL_SRC (1<<25) 122 #define MMCHS_SYSCTL_SRA (1<<24) 123 #define MMCHS_SYSCTL_DTO_SH 16 124 #define MMCHS_SYSCTL_DTO_MASK 0x000f0000 125 #define MMCHS_SYSCTL_CLKD_SH 6 126 #define MMCHS_SYSCTL_CLKD_MASK 0x0000ffc0 127 #define MMCHS_SYSCTL_CEN (1<<2) 128 #define MMCHS_SYSCTL_ICS (1<<1) 129 #define MMCHS_SYSCTL_ICE (1<<0) 130 #define MMCHS_STAT 0x130 131 #define MMCHS_STAT_BADA (1<<29) 132 #define MMCHS_STAT_CERR (1<<28) 133 #define MMCHS_STAT_ACE (1<<24) 134 #define MMCHS_STAT_DEB (1<<22) 135 #define MMCHS_STAT_DCRC (1<<21) 136 #define MMCHS_STAT_DTO (1<<20) 137 #define MMCHS_STAT_CIE (1<<19) 138 #define MMCHS_STAT_CEB (1<<18) 139 #define MMCHS_STAT_CCRC (1<<17) 140 #define MMCHS_STAT_CTO (1<<16) 141 #define MMCHS_STAT_ERRI (1<<15) 142 #define MMCHS_STAT_OBI (1<<9) 143 #define MMCHS_STAT_CIRQ (1<<8) 144 #define MMCHS_STAT_BRR (1<<5) 145 #define MMCHS_STAT_BWR (1<<4) 146 #define MMCHS_STAT_BGE (1<<2) 147 #define MMCHS_STAT_TC (1<<1) 148 #define MMCHS_STAT_CC (1<<0) 149 #define MMCHS_STAT_FMT "\20" \ 150 "\x09d_BADA" \ 151 "\x09c_CERR" \ 152 "\x098_ACE" \ 153 "\x096_DEB" \ 154 "\x095_DCRC" \ 155 "\x094_DTO" \ 156 "\x093_CIE" \ 157 "\x092_CEB" \ 158 "\x091_CCRC" \ 159 "\x090_CTO" \ 160 "\x08f_ERRI" \ 161 "\x089_OBI" \ 162 "\x088_CIRQ" \ 163 "\x085_BRR" \ 164 "\x084_BWR" \ 165 "\x082_BGE" \ 166 "\x081_TC" \ 167 "\x080_CC" 168 #define MMCHS_IE 0x134 169 #define MMCHS_ISE 0x138 170 #define MMCHS_AC12 0x13C 171 #define MMCHS_CAPA 0x140 172 #define MMCHS_CAPA_VS18 (1 << 26) 173 #define MMCHS_CAPA_VS30 (1 << 25) 174 #define MMCHS_CAPA_VS33 (1 << 24) 175 #define MMCHS_CAPA_SRS (1 << 23) 176 #define MMCHS_CAPA_DS (1 << 22) 177 #define MMCHS_CAPA_HSS (1 << 21) 178 #define MMCHS_CAPA_MBL_SHIFT 16 179 #define MMCHS_CAPA_MBL_MASK (3 << MMCHS_CAPA_MBL_SHIFT) 180 #define MMCHS_CUR_CAPA 0x148 181 #define MMCHS_REV 0x1fc 182 183 #define SDHC_COMMAND_TIMEOUT hz 184 #define SDHC_BUFFER_TIMEOUT hz 185 #define SDHC_TRANSFER_TIMEOUT hz 186 187 int ommmc_match(struct device *, void *, void *); 188 void ommmc_attach(struct device *, struct device *, void *); 189 190 struct ommmc_softc { 191 struct device sc_dev; 192 bus_space_tag_t sc_iot; 193 bus_space_handle_t sc_ioh; 194 void *sc_ih; /* Interrupt handler */ 195 uint32_t sc_flags; 196 197 struct device *sdmmc; /* generic SD/MMC device */ 198 int clockbit; /* clock control bit */ 199 uint32_t clkbase; /* base clock frequency in KHz */ 200 int maxblklen; /* maximum block length */ 201 int flags; /* flags for this host */ 202 uint32_t ocr; /* OCR value from capabilities */ 203 uint32_t intr_status; /* soft interrupt status */ 204 uint32_t intr_error_status; /* */ 205 }; 206 207 208 /* Host controller functions called by the attachment driver. */ 209 int ommmc_host_found(struct ommmc_softc *, bus_space_tag_t, 210 bus_space_handle_t, bus_size_t, int); 211 void ommmc_power(int, void *); 212 void ommmc_shutdown(void *); 213 int ommmc_intr(void *); 214 215 /* RESET MODES */ 216 #define MMC_RESET_DAT 1 217 #define MMC_RESET_CMD 2 218 #define MMC_RESET_ALL (MMC_RESET_CMD|MMC_RESET_DAT) 219 220 /* flag values */ 221 #define SHF_USE_DMA 0x0001 222 223 #define HREAD4(sc, reg) \ 224 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 225 #define HWRITE4(sc, reg, val) \ 226 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 227 #define HSET4(sc, reg, bits) \ 228 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 229 #define HCLR4(sc, reg, bits) \ 230 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 231 232 int ommmc_host_reset(sdmmc_chipset_handle_t); 233 uint32_t ommmc_host_ocr(sdmmc_chipset_handle_t); 234 int ommmc_host_maxblklen(sdmmc_chipset_handle_t); 235 int ommmc_card_detect(sdmmc_chipset_handle_t); 236 int ommmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 237 int ommmc_bus_clock(sdmmc_chipset_handle_t, int, int); 238 int ommmc_bus_width(sdmmc_chipset_handle_t, int); 239 void ommmc_card_intr_mask(sdmmc_chipset_handle_t, int); 240 void ommmc_card_intr_ack(sdmmc_chipset_handle_t); 241 void ommmc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 242 int ommmc_start_command(struct ommmc_softc *, struct sdmmc_command *); 243 int ommmc_wait_state(struct ommmc_softc *, uint32_t, uint32_t); 244 int ommmc_soft_reset(struct ommmc_softc *, int); 245 int ommmc_wait_intr(struct ommmc_softc *, int, int); 246 void ommmc_transfer_data(struct ommmc_softc *, struct sdmmc_command *); 247 void ommmc_read_data(struct ommmc_softc *, uint8_t *, int); 248 void ommmc_write_data(struct ommmc_softc *, uint8_t *, int); 249 250 /* #define SDHC_DEBUG */ 251 #ifdef SDHC_DEBUG 252 int ommmcdebug = 20; 253 #define DPRINTF(n,s) do { if ((n) <= ommmcdebug) printf s; } while (0) 254 void ommmc_dump_regs(struct ommmc_softc *); 255 #else 256 #define DPRINTF(n,s) do {} while(0) 257 #endif 258 259 struct sdmmc_chip_functions ommmc_functions = { 260 /* host controller reset */ 261 ommmc_host_reset, 262 /* host controller capabilities */ 263 ommmc_host_ocr, 264 ommmc_host_maxblklen, 265 /* card detection */ 266 ommmc_card_detect, 267 /* bus power and clock frequency */ 268 ommmc_bus_power, 269 ommmc_bus_clock, 270 ommmc_bus_width, 271 /* command execution */ 272 ommmc_exec_command, 273 /* card interrupt */ 274 ommmc_card_intr_mask, 275 ommmc_card_intr_ack 276 }; 277 278 struct cfdriver ommmc_cd = { 279 NULL, "ommmc", DV_DULL 280 }; 281 282 struct cfattach ommmc_ca = { 283 sizeof(struct ommmc_softc), ommmc_match, ommmc_attach 284 }; 285 286 int 287 ommmc_match(struct device *parent, void *match, void *aux) 288 { 289 struct fdt_attach_args *faa = aux; 290 291 return (OF_is_compatible(faa->fa_node, "ti,omap3-hsmmc") || 292 OF_is_compatible(faa->fa_node, "ti,omap4-hsmmc")); 293 } 294 295 void 296 ommmc_attach(struct device *parent, struct device *self, void *aux) 297 { 298 struct ommmc_softc *sc = (struct ommmc_softc *) self; 299 struct fdt_attach_args *faa = aux; 300 struct sdmmcbus_attach_args saa; 301 uint32_t caps; 302 uint32_t addr, size; 303 int len, unit; 304 char hwmods[128]; 305 306 if (faa->fa_nreg < 1) 307 return; 308 309 if (faa->fa_reg[0].size <= 0x100) 310 return; 311 312 if (OF_is_compatible(faa->fa_node, "ti,omap4-hsmmc")) { 313 addr = faa->fa_reg[0].addr + 0x100; 314 size = faa->fa_reg[0].size - 0x100; 315 } else { 316 addr = faa->fa_reg[0].addr; 317 size = faa->fa_reg[0].size; 318 } 319 320 unit = 0; 321 if ((len = OF_getprop(faa->fa_node, "ti,hwmods", hwmods, 322 sizeof(hwmods))) == 5) { 323 if (!strncmp(hwmods, "mmc", 3) && 324 (hwmods[3] > '0') && (hwmods[3] <= '9')) 325 unit = hwmods[3] - '1'; 326 } 327 328 sc->sc_iot = faa->fa_iot; 329 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) 330 panic("%s: bus_space_map failed!", __func__); 331 332 printf("\n"); 333 334 pinctrl_byname(faa->fa_node, "default"); 335 336 /* Enable ICLKEN, FCLKEN? */ 337 prcm_enablemodule(PRCM_MMC0 + unit); 338 339 sc->sc_ih = arm_intr_establish_fdt(faa->fa_node, IPL_SDMMC, 340 ommmc_intr, sc, DEVNAME(sc)); 341 if (sc->sc_ih == NULL) { 342 printf("%s: cannot map interrupt\n", DEVNAME(sc)); 343 goto err; 344 } 345 346 /* Controller Voltage Capabilities Initialization */ 347 HSET4(sc, MMCHS_CAPA, MMCHS_CAPA_VS18 | MMCHS_CAPA_VS30); 348 349 #ifdef SDHC_DEBUG 350 ommmc_dump_regs(sc); 351 #endif 352 353 /* 354 * Reset the host controller and enable interrupts. 355 */ 356 ommmc_host_reset(sc); 357 358 /* Determine host capabilities. */ 359 caps = HREAD4(sc, MMCHS_CAPA); 360 361 #if 0 362 /* we want this !! */ 363 /* Use DMA if the host system and the controller support it. */ 364 if (usedma && ISSET(caps, SDHC_DMA_SUPPORT)) 365 SET(sc->flags, SHF_USE_DMA); 366 #endif 367 368 /* 369 * Determine the base clock frequency. (2.2.24) 370 */ 371 372 sc->clkbase = 96 * 1000; 373 #if 0 374 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 375 sc->clkbase = SDHC_BASE_FREQ_KHZ(caps); 376 #endif 377 if (sc->clkbase == 0) { 378 /* The attachment driver must tell us. */ 379 printf("%s: base clock frequency unknown\n", DEVNAME(sc)); 380 goto err; 381 } else if (sc->clkbase < 10000 || sc->clkbase > 96000) { 382 /* SDHC 1.0 supports only 10-63 MHz. */ 383 printf("%s: base clock frequency out of range: %u MHz\n", 384 DEVNAME(sc), sc->clkbase / 1000); 385 goto err; 386 } 387 388 /* 389 * XXX Set the data timeout counter value according to 390 * capabilities. (2.2.15) 391 */ 392 393 394 /* 395 * Determine SD bus voltage levels supported by the controller. 396 */ 397 if (caps & MMCHS_CAPA_VS18) 398 SET(sc->ocr, MMC_OCR_1_65V_1_95V); 399 if (caps & MMCHS_CAPA_VS30) 400 SET(sc->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 401 if (caps & MMCHS_CAPA_VS33) 402 SET(sc->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 403 404 /* 405 * Omap max block size is fixed (single buffer), could limit 406 * this to 512 for double buffering, but dont see the point. 407 */ 408 switch ((caps & MMCHS_CAPA_MBL_MASK) >> MMCHS_CAPA_MBL_SHIFT) { 409 case 0: 410 sc->maxblklen = 512; 411 break; 412 case 1: 413 sc->maxblklen = 1024; 414 break; 415 case 2: 416 sc->maxblklen = 2048; 417 break; 418 default: 419 sc->maxblklen = 512; 420 printf("invalid capability blocksize in capa %08x," 421 " trying 512\n", HREAD4(sc, MMCHS_CAPA)); 422 } 423 /* 424 * MMC does not support blksize > 512 yet 425 */ 426 sc->maxblklen = 512; 427 /* 428 * Attach the generic SD/MMC bus driver. (The bus driver must 429 * not invoke any chipset functions before it is attached.) 430 */ 431 bzero(&saa, sizeof(saa)); 432 saa.saa_busname = "sdmmc"; 433 saa.sct = &ommmc_functions; 434 saa.sch = sc; 435 if (caps & MMCHS_CAPA_HSS) 436 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 437 438 sc->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 439 if (sc->sdmmc == NULL) { 440 printf("%s: can't attach sdmmc\n", DEVNAME(sc)); 441 goto err; 442 } 443 444 return; 445 err: 446 if (sc->sc_ih != NULL) 447 arm_intr_disestablish(sc->sc_ih); 448 bus_space_unmap(sc->sc_iot, sc->sc_ioh, size); 449 } 450 451 452 /* 453 * Power hook established by or called from attachment driver. 454 */ 455 void 456 ommmc_power(int why, void *arg) 457 { 458 #if 0 459 struct ommmc_softc *sc = arg; 460 int n, i; 461 #endif 462 463 switch(why) { 464 case DVACT_SUSPEND: 465 /* XXX poll for command completion or suspend command 466 * in progress */ 467 468 /* Save the host controller state. */ 469 #if 0 470 for (i = 0; i < sizeof sc->regs; i++) 471 sc->regs[i] = HREAD1(sc, i); 472 #endif 473 break; 474 475 case DVACT_RESUME: 476 /* Restore the host controller state. */ 477 #if 0 478 (void)ommmc_host_reset(sc); 479 for (i = 0; i < sizeof sc->regs; i++) 480 HWRITE1(sc, i, sc->regs[i]); 481 #endif 482 break; 483 } 484 } 485 486 /* 487 * Shutdown hook established by or called from attachment driver. 488 */ 489 void 490 ommmc_shutdown(void *arg) 491 { 492 struct ommmc_softc *sc = arg; 493 494 /* XXX chip locks up if we don't disable it before reboot. */ 495 (void)ommmc_host_reset(sc); 496 } 497 498 /* 499 * Reset the host controller. Called during initialization, when 500 * cards are removed, upon resume, and during error recovery. 501 */ 502 int 503 ommmc_host_reset(sdmmc_chipset_handle_t sch) 504 { 505 struct ommmc_softc *sc = sch; 506 uint32_t imask; 507 int error; 508 int s; 509 510 s = splsdmmc(); 511 512 /* Disable all interrupts. */ 513 HWRITE4(sc, MMCHS_IE, 0); 514 HWRITE4(sc, MMCHS_ISE, 0); 515 516 /* 517 * Reset the entire host controller and wait up to 100ms for 518 * the controller to clear the reset bit. 519 */ 520 if ((error = ommmc_soft_reset(sc, MMCHS_SYSCTL_SRA)) != 0) { 521 splx(s); 522 return (error); 523 } 524 525 #if 0 526 HSET4(sc, MMCHS_CON, MMCHS_CON_INIT); 527 HWRITE4(sc, MMCHS_CMD, 0); 528 delay(100); /* should delay 1ms */ 529 530 HWRITE4(sc, MMCHS_STAT, MMCHS_STAT_CC); 531 HCLR4(sc, MMCHS_CON, MMCHS_CON_INIT); 532 HWRITE4(sc, MMCHS_STAT, ~0); 533 #endif 534 535 536 /* Set data timeout counter value to max for now. */ 537 HSET4(sc, MMCHS_SYSCTL, 0xe << MMCHS_SYSCTL_DTO_SH); 538 539 /* Enable interrupts. */ 540 imask = MMCHS_STAT_BRR | MMCHS_STAT_BWR | MMCHS_STAT_BGE | 541 MMCHS_STAT_TC | MMCHS_STAT_CC; 542 543 imask |= MMCHS_STAT_BADA | MMCHS_STAT_CERR | MMCHS_STAT_DEB | 544 MMCHS_STAT_DCRC | MMCHS_STAT_DTO | MMCHS_STAT_CIE | 545 MMCHS_STAT_CEB | MMCHS_STAT_CCRC | MMCHS_STAT_CTO; 546 547 HWRITE4(sc, MMCHS_IE, imask); 548 HWRITE4(sc, MMCHS_ISE, imask); 549 550 /* Switch back to 1-bit bus. */ 551 HCLR4(sc, MMCHS_CON, MMCHS_CON_DW8); 552 HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_DTW); 553 554 splx(s); 555 return (0); 556 } 557 558 uint32_t 559 ommmc_host_ocr(sdmmc_chipset_handle_t sch) 560 { 561 struct ommmc_softc *sc = sch; 562 return (sc->ocr); 563 } 564 565 int 566 ommmc_host_maxblklen(sdmmc_chipset_handle_t sch) 567 { 568 struct ommmc_softc *sc = sch; 569 return (sc->maxblklen); 570 } 571 572 /* 573 * Return non-zero if the card is currently inserted. 574 */ 575 int 576 ommmc_card_detect(sdmmc_chipset_handle_t sch) 577 { 578 struct ommmc_softc *sc = sch; 579 return !ISSET(HREAD4(sc, MMCHS_SYSTEST), MMCHS_SYSTEST_SDCD) ? 580 1 : 0; 581 } 582 583 /* 584 * Set or change SD bus voltage and enable or disable SD bus power. 585 * Return zero on success. 586 */ 587 int 588 ommmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 589 { 590 struct ommmc_softc *sc = sch; 591 uint32_t vdd; 592 uint32_t reg; 593 int s; 594 595 s = splsdmmc(); 596 597 /* 598 * Disable bus power before voltage change. 599 */ 600 HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_SDBP); 601 602 /* If power is disabled, reset the host and return now. */ 603 if (ocr == 0) { 604 splx(s); 605 (void)ommmc_host_reset(sc); 606 return (0); 607 } 608 609 /* 610 * Select the maximum voltage according to capabilities. 611 */ 612 ocr &= sc->ocr; 613 614 if (ISSET(ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V)) 615 vdd = MMCHS_HCTL_SDVS_V33; 616 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V)) 617 vdd = MMCHS_HCTL_SDVS_V30; 618 else if (ISSET(ocr, MMC_OCR_1_65V_1_95V)) 619 vdd = MMCHS_HCTL_SDVS_V18; 620 else { 621 /* Unsupported voltage level requested. */ 622 splx(s); 623 return (EINVAL); 624 } 625 626 /* 627 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 628 * voltage ramp until power rises. 629 */ 630 reg = HREAD4(sc, MMCHS_HCTL); 631 reg &= ~MMCHS_HCTL_SDVS_MASK; 632 reg |= vdd; 633 HWRITE4(sc, MMCHS_HCTL, reg); 634 635 HSET4(sc, MMCHS_HCTL, MMCHS_HCTL_SDBP); 636 delay(10000); /* XXX */ 637 638 /* 639 * The host system may not power the bus due to battery low, 640 * etc. In that case, the host controller should clear the 641 * bus power bit. 642 */ 643 if (!ISSET(HREAD4(sc, MMCHS_HCTL), MMCHS_HCTL_SDBP)) { 644 splx(s); 645 return (ENXIO); 646 } 647 648 splx(s); 649 return (0); 650 } 651 652 /* 653 * Return the smallest possible base clock frequency divisor value 654 * for the CLOCK_CTL register to produce `freq' (KHz). 655 */ 656 static int 657 ommmc_clock_divisor(struct ommmc_softc *sc, uint32_t freq) 658 { 659 int div; 660 uint32_t maxclk = MMCHS_SYSCTL_CLKD_MASK>>MMCHS_SYSCTL_CLKD_SH; 661 662 for (div = 1; div <= maxclk; div++) 663 if ((sc->clkbase / div) <= freq) { 664 return (div); 665 } 666 667 printf("divisor failure\n"); 668 /* No divisor found. */ 669 return (-1); 670 } 671 672 /* 673 * Set or change SDCLK frequency or disable the SD clock. 674 * Return zero on success. 675 */ 676 int 677 ommmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 678 { 679 int error = 0; 680 struct ommmc_softc *sc = sch; 681 uint32_t reg; 682 int s; 683 int div; 684 int timo; 685 686 s = splsdmmc(); 687 688 /* Must not stop the clock if commands are in progress. */ 689 for (timo = 1000; timo > 0; timo--) { 690 if (!ISSET(HREAD4(sc, MMCHS_PSTATE), 691 MMCHS_PSTATE_CMDI|MMCHS_PSTATE_DATI)) 692 break; 693 delay(10); 694 } 695 if (timo == 0) { 696 error = ETIMEDOUT; 697 goto ret; 698 } 699 700 /* 701 * Stop SD clock before changing the frequency. 702 */ 703 HCLR4(sc, MMCHS_SYSCTL, MMCHS_SYSCTL_CEN); 704 if (freq == SDMMC_SDCLK_OFF) 705 goto ret; 706 707 /* 708 * Set the minimum base clock frequency divisor. 709 */ 710 if ((div = ommmc_clock_divisor(sc, freq)) < 0) { 711 /* Invalid base clock frequency or `freq' value. */ 712 error = EINVAL; 713 goto ret; 714 } 715 reg = HREAD4(sc, MMCHS_SYSCTL); 716 reg &= ~MMCHS_SYSCTL_CLKD_MASK; 717 reg |= div << MMCHS_SYSCTL_CLKD_SH; 718 HWRITE4(sc, MMCHS_SYSCTL, reg); 719 720 if (timing == SDMMC_TIMING_LEGACY) 721 HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_HSPE); 722 else 723 HSET4(sc, MMCHS_HCTL, MMCHS_HCTL_HSPE); 724 725 /* 726 * Start internal clock. Wait 10ms for stabilization. 727 */ 728 HSET4(sc, MMCHS_SYSCTL, MMCHS_SYSCTL_ICE); 729 for (timo = 1000; timo > 0; timo--) { 730 if (ISSET(HREAD4(sc, MMCHS_SYSCTL), MMCHS_SYSCTL_ICS)) 731 break; 732 delay(10); 733 } 734 if (timo == 0) { 735 error = ETIMEDOUT; 736 goto ret; 737 } 738 739 /* 740 * Enable SD clock. 741 */ 742 HSET4(sc, MMCHS_SYSCTL, MMCHS_SYSCTL_CEN); 743 ret: 744 splx(s); 745 return (error); 746 } 747 748 int 749 ommmc_bus_width(sdmmc_chipset_handle_t sch, int width) 750 { 751 struct ommmc_softc *sc = sch; 752 int s; 753 754 if (width != 1 && width != 4 && width != 8) 755 return (1); 756 757 s = splsdmmc(); 758 759 if (width == 8) 760 HSET4(sc, MMCHS_CON, MMCHS_CON_DW8); 761 else 762 HCLR4(sc, MMCHS_CON, MMCHS_CON_DW8); 763 764 if (width == 4) 765 HSET4(sc, MMCHS_HCTL, MMCHS_HCTL_DTW); 766 else if (width == 1) 767 HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_DTW); 768 769 splx(s); 770 771 return (0); 772 } 773 774 void 775 ommmc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 776 { 777 /* - this is SDIO card interrupt */ 778 struct ommmc_softc *sc = sch; 779 780 if (enable) { 781 HSET4(sc, MMCHS_IE, MMCHS_STAT_CIRQ); 782 HSET4(sc, MMCHS_ISE, MMCHS_STAT_CIRQ); 783 } else { 784 HCLR4(sc, MMCHS_IE, MMCHS_STAT_CIRQ); 785 HCLR4(sc, MMCHS_ISE, MMCHS_STAT_CIRQ); 786 } 787 } 788 789 void 790 ommmc_card_intr_ack(sdmmc_chipset_handle_t sch) 791 { 792 struct ommmc_softc *sc = sch; 793 794 HWRITE4(sc, MMCHS_STAT, MMCHS_STAT_CIRQ); 795 } 796 797 int 798 ommmc_wait_state(struct ommmc_softc *sc, uint32_t mask, uint32_t value) 799 { 800 uint32_t state; 801 int timeout; 802 803 state = HREAD4(sc, MMCHS_PSTATE); 804 DPRINTF(3,("%s: wait_state %x %x %x(state=%b)\n", DEVNAME(sc), 805 mask, value, state, state, MMCHS_PSTATE_FMT)); 806 for (timeout = 1000; timeout > 0; timeout--) { 807 if (((state = HREAD4(sc, MMCHS_PSTATE)) & mask) == value) 808 return (0); 809 delay(10); 810 } 811 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(sc), 812 value, state, MMCHS_PSTATE_FMT)); 813 return (ETIMEDOUT); 814 } 815 816 void 817 ommmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 818 { 819 struct ommmc_softc *sc = sch; 820 int error; 821 822 /* 823 * Start the MMC command, or mark `cmd' as failed and return. 824 */ 825 error = ommmc_start_command(sc, cmd); 826 if (error != 0) { 827 cmd->c_error = error; 828 SET(cmd->c_flags, SCF_ITSDONE); 829 return; 830 } 831 832 /* 833 * Wait until the command phase is done, or until the command 834 * is marked done for any other reason. 835 */ 836 if (!ommmc_wait_intr(sc, MMCHS_STAT_CC, SDHC_COMMAND_TIMEOUT)) { 837 cmd->c_error = ETIMEDOUT; 838 SET(cmd->c_flags, SCF_ITSDONE); 839 return; 840 } 841 842 /* 843 * The host controller removes bits [0:7] from the response 844 * data (CRC) and we pass the data up unchanged to the bus 845 * driver (without padding). 846 */ 847 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 848 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 849 uint32_t v0,v1,v2,v3; 850 v0 = HREAD4(sc, MMCHS_RSP10); 851 v1 = HREAD4(sc, MMCHS_RSP32); 852 v2 = HREAD4(sc, MMCHS_RSP54); 853 v3 = HREAD4(sc, MMCHS_RSP76); 854 855 cmd->c_resp[0] = (v0 >> 8) | ((v1 & 0xff) << 24); 856 cmd->c_resp[1] = (v1 >> 8) | ((v2 & 0xff) << 24); 857 cmd->c_resp[2] = (v2 >> 8) | ((v3 & 0xff) << 24); 858 cmd->c_resp[3] = v3 >> 8; 859 #ifdef SDHC_DEBUG 860 printf("resp[0] 0x%08x\nresp[1] 0x%08x\nresp[2] 0x%08x\nresp[3] 0x%08x\n", cmd->c_resp[0], cmd->c_resp[1], cmd->c_resp[2], cmd->c_resp[3]); 861 #endif 862 } else { 863 cmd->c_resp[0] = HREAD4(sc, MMCHS_RSP10); 864 #ifdef SDHC_DEBUG 865 printf("resp[0] 0x%08x\n", cmd->c_resp[0]); 866 #endif 867 } 868 } 869 870 /* 871 * If the command has data to transfer in any direction, 872 * execute the transfer now. 873 */ 874 if (cmd->c_error == 0 && cmd->c_data != NULL) 875 ommmc_transfer_data(sc, cmd); 876 877 #if 0 878 /* Turn off the LED. */ 879 HCLR1(sc, SDHC_HOST_CTL, SDHC_LED_ON); 880 #endif 881 882 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n", 883 DEVNAME(sc), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 884 SET(cmd->c_flags, SCF_ITSDONE); 885 } 886 887 int 888 ommmc_start_command(struct ommmc_softc *sc, struct sdmmc_command *cmd) 889 { 890 uint32_t blksize = 0; 891 uint32_t blkcount = 0; 892 uint32_t command; 893 int error; 894 int s; 895 896 DPRINTF(1,("%s: start cmd %u arg=%#x data=%p dlen=%d flags=%#x " 897 "proc=\"%s\"\n", DEVNAME(sc), cmd->c_opcode, cmd->c_arg, 898 cmd->c_data, cmd->c_datalen, cmd->c_flags, curproc ? 899 curproc->p_comm : "")); 900 901 /* 902 * The maximum block length for commands should be the minimum 903 * of the host buffer size and the card buffer size. (1.7.2) 904 */ 905 906 /* Fragment the data into proper blocks. */ 907 if (cmd->c_datalen > 0) { 908 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 909 blkcount = cmd->c_datalen / blksize; 910 if (cmd->c_datalen % blksize > 0) { 911 /* XXX: Split this command. (1.7.4) */ 912 printf("%s: data not a multiple of %d bytes\n", 913 DEVNAME(sc), blksize); 914 return (EINVAL); 915 } 916 } 917 918 /* Check limit imposed by 9-bit block count. (1.7.2) */ 919 if (blkcount > MMCHS_BLK_NBLK_MAX) { 920 printf("%s: too much data\n", DEVNAME(sc)); 921 return (EINVAL); 922 } 923 924 /* Prepare transfer mode register value. (2.2.5) */ 925 command = 0; 926 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 927 command |= MMCHS_CMD_DDIR; 928 if (blkcount > 0) { 929 command |= MMCHS_CMD_BCE; 930 if (blkcount > 1) { 931 command |= MMCHS_CMD_MSBS; 932 /* XXX only for memory commands? */ 933 command |= MMCHS_CMD_ACEN; 934 } 935 } 936 #ifdef notyet 937 if (ISSET(sc->flags, SHF_USE_DMA)) 938 command |= MMCHS_CMD_DE; 939 #endif 940 941 /* 942 * Prepare command register value. (2.2.6) 943 */ 944 command |= (cmd->c_opcode << MMCHS_CMD_INDX_SHIFT) & 945 MMCHS_CMD_INDX_SHIFT_MASK; 946 947 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 948 command |= MMCHS_CMD_CCCE; 949 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 950 command |= MMCHS_CMD_CICE; 951 if (cmd->c_data != NULL) 952 command |= MMCHS_CMD_DP; 953 954 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 955 command |= MMCHS_CMD_RESP_NONE; 956 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 957 command |= MMCHS_CMD_RESP136; 958 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 959 command |= MMCHS_CMD_RESP48B; 960 else 961 command |= MMCHS_CMD_RESP48; 962 963 /* Wait until command and data inhibit bits are clear. (1.5) */ 964 if ((error = ommmc_wait_state(sc, MMCHS_PSTATE_CMDI, 0)) != 0) 965 return (error); 966 967 s = splsdmmc(); 968 969 #if 0 970 /* Alert the user not to remove the card. */ 971 HSET1(sc, SDHC_HOST_CTL, SDHC_LED_ON); 972 #endif 973 974 /* XXX: Set DMA start address if SHF_USE_DMA is set. */ 975 976 DPRINTF(1,("%s: cmd=%#x blksize=%d blkcount=%d\n", 977 DEVNAME(sc), command, blksize, blkcount)); 978 979 /* 980 * Start a CPU data transfer. Writing to the high order byte 981 * of the SDHC_COMMAND register triggers the SD command. (1.5) 982 */ 983 HWRITE4(sc, MMCHS_BLK, (blkcount << MMCHS_BLK_NBLK_SHIFT) | 984 (blksize << MMCHS_BLK_BLEN_SHIFT)); 985 HWRITE4(sc, MMCHS_ARG, cmd->c_arg); 986 HWRITE4(sc, MMCHS_CMD, command); 987 988 splx(s); 989 return (0); 990 } 991 992 void 993 ommmc_transfer_data(struct ommmc_softc *sc, struct sdmmc_command *cmd) 994 { 995 uint8_t *datap = cmd->c_data; 996 int i, datalen; 997 int mask; 998 int error; 999 1000 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 1001 MMCHS_PSTATE_BRE : MMCHS_PSTATE_BWE; 1002 error = 0; 1003 datalen = cmd->c_datalen; 1004 1005 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(sc), 1006 MMC_R1(cmd->c_resp), datalen)); 1007 1008 while (datalen > 0) { 1009 if (!ommmc_wait_intr(sc, MMCHS_STAT_BRR| MMCHS_STAT_BWR, 1010 SDHC_BUFFER_TIMEOUT)) { 1011 error = ETIMEDOUT; 1012 break; 1013 } 1014 1015 if ((error = ommmc_wait_state(sc, mask, mask)) != 0) 1016 break; 1017 1018 i = MIN(datalen, cmd->c_blklen); 1019 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1020 ommmc_read_data(sc, datap, i); 1021 else 1022 ommmc_write_data(sc, datap, i); 1023 1024 datap += i; 1025 datalen -= i; 1026 } 1027 1028 if (error == 0 && !ommmc_wait_intr(sc, MMCHS_STAT_TC, 1029 SDHC_TRANSFER_TIMEOUT)) 1030 error = ETIMEDOUT; 1031 1032 if (error != 0) 1033 cmd->c_error = error; 1034 SET(cmd->c_flags, SCF_ITSDONE); 1035 1036 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1037 DEVNAME(sc), cmd->c_error)); 1038 } 1039 1040 void 1041 ommmc_read_data(struct ommmc_softc *sc, uint8_t *datap, int datalen) 1042 { 1043 while (datalen > 3) { 1044 *(uint32_t *)datap = HREAD4(sc, MMCHS_DATA); 1045 datap += 4; 1046 datalen -= 4; 1047 } 1048 if (datalen > 0) { 1049 uint32_t rv = HREAD4(sc, MMCHS_DATA); 1050 do { 1051 *datap++ = rv & 0xff; 1052 rv = rv >> 8; 1053 } while (--datalen > 0); 1054 } 1055 } 1056 1057 void 1058 ommmc_write_data(struct ommmc_softc *sc, uint8_t *datap, int datalen) 1059 { 1060 while (datalen > 3) { 1061 DPRINTF(3,("%08x\n", *(uint32_t *)datap)); 1062 HWRITE4(sc, MMCHS_DATA, *((uint32_t *)datap)); 1063 datap += 4; 1064 datalen -= 4; 1065 } 1066 if (datalen > 0) { 1067 uint32_t rv = *datap++; 1068 if (datalen > 1) 1069 rv |= *datap++ << 8; 1070 if (datalen > 2) 1071 rv |= *datap++ << 16; 1072 DPRINTF(3,("rv %08x\n", rv)); 1073 HWRITE4(sc, MMCHS_DATA, rv); 1074 } 1075 } 1076 1077 /* Prepare for another command. */ 1078 int 1079 ommmc_soft_reset(struct ommmc_softc *sc, int mask) 1080 { 1081 1082 int timo; 1083 1084 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(sc), mask)); 1085 1086 HSET4(sc, MMCHS_SYSCTL, mask); 1087 /* 1088 * If we read the software reset register too fast after writing it we 1089 * can get back a zero that means the reset hasn't started yet rather 1090 * than that the reset is complete. Per TI recommendations, work around 1091 * it by reading until we see the reset bit asserted, then read until 1092 * it's clear. 1093 */ 1094 for (timo = 1000; timo > 0; timo--) { 1095 if (ISSET(HREAD4(sc, MMCHS_SYSCTL), mask)) 1096 break; 1097 delay(1); 1098 } 1099 for (timo = 1000; timo > 0; timo--) { 1100 if (!ISSET(HREAD4(sc, MMCHS_SYSCTL), mask)) 1101 break; 1102 delay(10); 1103 } 1104 if (timo == 0) { 1105 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(sc), 1106 HREAD4(sc, MMCHS_SYSCTL))); 1107 return (ETIMEDOUT); 1108 } 1109 1110 return (0); 1111 } 1112 1113 int 1114 ommmc_wait_intr(struct ommmc_softc *sc, int mask, int timo) 1115 { 1116 int status; 1117 int s; 1118 1119 mask |= MMCHS_STAT_ERRI; 1120 1121 s = splsdmmc(); 1122 status = sc->intr_status & mask; 1123 while (status == 0) { 1124 if (tsleep(&sc->intr_status, PWAIT, "hcintr", timo) 1125 == EWOULDBLOCK) { 1126 status |= MMCHS_STAT_ERRI; 1127 break; 1128 } 1129 status = sc->intr_status & mask; 1130 } 1131 sc->intr_status &= ~status; 1132 1133 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(sc), status, 1134 sc->intr_error_status)); 1135 1136 /* Command timeout has higher priority than command complete. */ 1137 if (ISSET(status, MMCHS_STAT_ERRI)) { 1138 sc->intr_error_status = 0; 1139 (void)ommmc_soft_reset(sc, MMCHS_SYSCTL_SRC|MMCHS_SYSCTL_SRD); 1140 status = 0; 1141 } 1142 1143 splx(s); 1144 return (status); 1145 } 1146 1147 /* 1148 * Established by attachment driver at interrupt priority IPL_SDMMC. 1149 */ 1150 int 1151 ommmc_intr(void *arg) 1152 { 1153 struct ommmc_softc *sc = arg; 1154 1155 uint32_t status; 1156 1157 /* Find out which interrupts are pending. */ 1158 status = HREAD4(sc, MMCHS_STAT); 1159 1160 /* Acknowledge the interrupts we are about to handle. */ 1161 HWRITE4(sc, MMCHS_STAT, status); 1162 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(sc), 1163 status, MMCHS_STAT_FMT)); 1164 1165 /* 1166 * Service error interrupts. 1167 */ 1168 if (ISSET(status, MMCHS_STAT_ERRI)) { 1169 if (ISSET(status, MMCHS_STAT_CTO| 1170 MMCHS_STAT_DTO)) { 1171 sc->intr_status |= status; 1172 sc->intr_error_status |= status & 0xffff0000; 1173 wakeup(&sc->intr_status); 1174 } 1175 } 1176 1177 #if 0 1178 /* 1179 * Wake up the sdmmc event thread to scan for cards. 1180 */ 1181 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 1182 ommmc_needs_discover(sc->sdmmc); 1183 #endif 1184 1185 /* 1186 * Wake up the blocking process to service command 1187 * related interrupt(s). 1188 */ 1189 if (ISSET(status, MMCHS_STAT_BRR| 1190 MMCHS_STAT_BWR|MMCHS_STAT_TC| 1191 MMCHS_STAT_CC)) { 1192 sc->intr_status |= status; 1193 wakeup(&sc->intr_status); 1194 } 1195 1196 /* 1197 * Service SD card interrupts. 1198 */ 1199 if (ISSET(status, MMCHS_STAT_CIRQ)) { 1200 DPRINTF(0,("%s: card interrupt\n", DEVNAME(sc))); 1201 HCLR4(sc, MMCHS_STAT, MMCHS_STAT_CIRQ); 1202 sdmmc_card_intr(sc->sdmmc); 1203 } 1204 return 1; 1205 } 1206 1207 #ifdef SDHC_DEBUG 1208 void 1209 ommmc_dump_regs(struct ommmc_softc *sc) 1210 { 1211 } 1212 #endif 1213