1 /* $OpenBSD: ommmc.c,v 1.13 2014/11/04 13:18:04 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Dale Rahn <drahn@openbsd.org> 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* Omap SD/MMC support derived from /sys/dev/sdmmc/sdhc.c */ 21 22 23 #include <sys/param.h> 24 #include <sys/device.h> 25 #include <sys/kernel.h> 26 #include <sys/kthread.h> 27 #include <sys/malloc.h> 28 #include <sys/systm.h> 29 #include <machine/bus.h> 30 31 #include <dev/sdmmc/sdmmcchip.h> 32 #include <dev/sdmmc/sdmmcvar.h> 33 34 #include <armv7/armv7/armv7var.h> 35 #include <armv7/omap/prcmvar.h> 36 37 /* 38 * NOTE: on OMAP4430/AM335x these registers skew by 0x100 39 * this is handled by mapping at base address + 0x100 40 */ 41 /* registers */ 42 #define MMCHS_SYSCONFIG 0x010 43 #define MMCHS_SYSSTATUS 0x014 44 #define MMCHS_CSRE 0x024 45 #define MMCHS_SYSTEST 0x028 46 #define MMCHS_SYSTEST_SDCD (1 << 15) 47 #define MMCHS_CON 0x02C 48 #define MMCHS_CON_INIT (1<<1) 49 #define MMCHS_CON_DW8 (1<<5) 50 #define MMCHS_CON_OD (1<<0) 51 #define MMCHS_PWCNT 0x030 52 #define MMCHS_BLK 0x104 53 #define MMCHS_BLK_NBLK_MAX 0xffff 54 #define MMCHS_BLK_NBLK_SHIFT 16 55 #define MMCHS_BLK_NBLK_MASK (MMCHS_BLK_NBLK_MAX<<MMCHS_BLK_NBLK_SHIFT) 56 #define MMCHS_BLK_BLEN_MAX 0x400 57 #define MMCHS_BLK_BLEN_SHIFT 0 58 #define MMCHS_BLK_BLEN_MASK (MMCHS_BLK_BLEN_MAX<<MMCHS_BLK_BLEN_SHIFT) 59 #define MMCHS_ARG 0x108 60 #define MMCHS_CMD 0x10C 61 #define MMCHS_CMD_INDX_SHIFT 24 62 #define MMCHS_CMD_INDX_SHIFT_MASK (0x3f << MMCHS_CMD_INDX_SHIFT) 63 #define MMCHS_CMD_CMD_TYPE_SHIFT 22 64 #define MMCHS_CMD_DP_SHIFT 21 65 #define MMCHS_CMD_DP (1 << MMCHS_CMD_DP_SHIFT) 66 #define MMCHS_CMD_CICE_SHIFT 20 67 #define MMCHS_CMD_CICE (1 << MMCHS_CMD_CICE_SHIFT) 68 #define MMCHS_CMD_CCCE_SHIFT 19 69 #define MMCHS_CMD_CCCE (1 << MMCHS_CMD_CCCE_SHIFT) 70 #define MMCHS_CMD_RSP_TYPE_SHIFT 16 71 #define MMCHS_CMD_RESP_NONE (0x0 << MMCHS_CMD_RSP_TYPE_SHIFT) 72 #define MMCHS_CMD_RESP136 (0x1 << MMCHS_CMD_RSP_TYPE_SHIFT) 73 #define MMCHS_CMD_RESP48 (0x2 << MMCHS_CMD_RSP_TYPE_SHIFT) 74 #define MMCHS_CMD_RESP48B (0x3 << MMCHS_CMD_RSP_TYPE_SHIFT) 75 #define MMCHS_CMD_MSBS (1 << 5) 76 #define MMCHS_CMD_DDIR (1 << 4) 77 #define MMCHS_CMD_ACEN (1 << 2) 78 #define MMCHS_CMD_BCE (1 << 1) 79 #define MMCHS_CMD_DE (1 << 0) 80 #define MMCHS_RSP10 0x110 81 #define MMCHS_RSP32 0x114 82 #define MMCHS_RSP54 0x118 83 #define MMCHS_RSP76 0x11C 84 #define MMCHS_DATA 0x120 85 #define MMCHS_PSTATE 0x124 86 #define MMCHS_PSTATE_CLEV (1<<24) 87 #define MMCHS_PSTATE_DLEV_SH 20 88 #define MMCHS_PSTATE_DLEV_M (0xf << MMCHS_PSTATE_DLEV_SH) 89 #define MMCHS_PSTATE_BRE (1<<11) 90 #define MMCHS_PSTATE_BWE (1<<10) 91 #define MMCHS_PSTATE_RTA (1<<9) 92 #define MMCHS_PSTATE_WTA (1<<8) 93 #define MMCHS_PSTATE_DLA (1<<2) 94 #define MMCHS_PSTATE_DATI (1<<1) 95 #define MMCHS_PSTATE_CMDI (1<<0) 96 #define MMCHS_PSTATE_FMT "\20" \ 97 "\x098_CLEV" \ 98 "\x08b_BRE" \ 99 "\x08a_BWE" \ 100 "\x089_RTA" \ 101 "\x088_WTA" \ 102 "\x082_DLA" \ 103 "\x081_DATI" \ 104 "\x080_CMDI" 105 #define MMCHS_HCTL 0x128 106 #define MMCHS_HCTL_SDVS_SHIFT 9 107 #define MMCHS_HCTL_SDVS_MASK (0x7<<MMCHS_HCTL_SDVS_SHIFT) 108 #define MMCHS_HCTL_SDVS_V18 (0x5<<MMCHS_HCTL_SDVS_SHIFT) 109 #define MMCHS_HCTL_SDVS_V30 (0x6<<MMCHS_HCTL_SDVS_SHIFT) 110 #define MMCHS_HCTL_SDVS_V33 (0x7<<MMCHS_HCTL_SDVS_SHIFT) 111 #define MMCHS_HCTL_SDBP (1<<8) 112 #define MMCHS_HCTL_HSPE (1<<2) 113 #define MMCHS_HCTL_DTW (1<<1) 114 #define MMCHS_SYSCTL 0x12C 115 #define MMCHS_SYSCTL_SRD (1<<26) 116 #define MMCHS_SYSCTL_SRC (1<<25) 117 #define MMCHS_SYSCTL_SRA (1<<24) 118 #define MMCHS_SYSCTL_DTO_SH 16 119 #define MMCHS_SYSCTL_DTO_MASK 0x000f0000 120 #define MMCHS_SYSCTL_CLKD_SH 6 121 #define MMCHS_SYSCTL_CLKD_MASK 0x0000ffc0 122 #define MMCHS_SYSCTL_CEN (1<<2) 123 #define MMCHS_SYSCTL_ICS (1<<1) 124 #define MMCHS_SYSCTL_ICE (1<<0) 125 #define MMCHS_STAT 0x130 126 #define MMCHS_STAT_BADA (1<<29) 127 #define MMCHS_STAT_CERR (1<<28) 128 #define MMCHS_STAT_ACE (1<<24) 129 #define MMCHS_STAT_DEB (1<<22) 130 #define MMCHS_STAT_DCRC (1<<21) 131 #define MMCHS_STAT_DTO (1<<20) 132 #define MMCHS_STAT_CIE (1<<19) 133 #define MMCHS_STAT_CEB (1<<18) 134 #define MMCHS_STAT_CCRC (1<<17) 135 #define MMCHS_STAT_CTO (1<<16) 136 #define MMCHS_STAT_ERRI (1<<15) 137 #define MMCHS_STAT_OBI (1<<9) 138 #define MMCHS_STAT_CIRQ (1<<8) 139 #define MMCHS_STAT_BRR (1<<5) 140 #define MMCHS_STAT_BWR (1<<4) 141 #define MMCHS_STAT_BGE (1<<2) 142 #define MMCHS_STAT_TC (1<<1) 143 #define MMCHS_STAT_CC (1<<0) 144 #define MMCHS_STAT_FMT "\20" \ 145 "\x09d_BADA" \ 146 "\x09c_CERR" \ 147 "\x098_ACE" \ 148 "\x096_DEB" \ 149 "\x095_DCRC" \ 150 "\x094_DTO" \ 151 "\x093_CIE" \ 152 "\x092_CEB" \ 153 "\x091_CCRC" \ 154 "\x090_CTO" \ 155 "\x08f_ERRI" \ 156 "\x089_OBI" \ 157 "\x088_CIRQ" \ 158 "\x085_BRR" \ 159 "\x084_BWR" \ 160 "\x082_BGE" \ 161 "\x081_TC" \ 162 "\x080_CC" 163 #define MMCHS_IE 0x134 164 #define MMCHS_ISE 0x138 165 #define MMCHS_AC12 0x13C 166 #define MMCHS_CAPA 0x140 167 #define MMCHS_CAPA_VS18 (1 << 26) 168 #define MMCHS_CAPA_VS30 (1 << 25) 169 #define MMCHS_CAPA_VS33 (1 << 24) 170 #define MMCHS_CAPA_SRS (1 << 23) 171 #define MMCHS_CAPA_DS (1 << 22) 172 #define MMCHS_CAPA_HSS (1 << 21) 173 #define MMCHS_CAPA_MBL_SHIFT 16 174 #define MMCHS_CAPA_MBL_MASK (3 << MMCHS_CAPA_MBL_SHIFT) 175 #define MMCHS_CUR_CAPA 0x148 176 #define MMCHS_REV 0x1fc 177 178 #define SDHC_COMMAND_TIMEOUT hz 179 #define SDHC_BUFFER_TIMEOUT hz 180 #define SDHC_TRANSFER_TIMEOUT hz 181 182 void ommmc_attach(struct device *parent, struct device *self, void *args); 183 184 struct ommmc_softc { 185 struct device sc_dev; 186 bus_space_tag_t sc_iot; 187 bus_space_handle_t sc_ioh; 188 void *sc_ih; /* Interrupt handler */ 189 uint32_t sc_flags; 190 191 struct device *sdmmc; /* generic SD/MMC device */ 192 int clockbit; /* clock control bit */ 193 uint32_t clkbase; /* base clock frequency in KHz */ 194 int maxblklen; /* maximum block length */ 195 int flags; /* flags for this host */ 196 uint32_t ocr; /* OCR value from capabilities */ 197 uint32_t intr_status; /* soft interrupt status */ 198 uint32_t intr_error_status; /* */ 199 }; 200 201 202 /* Host controller functions called by the attachment driver. */ 203 int ommmc_host_found(struct ommmc_softc *, bus_space_tag_t, 204 bus_space_handle_t, bus_size_t, int); 205 void ommmc_power(int, void *); 206 void ommmc_shutdown(void *); 207 int ommmc_intr(void *); 208 209 /* RESET MODES */ 210 #define MMC_RESET_DAT 1 211 #define MMC_RESET_CMD 2 212 #define MMC_RESET_ALL (MMC_RESET_CMD|MMC_RESET_DAT) 213 214 /* flag values */ 215 #define SHF_USE_DMA 0x0001 216 217 #define HREAD4(sc, reg) \ 218 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 219 #define HWRITE4(sc, reg, val) \ 220 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 221 #define HSET4(sc, reg, bits) \ 222 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 223 #define HCLR4(sc, reg, bits) \ 224 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 225 226 int ommmc_host_reset(sdmmc_chipset_handle_t); 227 uint32_t ommmc_host_ocr(sdmmc_chipset_handle_t); 228 int ommmc_host_maxblklen(sdmmc_chipset_handle_t); 229 int ommmc_card_detect(sdmmc_chipset_handle_t); 230 int ommmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 231 int ommmc_bus_clock(sdmmc_chipset_handle_t, int); 232 void ommmc_card_intr_mask(sdmmc_chipset_handle_t, int); 233 void ommmc_card_intr_ack(sdmmc_chipset_handle_t); 234 void ommmc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 235 int ommmc_start_command(struct ommmc_softc *, struct sdmmc_command *); 236 int ommmc_wait_state(struct ommmc_softc *, uint32_t, uint32_t); 237 int ommmc_soft_reset(struct ommmc_softc *, int); 238 int ommmc_wait_intr(struct ommmc_softc *, int, int); 239 void ommmc_transfer_data(struct ommmc_softc *, struct sdmmc_command *); 240 void ommmc_read_data(struct ommmc_softc *, uint8_t *, int); 241 void ommmc_write_data(struct ommmc_softc *, uint8_t *, int); 242 243 /* #define SDHC_DEBUG */ 244 #ifdef SDHC_DEBUG 245 int ommmcdebug = 20; 246 #define DPRINTF(n,s) do { if ((n) <= ommmcdebug) printf s; } while (0) 247 void ommmc_dump_regs(struct ommmc_softc *); 248 #else 249 #define DPRINTF(n,s) do {} while(0) 250 #endif 251 252 struct sdmmc_chip_functions ommmc_functions = { 253 /* host controller reset */ 254 ommmc_host_reset, 255 /* host controller capabilities */ 256 ommmc_host_ocr, 257 ommmc_host_maxblklen, 258 /* card detection */ 259 ommmc_card_detect, 260 /* bus power and clock frequency */ 261 ommmc_bus_power, 262 ommmc_bus_clock, 263 /* command execution */ 264 ommmc_exec_command, 265 /* card interrupt */ 266 ommmc_card_intr_mask, 267 ommmc_card_intr_ack 268 }; 269 270 struct cfdriver ommmc_cd = { 271 NULL, "ommmc", DV_DULL 272 }; 273 274 struct cfattach ommmc_ca = { 275 sizeof(struct ommmc_softc), NULL, ommmc_attach 276 }; 277 278 void 279 ommmc_attach(struct device *parent, struct device *self, void *args) 280 { 281 struct ommmc_softc *sc = (struct ommmc_softc *) self; 282 struct armv7_attach_args *aa = args; 283 struct sdmmcbus_attach_args saa; 284 uint32_t caps; 285 286 sc->sc_iot = aa->aa_iot; 287 if (bus_space_map(sc->sc_iot, aa->aa_dev->mem[0].addr, 288 aa->aa_dev->mem[0].size, 0, &sc->sc_ioh)) 289 panic("%s: bus_space_map failed!", __func__); 290 291 printf("\n"); 292 293 /* Enable ICLKEN, FCLKEN? */ 294 prcm_enablemodule(PRCM_MMC0 + aa->aa_dev->unit); 295 296 sc->sc_ih = arm_intr_establish(aa->aa_dev->irq[0], IPL_SDMMC, 297 ommmc_intr, sc, DEVNAME(sc)); 298 if (sc->sc_ih == NULL) { 299 printf("%s: cannot map interrupt\n", DEVNAME(sc)); 300 goto err; 301 } 302 303 /* Controller Voltage Capabilities Initialization */ 304 HSET4(sc, MMCHS_CAPA, MMCHS_CAPA_VS18 | MMCHS_CAPA_VS30); 305 306 #ifdef SDHC_DEBUG 307 ommmc_dump_regs(sc); 308 #endif 309 310 /* 311 * Reset the host controller and enable interrupts. 312 */ 313 ommmc_host_reset(sc); 314 315 /* Determine host capabilities. */ 316 caps = HREAD4(sc, MMCHS_CAPA); 317 318 #if 0 319 /* we want this !! */ 320 /* Use DMA if the host system and the controller support it. */ 321 if (usedma && ISSET(caps, SDHC_DMA_SUPPORT)) 322 SET(sc->flags, SHF_USE_DMA); 323 #endif 324 325 /* 326 * Determine the base clock frequency. (2.2.24) 327 */ 328 329 sc->clkbase = 96 * 1000; 330 #if 0 331 if (SDHC_BASE_FREQ_KHZ(caps) != 0) 332 sc->clkbase = SDHC_BASE_FREQ_KHZ(caps); 333 sc->clkbase = SDHC_BASE_FREQ_KHZ(caps); 334 #endif 335 if (sc->clkbase == 0) { 336 /* The attachment driver must tell us. */ 337 printf("%s: base clock frequency unknown\n", DEVNAME(sc)); 338 goto err; 339 } else if (sc->clkbase < 10000 || sc->clkbase > 96000) { 340 /* SDHC 1.0 supports only 10-63 MHz. */ 341 printf("%s: base clock frequency out of range: %u MHz\n", 342 DEVNAME(sc), sc->clkbase / 1000); 343 goto err; 344 } 345 346 /* 347 * XXX Set the data timeout counter value according to 348 * capabilities. (2.2.15) 349 */ 350 351 352 /* 353 * Determine SD bus voltage levels supported by the controller. 354 */ 355 if (caps & MMCHS_CAPA_VS18) 356 SET(sc->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 357 if (caps & MMCHS_CAPA_VS30) 358 SET(sc->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 359 if (caps & MMCHS_CAPA_VS33) 360 SET(sc->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 361 362 /* 363 * Omap max block size is fixed (single buffer), could limit 364 * this to 512 for double buffering, but dont see the point. 365 */ 366 switch ((caps & MMCHS_CAPA_MBL_MASK) >> MMCHS_CAPA_MBL_SHIFT) { 367 case 0: 368 sc->maxblklen = 512; 369 break; 370 case 1: 371 sc->maxblklen = 1024; 372 break; 373 case 2: 374 sc->maxblklen = 2048; 375 break; 376 default: 377 sc->maxblklen = 512; 378 printf("invalid capability blocksize in capa %08x," 379 " trying 512\n", HREAD4(sc, MMCHS_CAPA)); 380 } 381 /* 382 * MMC does not support blksize > 512 yet 383 */ 384 sc->maxblklen = 512; 385 /* 386 * Attach the generic SD/MMC bus driver. (The bus driver must 387 * not invoke any chipset functions before it is attached.) 388 */ 389 bzero(&saa, sizeof(saa)); 390 saa.saa_busname = "sdmmc"; 391 saa.sct = &ommmc_functions; 392 saa.sch = sc; 393 saa.caps = 0; 394 if (caps & MMCHS_CAPA_HSS) 395 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 396 397 sc->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 398 if (sc->sdmmc == NULL) { 399 printf("%s: can't attach sdmmc\n", DEVNAME(sc)); 400 goto err; 401 } 402 403 return; 404 err: 405 if (sc->sc_ih != NULL) 406 arm_intr_disestablish(sc->sc_ih); 407 bus_space_unmap(sc->sc_iot, sc->sc_ioh, aa->aa_dev->mem[0].size); 408 } 409 410 411 /* 412 * Power hook established by or called from attachment driver. 413 */ 414 void 415 ommmc_power(int why, void *arg) 416 { 417 #if 0 418 struct ommmc_softc *sc = arg; 419 int n, i; 420 #endif 421 422 switch(why) { 423 case DVACT_SUSPEND: 424 /* XXX poll for command completion or suspend command 425 * in progress */ 426 427 /* Save the host controller state. */ 428 #if 0 429 for (i = 0; i < sizeof sc->regs; i++) 430 sc->regs[i] = HREAD1(sc, i); 431 #endif 432 break; 433 434 case DVACT_RESUME: 435 /* Restore the host controller state. */ 436 #if 0 437 (void)ommmc_host_reset(sc); 438 for (i = 0; i < sizeof sc->regs; i++) 439 HWRITE1(sc, i, sc->regs[i]); 440 #endif 441 break; 442 } 443 } 444 445 /* 446 * Shutdown hook established by or called from attachment driver. 447 */ 448 void 449 ommmc_shutdown(void *arg) 450 { 451 struct ommmc_softc *sc = arg; 452 453 /* XXX chip locks up if we don't disable it before reboot. */ 454 (void)ommmc_host_reset(sc); 455 } 456 457 /* 458 * Reset the host controller. Called during initialization, when 459 * cards are removed, upon resume, and during error recovery. 460 */ 461 int 462 ommmc_host_reset(sdmmc_chipset_handle_t sch) 463 { 464 struct ommmc_softc *sc = sch; 465 uint32_t imask; 466 int error; 467 int s; 468 469 s = splsdmmc(); 470 471 /* Disable all interrupts. */ 472 HWRITE4(sc, MMCHS_IE, 0); 473 HWRITE4(sc, MMCHS_ISE, 0); 474 475 /* 476 * Reset the entire host controller and wait up to 100ms for 477 * the controller to clear the reset bit. 478 */ 479 if ((error = ommmc_soft_reset(sc, MMCHS_SYSCTL_SRA)) != 0) { 480 splx(s); 481 return (error); 482 } 483 484 #if 0 485 HSET4(sc, MMCHS_CON, MMCHS_CON_INIT); 486 HWRITE4(sc, MMCHS_CMD, 0); 487 delay(100); /* should delay 1ms */ 488 489 HWRITE4(sc, MMCHS_STAT, MMCHS_STAT_CC); 490 HCLR4(sc, MMCHS_CON, MMCHS_CON_INIT); 491 HWRITE4(sc, MMCHS_STAT, ~0); 492 #endif 493 494 495 /* Set data timeout counter value to max for now. */ 496 HSET4(sc, MMCHS_SYSCTL, 0xe << MMCHS_SYSCTL_DTO_SH); 497 498 /* Enable interrupts. */ 499 imask = MMCHS_STAT_BRR | MMCHS_STAT_BWR | MMCHS_STAT_BGE | 500 MMCHS_STAT_TC | MMCHS_STAT_CC; 501 502 imask |= MMCHS_STAT_BADA | MMCHS_STAT_CERR | MMCHS_STAT_DEB | 503 MMCHS_STAT_DCRC | MMCHS_STAT_DTO | MMCHS_STAT_CIE | 504 MMCHS_STAT_CEB | MMCHS_STAT_CCRC | MMCHS_STAT_CTO; 505 506 HWRITE4(sc, MMCHS_IE, imask); 507 HWRITE4(sc, MMCHS_ISE, imask); 508 509 splx(s); 510 return (0); 511 } 512 513 uint32_t 514 ommmc_host_ocr(sdmmc_chipset_handle_t sch) 515 { 516 struct ommmc_softc *sc = sch; 517 return (sc->ocr); 518 } 519 520 int 521 ommmc_host_maxblklen(sdmmc_chipset_handle_t sch) 522 { 523 struct ommmc_softc *sc = sch; 524 return (sc->maxblklen); 525 } 526 527 /* 528 * Return non-zero if the card is currently inserted. 529 */ 530 int 531 ommmc_card_detect(sdmmc_chipset_handle_t sch) 532 { 533 struct ommmc_softc *sc = sch; 534 return !ISSET(HREAD4(sc, MMCHS_SYSTEST), MMCHS_SYSTEST_SDCD) ? 535 1 : 0; 536 } 537 538 /* 539 * Set or change SD bus voltage and enable or disable SD bus power. 540 * Return zero on success. 541 */ 542 int 543 ommmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 544 { 545 struct ommmc_softc *sc = sch; 546 uint32_t vdd; 547 uint32_t reg; 548 int s; 549 550 s = splsdmmc(); 551 552 /* 553 * Disable bus power before voltage change. 554 */ 555 HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_SDBP); 556 557 /* If power is disabled, reset the host and return now. */ 558 if (ocr == 0) { 559 splx(s); 560 (void)ommmc_host_reset(sc); 561 return (0); 562 } 563 564 /* 565 * Select the maximum voltage according to capabilities. 566 */ 567 ocr &= sc->ocr; 568 569 if (ISSET(ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V)) 570 vdd = MMCHS_HCTL_SDVS_V33; 571 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V)) 572 vdd = MMCHS_HCTL_SDVS_V30; 573 else if (ISSET(ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V)) 574 vdd = MMCHS_HCTL_SDVS_V18; 575 else { 576 /* Unsupported voltage level requested. */ 577 splx(s); 578 return (EINVAL); 579 } 580 581 /* 582 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 583 * voltage ramp until power rises. 584 */ 585 reg = HREAD4(sc, MMCHS_HCTL); 586 reg &= ~MMCHS_HCTL_SDVS_MASK; 587 reg |= vdd; 588 HWRITE4(sc, MMCHS_HCTL, reg); 589 590 HSET4(sc, MMCHS_HCTL, MMCHS_HCTL_SDBP); 591 delay(10000); /* XXX */ 592 593 /* 594 * The host system may not power the bus due to battery low, 595 * etc. In that case, the host controller should clear the 596 * bus power bit. 597 */ 598 if (!ISSET(HREAD4(sc, MMCHS_HCTL), MMCHS_HCTL_SDBP)) { 599 splx(s); 600 return (ENXIO); 601 } 602 603 splx(s); 604 return (0); 605 } 606 607 /* 608 * Return the smallest possible base clock frequency divisor value 609 * for the CLOCK_CTL register to produce `freq' (KHz). 610 */ 611 static int 612 ommmc_clock_divisor(struct ommmc_softc *sc, uint32_t freq) 613 { 614 int div; 615 uint32_t maxclk = MMCHS_SYSCTL_CLKD_MASK>>MMCHS_SYSCTL_CLKD_SH; 616 617 for (div = 1; div <= maxclk; div++) 618 if ((sc->clkbase / div) <= freq) { 619 return (div); 620 } 621 622 printf("divisor failure\n"); 623 /* No divisor found. */ 624 return (-1); 625 } 626 627 /* 628 * Set or change SDCLK frequency or disable the SD clock. 629 * Return zero on success. 630 */ 631 int 632 ommmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 633 { 634 int error = 0; 635 struct ommmc_softc *sc = sch; 636 uint32_t reg; 637 int s; 638 int div; 639 int timo; 640 641 s = splsdmmc(); 642 643 /* Must not stop the clock if commands are in progress. */ 644 for (timo = 1000; timo > 0; timo--) { 645 if (!ISSET(HREAD4(sc, MMCHS_PSTATE), 646 MMCHS_PSTATE_CMDI|MMCHS_PSTATE_DATI)) 647 break; 648 delay(10); 649 } 650 if (timo == 0) { 651 error = ETIMEDOUT; 652 goto ret; 653 } 654 655 /* 656 * Stop SD clock before changing the frequency. 657 */ 658 HCLR4(sc, MMCHS_SYSCTL, MMCHS_SYSCTL_CEN); 659 if (freq == SDMMC_SDCLK_OFF) 660 goto ret; 661 662 /* 663 * Set the minimum base clock frequency divisor. 664 */ 665 if ((div = ommmc_clock_divisor(sc, freq)) < 0) { 666 /* Invalid base clock frequency or `freq' value. */ 667 error = EINVAL; 668 goto ret; 669 } 670 reg = HREAD4(sc, MMCHS_SYSCTL); 671 reg &= ~MMCHS_SYSCTL_CLKD_MASK; 672 reg |= div << MMCHS_SYSCTL_CLKD_SH; 673 HWRITE4(sc, MMCHS_SYSCTL, reg); 674 675 /* 676 * Start internal clock. Wait 10ms for stabilization. 677 */ 678 HSET4(sc, MMCHS_SYSCTL, MMCHS_SYSCTL_ICE); 679 for (timo = 1000; timo > 0; timo--) { 680 if (ISSET(HREAD4(sc, MMCHS_SYSCTL), MMCHS_SYSCTL_ICS)) 681 break; 682 delay(10); 683 } 684 if (timo == 0) { 685 error = ETIMEDOUT; 686 goto ret; 687 } 688 689 /* 690 * Enable SD clock. 691 */ 692 HSET4(sc, MMCHS_SYSCTL, MMCHS_SYSCTL_CEN); 693 ret: 694 splx(s); 695 return (error); 696 } 697 698 void 699 ommmc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 700 { 701 /* - this is SDIO card interrupt */ 702 struct ommmc_softc *sc = sch; 703 704 if (enable) { 705 HSET4(sc, MMCHS_IE, MMCHS_STAT_CIRQ); 706 HSET4(sc, MMCHS_ISE, MMCHS_STAT_CIRQ); 707 } else { 708 HCLR4(sc, MMCHS_IE, MMCHS_STAT_CIRQ); 709 HCLR4(sc, MMCHS_ISE, MMCHS_STAT_CIRQ); 710 } 711 } 712 713 void 714 ommmc_card_intr_ack(sdmmc_chipset_handle_t sch) 715 { 716 struct ommmc_softc *sc = sch; 717 718 HWRITE4(sc, MMCHS_STAT, MMCHS_STAT_CIRQ); 719 } 720 721 int 722 ommmc_wait_state(struct ommmc_softc *sc, uint32_t mask, uint32_t value) 723 { 724 uint32_t state; 725 int timeout; 726 727 state = HREAD4(sc, MMCHS_PSTATE); 728 DPRINTF(3,("%s: wait_state %x %x %x(state=%b)\n", DEVNAME(sc), 729 mask, value, state, state, MMCHS_PSTATE_FMT)); 730 for (timeout = 1000; timeout > 0; timeout--) { 731 if (((state = HREAD4(sc, MMCHS_PSTATE)) & mask) == value) 732 return (0); 733 delay(10); 734 } 735 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(sc), 736 value, state, MMCHS_PSTATE_FMT)); 737 return (ETIMEDOUT); 738 } 739 740 void 741 ommmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 742 { 743 struct ommmc_softc *sc = sch; 744 int error; 745 746 /* 747 * Start the MMC command, or mark `cmd' as failed and return. 748 */ 749 error = ommmc_start_command(sc, cmd); 750 if (error != 0) { 751 cmd->c_error = error; 752 SET(cmd->c_flags, SCF_ITSDONE); 753 return; 754 } 755 756 /* 757 * Wait until the command phase is done, or until the command 758 * is marked done for any other reason. 759 */ 760 if (!ommmc_wait_intr(sc, MMCHS_STAT_CC, SDHC_COMMAND_TIMEOUT)) { 761 cmd->c_error = ETIMEDOUT; 762 SET(cmd->c_flags, SCF_ITSDONE); 763 return; 764 } 765 766 /* 767 * The host controller removes bits [0:7] from the response 768 * data (CRC) and we pass the data up unchanged to the bus 769 * driver (without padding). 770 */ 771 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 772 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 773 uint32_t v0,v1,v2,v3; 774 v0 = HREAD4(sc, MMCHS_RSP10); 775 v1 = HREAD4(sc, MMCHS_RSP32); 776 v2 = HREAD4(sc, MMCHS_RSP54); 777 v3 = HREAD4(sc, MMCHS_RSP76); 778 779 cmd->c_resp[0] = (v0 >> 8) | ((v1 & 0xff) << 24); 780 cmd->c_resp[1] = (v1 >> 8) | ((v2 & 0xff) << 24); 781 cmd->c_resp[2] = (v2 >> 8) | ((v3 & 0xff) << 24); 782 cmd->c_resp[3] = v3 >> 8; 783 #ifdef SDHC_DEBUG 784 printf("resp[0] 0x%08x\nresp[1] 0x%08x\nresp[2] 0x%08x\nresp[3] 0x%08x\n", cmd->c_resp[0], cmd->c_resp[1], cmd->c_resp[2], cmd->c_resp[3]); 785 #endif 786 } else { 787 cmd->c_resp[0] = HREAD4(sc, MMCHS_RSP10); 788 #ifdef SDHC_DEBUG 789 printf("resp[0] 0x%08x\n", cmd->c_resp[0]); 790 #endif 791 } 792 } 793 794 /* 795 * If the command has data to transfer in any direction, 796 * execute the transfer now. 797 */ 798 if (cmd->c_error == 0 && cmd->c_data != NULL) 799 ommmc_transfer_data(sc, cmd); 800 801 #if 0 802 /* Turn off the LED. */ 803 HCLR1(sc, SDHC_HOST_CTL, SDHC_LED_ON); 804 #endif 805 806 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n", 807 DEVNAME(sc), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 808 SET(cmd->c_flags, SCF_ITSDONE); 809 } 810 811 int 812 ommmc_start_command(struct ommmc_softc *sc, struct sdmmc_command *cmd) 813 { 814 uint32_t blksize = 0; 815 uint32_t blkcount = 0; 816 uint32_t command; 817 int error; 818 int s; 819 820 DPRINTF(1,("%s: start cmd %u arg=%#x data=%#x dlen=%d flags=%#x " 821 "proc=\"%s\"\n", DEVNAME(sc), cmd->c_opcode, cmd->c_arg, 822 cmd->c_data, cmd->c_datalen, cmd->c_flags, curproc ? 823 curproc->p_comm : "")); 824 825 /* 826 * The maximum block length for commands should be the minimum 827 * of the host buffer size and the card buffer size. (1.7.2) 828 */ 829 830 /* Fragment the data into proper blocks. */ 831 if (cmd->c_datalen > 0) { 832 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 833 blkcount = cmd->c_datalen / blksize; 834 if (cmd->c_datalen % blksize > 0) { 835 /* XXX: Split this command. (1.7.4) */ 836 printf("%s: data not a multiple of %d bytes\n", 837 DEVNAME(sc), blksize); 838 return (EINVAL); 839 } 840 } 841 842 /* Check limit imposed by 9-bit block count. (1.7.2) */ 843 if (blkcount > MMCHS_BLK_NBLK_MAX) { 844 printf("%s: too much data\n", DEVNAME(sc)); 845 return (EINVAL); 846 } 847 848 /* Prepare transfer mode register value. (2.2.5) */ 849 command = 0; 850 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 851 command |= MMCHS_CMD_DDIR; 852 if (blkcount > 0) { 853 command |= MMCHS_CMD_BCE; 854 if (blkcount > 1) { 855 command |= MMCHS_CMD_MSBS; 856 /* XXX only for memory commands? */ 857 command |= MMCHS_CMD_ACEN; 858 } 859 } 860 #ifdef notyet 861 if (ISSET(sc->flags, SHF_USE_DMA)) 862 command |= MMCHS_CMD_DE; 863 #endif 864 865 /* 866 * Prepare command register value. (2.2.6) 867 */ 868 command |= (cmd->c_opcode << MMCHS_CMD_INDX_SHIFT) & 869 MMCHS_CMD_INDX_SHIFT_MASK; 870 871 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 872 command |= MMCHS_CMD_CCCE; 873 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 874 command |= MMCHS_CMD_CICE; 875 if (cmd->c_data != NULL) 876 command |= MMCHS_CMD_DP; 877 878 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 879 command |= MMCHS_CMD_RESP_NONE; 880 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 881 command |= MMCHS_CMD_RESP136; 882 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 883 command |= MMCHS_CMD_RESP48B; 884 else 885 command |= MMCHS_CMD_RESP48; 886 887 /* Wait until command and data inhibit bits are clear. (1.5) */ 888 if ((error = ommmc_wait_state(sc, MMCHS_PSTATE_CMDI, 0)) != 0) 889 return (error); 890 891 s = splsdmmc(); 892 893 #if 0 894 /* Alert the user not to remove the card. */ 895 HSET1(sc, SDHC_HOST_CTL, SDHC_LED_ON); 896 #endif 897 898 /* XXX: Set DMA start address if SHF_USE_DMA is set. */ 899 900 DPRINTF(1,("%s: cmd=%#x blksize=%d blkcount=%d\n", 901 DEVNAME(sc), command, blksize, blkcount)); 902 903 /* 904 * Start a CPU data transfer. Writing to the high order byte 905 * of the SDHC_COMMAND register triggers the SD command. (1.5) 906 */ 907 HWRITE4(sc, MMCHS_BLK, (blkcount << MMCHS_BLK_NBLK_SHIFT) | 908 (blksize << MMCHS_BLK_BLEN_SHIFT)); 909 HWRITE4(sc, MMCHS_ARG, cmd->c_arg); 910 HWRITE4(sc, MMCHS_CMD, command); 911 912 splx(s); 913 return (0); 914 } 915 916 void 917 ommmc_transfer_data(struct ommmc_softc *sc, struct sdmmc_command *cmd) 918 { 919 uint8_t *datap = cmd->c_data; 920 int i, datalen; 921 int mask; 922 int error; 923 924 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 925 MMCHS_PSTATE_BRE : MMCHS_PSTATE_BWE; 926 error = 0; 927 datalen = cmd->c_datalen; 928 929 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(sc), 930 MMC_R1(cmd->c_resp), datalen)); 931 932 while (datalen > 0) { 933 if (!ommmc_wait_intr(sc, MMCHS_STAT_BRR| MMCHS_STAT_BWR, 934 SDHC_BUFFER_TIMEOUT)) { 935 error = ETIMEDOUT; 936 break; 937 } 938 939 if ((error = ommmc_wait_state(sc, mask, mask)) != 0) 940 break; 941 942 i = MIN(datalen, cmd->c_blklen); 943 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 944 ommmc_read_data(sc, datap, i); 945 else 946 ommmc_write_data(sc, datap, i); 947 948 datap += i; 949 datalen -= i; 950 } 951 952 if (error == 0 && !ommmc_wait_intr(sc, MMCHS_STAT_TC, 953 SDHC_TRANSFER_TIMEOUT)) 954 error = ETIMEDOUT; 955 956 if (error != 0) 957 cmd->c_error = error; 958 SET(cmd->c_flags, SCF_ITSDONE); 959 960 DPRINTF(1,("%s: data transfer done (error=%d)\n", 961 DEVNAME(sc), cmd->c_error)); 962 } 963 964 void 965 ommmc_read_data(struct ommmc_softc *sc, uint8_t *datap, int datalen) 966 { 967 while (datalen > 3) { 968 *(uint32_t *)datap = HREAD4(sc, MMCHS_DATA); 969 datap += 4; 970 datalen -= 4; 971 } 972 if (datalen > 0) { 973 uint32_t rv = HREAD4(sc, MMCHS_DATA); 974 do { 975 *datap++ = rv & 0xff; 976 rv = rv >> 8; 977 } while (--datalen > 0); 978 } 979 } 980 981 void 982 ommmc_write_data(struct ommmc_softc *sc, uint8_t *datap, int datalen) 983 { 984 while (datalen > 3) { 985 DPRINTF(3,("%08x\n", *(uint32_t *)datap)); 986 HWRITE4(sc, MMCHS_DATA, *((uint32_t *)datap)); 987 datap += 4; 988 datalen -= 4; 989 } 990 if (datalen > 0) { 991 uint32_t rv = *datap++; 992 if (datalen > 1) 993 rv |= *datap++ << 8; 994 if (datalen > 2) 995 rv |= *datap++ << 16; 996 DPRINTF(3,("rv %08x\n", rv)); 997 HWRITE4(sc, MMCHS_DATA, rv); 998 } 999 } 1000 1001 /* Prepare for another command. */ 1002 int 1003 ommmc_soft_reset(struct ommmc_softc *sc, int mask) 1004 { 1005 1006 int timo; 1007 1008 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(sc), mask)); 1009 1010 HSET4(sc, MMCHS_SYSCTL, mask); 1011 delay(10); 1012 for (timo = 1000; timo > 0; timo--) { 1013 if (!ISSET(HREAD4(sc, MMCHS_SYSCTL), mask)) 1014 break; 1015 delay(10); 1016 } 1017 if (timo == 0) { 1018 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(sc), 1019 HREAD4(sc, MMCHS_SYSCTL))); 1020 return (ETIMEDOUT); 1021 } 1022 1023 return (0); 1024 } 1025 1026 int 1027 ommmc_wait_intr(struct ommmc_softc *sc, int mask, int timo) 1028 { 1029 int status; 1030 int s; 1031 1032 mask |= MMCHS_STAT_ERRI; 1033 1034 s = splsdmmc(); 1035 status = sc->intr_status & mask; 1036 while (status == 0) { 1037 if (tsleep(&sc->intr_status, PWAIT, "hcintr", timo) 1038 == EWOULDBLOCK) { 1039 status |= MMCHS_STAT_ERRI; 1040 break; 1041 } 1042 status = sc->intr_status & mask; 1043 } 1044 sc->intr_status &= ~status; 1045 1046 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(sc), status, 1047 sc->intr_error_status)); 1048 1049 /* Command timeout has higher priority than command complete. */ 1050 if (ISSET(status, MMCHS_STAT_ERRI)) { 1051 sc->intr_error_status = 0; 1052 (void)ommmc_soft_reset(sc, MMCHS_SYSCTL_SRC|MMCHS_SYSCTL_SRD); 1053 status = 0; 1054 } 1055 1056 splx(s); 1057 return (status); 1058 } 1059 1060 /* 1061 * Established by attachment driver at interrupt priority IPL_SDMMC. 1062 */ 1063 int 1064 ommmc_intr(void *arg) 1065 { 1066 struct ommmc_softc *sc = arg; 1067 1068 uint32_t status; 1069 1070 /* Find out which interrupts are pending. */ 1071 status = HREAD4(sc, MMCHS_STAT); 1072 1073 /* Acknowledge the interrupts we are about to handle. */ 1074 HWRITE4(sc, MMCHS_STAT, status); 1075 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(sc), 1076 status, MMCHS_STAT_FMT)); 1077 1078 /* 1079 * Service error interrupts. 1080 */ 1081 if (ISSET(status, MMCHS_STAT_ERRI)) { 1082 if (ISSET(status, MMCHS_STAT_CTO| 1083 MMCHS_STAT_DTO)) { 1084 sc->intr_status |= status; 1085 sc->intr_error_status |= status & 0xffff0000; 1086 wakeup(&sc->intr_status); 1087 } 1088 } 1089 1090 #if 0 1091 /* 1092 * Wake up the sdmmc event thread to scan for cards. 1093 */ 1094 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) 1095 ommmc_needs_discover(sc->sdmmc); 1096 #endif 1097 1098 /* 1099 * Wake up the blocking process to service command 1100 * related interrupt(s). 1101 */ 1102 if (ISSET(status, MMCHS_STAT_BRR| 1103 MMCHS_STAT_BWR|MMCHS_STAT_TC| 1104 MMCHS_STAT_CC)) { 1105 sc->intr_status |= status; 1106 wakeup(&sc->intr_status); 1107 } 1108 1109 /* 1110 * Service SD card interrupts. 1111 */ 1112 if (ISSET(status, MMCHS_STAT_CIRQ)) { 1113 DPRINTF(0,("%s: card interrupt\n", DEVNAME(sc))); 1114 HCLR4(sc, MMCHS_STAT, MMCHS_STAT_CIRQ); 1115 sdmmc_card_intr(sc->sdmmc); 1116 } 1117 return 1; 1118 } 1119