1 /* $OpenBSD: iomod.h,v 1.9 2001/12/02 04:10:25 mickey Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Michael Shalayeff. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 30 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 1990 mt Xinu, Inc. All rights reserved. 35 * Copyright (c) 1990,1991,1992,1994 University of Utah. All rights reserved. 36 * 37 * Permission to use, copy, modify and distribute this software is hereby 38 * granted provided that (1) source code retains these copyright, permission, 39 * and disclaimer notices, and (2) redistributions including binaries 40 * reproduce the notices in supporting documentation, and (3) all advertising 41 * materials mentioning features or use of this software display the following 42 * acknowledgement: ``This product includes software developed by the 43 * Computer Systems Laboratory at the University of Utah.'' 44 * 45 * Copyright (c) 1990 mt Xinu, Inc. 46 * This file may be freely distributed in any form as long as 47 * this copyright notice is included. 48 * MTXINU, THE UNIVERSITY OF UTAH, AND CSL PROVIDE THIS SOFTWARE ``AS 49 * IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, 50 * WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND 51 * FITNESS FOR A PARTICULAR PURPOSE. 52 * 53 * CSL requests users of this software to return to csl-dist@cs.utah.edu any 54 * improvements that they make and grant CSL redistribution rights. 55 * 56 * Utah $Hdr: iomod.h 1.6 94/12/14$ 57 */ 58 59 #ifndef _MACHINE_IOMOD_H_ 60 #define _MACHINE_IOMOD_H_ 61 62 #include <machine/pdc.h> 63 64 /* 65 * Structures and definitions for I/O Modules on HP-PA (9000/800). 66 * 67 * Memory layout: 68 * 69 * 0x00000000 +---------------------------------+ 70 * | Page Zero | 71 * 0x00000800 + - - - - - - - - - - - - - - - - + 72 * | | 73 * | | 74 * | Memory Address Space | 75 * | | 76 * | | 77 * 0xEF000000 +---------------------------------+ 78 * | | 79 * | PDC Address Space | 80 * | | 81 * 0xF1000000 +---------------------------------+ 82 * | | 83 * | | 84 * | I/O Address Space | 85 * | | 86 * | | 87 * 0xFFF80000 + - - - - - - - - - - - - - - - - + 88 * | Fixed Physical Address Space | 89 * 0xFFFC0000 + - - - - - - - - - - - - - - - - + 90 * | Local Broadcast Address Space | 91 * 0xFFFE0000 + - - - - - - - - - - - - - - - - + 92 * | Global Broadcast Address Space | 93 * 0xFFFFFFFF +---------------------------------+ 94 * 95 * "Memory Address Space" is used by memory modules, 96 * "Page Zero" is described below. 97 * "PDC Address Space" is used by Processor-Dependent Code. 98 * "I/O Address Space" is used by I/O modules (and is not cached), 99 * "Fixed Physical" is used by modules on the central bus, 100 * "Local Broadcast" is used to reach all modules on the same bus, and 101 * "Global Broadcast" is used to reach all modules (thru bus converters). 102 * 103 * SPA space (see below) ranges from 0xF1000000 thru 0xFFFC0000. 104 */ 105 106 #define HPPA_IOBEGIN 0xF0000000 107 #define HPPA_IOLEN 0x10000000 108 #define PDC_ADDR 0xEF000000 /* explained above */ 109 #define IO_ADDR 0xF1000000 110 #define SGC_SLOT1 0xF4000000 /* (hp700) */ 111 #define SGC_SLOT2 0xF8000000 /* (hp700) */ 112 #define SGC_SIZE 0x02000000 /* (hp700) */ 113 #define FP_ADDR 0xFFF80000 114 #define LBCAST_ADDR 0xFFFC0000 115 #define GBCAST_ADDR 0xFFFE0000 116 117 #define PDC_LOW PDC_ADDR /* define some ranges */ 118 #define PDC_HIGH IO_ADDR 119 #define FPA_LOW FP_ADDR 120 #define FPA_HIGH LBCAST_ADDR 121 #define SPA_LOW IO_ADDR 122 #define SPA_HIGH LBCAST_ADDR 123 #define SGC_LOW SGC_SLOT1 124 #define SGC_HIGH (SGC_SLOT2+SGC_SIZE) 125 126 #define FPA_IOMOD ((FPA_HIGH-FPA_LOW)/sizeof(struct iomod)) 127 #define MAXMODBUS ((int)(FPA_IOMOD)) /* maximum modules/bus */ 128 129 /* size of HPA space for any device */ 130 #define IOMOD_HPASIZE 0x1000 131 132 /* ASP prom offset for an lan stattion id */ 133 #define ASP_PROM (0xf0810000) 134 135 /* offset to the device-specific registers, 136 * basically sizeof(struct iomod) (see later) 137 */ 138 #define IOMOD_DEVOFFSET 0x800 139 140 #if !defined(_LOCORE) 141 142 /* 143 * The first 2K of Soft Physical Address space on the Initial Memory Module 144 * is aptly called "page zero". The following structure defines the format 145 * of page zero. Individual members of this structure should be accessed 146 * as "PAGE0->member". 147 */ 148 149 #define PAGE0 ((struct pagezero *)0) /* can't get any lower than this! */ 150 151 struct pagezero { 152 /* [0x000] Initialize Vectors */ 153 int ivec_special; /* must be zero */ 154 int (*ivec_mempf)__P((void)); /* powerfail recovery software */ 155 int (*ivec_toc)__P((void)); /* exec'd after Transfer Of Control */ 156 u_int ivec_toclen; /* bytes of ivec_toc code */ 157 int (*ivec_rendz)__P((void)); /* exec'd after Rendezvous Signal */ 158 u_int ivec_mempflen; /* bytes of ivec_mempf code */ 159 u_int ivec_resv[2]; /* (reserved) */ 160 u_int ivec_mbz; /* must be zero */ 161 u_int ivec_resv2[7]; /* (reserved) */ 162 163 /* [0x040] Processor Dependent */ 164 union { 165 u_int pd_Resv1[112]; /* (reserved) processor dependent */ 166 struct { /* Viper-specific data */ 167 u_int v_Resv1[39]; 168 u_int v_Ctrlcpy; /* copy of Viper `vi_control' */ 169 u_int v_Resv2[72]; 170 } pd_Viper; 171 } pz_Pdep; 172 173 /* [0x200] IODC Data Area Descriptors 174 use PDC_ALLOC to allocate these memory regions */ 175 u_int iodc_cons_base; /* */ 176 u_int iodc_cons_size; /* */ 177 u_int iodc_kbrd_base; /* */ 178 u_int iodc_kbrd_size; /* */ 179 u_int iodc_boot_base; /* */ 180 u_int iodc_boot_size; /* */ 181 182 /* [0x218] */ 183 u_int resv1[0x41]; 184 185 /* [0x31C] Capability Flags */ 186 u_int cap_flags; /* system capabitlities */ 187 #define HPPA_CAP_WIDESCSI 0x00000001 188 189 /* [0x320] Keyboard Extensions */ 190 u_int kbrd_ext[2]; 191 192 /* [0x328] Boot Device Extensions */ 193 u_int boot_ext[2]; 194 195 /* [0x330] Console/Display Extensions */ 196 u_int cons_ext[2]; 197 198 /* [0x338] Initial Memory Module Extensions */ 199 u_int imm_ext[2]; 200 201 /* [0x340] Memory Configuration */ 202 u_int memc_cont_l; /* memc_cont low part */ 203 u_int memc_phsize_l; /* memc_phsize low part */ 204 u_int memc_adsize_l; /* memc_adsize low part */ 205 u_int memc_resv; /* (reserved) */ 206 u_int memc_cont; /* bytes of contiguous valid memory */ 207 u_int memc_phsize; /* bytes of valid physical memory */ 208 u_int memc_adsize; /* bytes of SPA space used by PDC */ 209 u_int memc_hpa_h; /* HPA of CPU (high) */ 210 211 /* [0x360] Miscellaneous */ 212 struct boot_err mem_be[8]; /* boot errors (see above) */ 213 u_int mem_free; /* first free phys. memory location */ 214 u_int mem_hpa; /* HPA of CPU */ 215 int (*mem_pdc)__P((void)); /* PDC entry point */ 216 u_int mem_10msec; /* # of Interval Timer ticks in 10msec*/ 217 218 /* [0x390] Initial Memory Module */ 219 struct iomod *imm_hpa; /* HPA of Initial Memory module */ 220 u_int imm_soft_boot; /* 0 == hard boot, 1 == soft boot */ 221 u_int imm_spa_size; /* bytes of SPA in IMM */ 222 u_int imm_max_mem; /* bytes of mem in IMM (<= spa_size) */ 223 224 /* [0x3A0] Boot Console/Display, Device, and Keyboard */ 225 struct pz_device mem_cons; /* description of console device */ 226 struct pz_device mem_boot; /* description of boot device */ 227 struct pz_device mem_kbd; /* description of keyboard device */ 228 229 /* [0x430] Reserved */ 230 u_int resv2[116]; /* (reserved) */ 231 232 /* [0x600] Processor Dependent */ 233 u_int pd_resv2[128]; /* (reserved) processor dependent */ 234 }; 235 #define v_ctrlcpy pz_Pdep.pd_Viper.v_Ctrlcpy 236 237 238 /* 239 * Every module has 4K-bytes of address space associated with it. 240 * A Hard Physical Address (HPA) can be broken down as follows. 241 * 242 * Since this is an I/O space, the high 4 bits are always 1's. 243 * 244 * The "flex" address specifies which bus a module is on; there are 245 * 256K-bytes of HPA space for each bus, however only values from 246 * 64 - 1022 are valid for the "flex" field (1022 designates the 247 * central bus). The "flex" addr is set at bus configuration time. 248 * 249 * The "fixed" address specifies a particular module on the same 250 * bus (i.e. among modules with the same "flex" address). This 251 * value can also be found in "device_path.dp_mod" in "pdc.h". 252 * 253 * A modules HPA space consists of 2 pages; the "up" bit specifies 254 * which of these pages is being addressed. In general, the lower 255 * page is privileged and the upper page it module-type dependent. 256 * 257 */ 258 259 struct hpa { 260 u_int hpa_ones: 4, /* must be 1's; this is an I/O space addr */ 261 hpa_flex:10, /* bus address for this module */ 262 hpa_fixed:6, /* location of module on bus */ 263 hpa_up : 1, /* 1 == upper page, 0 == lower page */ 264 hpa_set : 5, /* register set */ 265 hpa_reg : 4, /* register number within a register set */ 266 hpa_zeros:2; /* must be 0's; addrs are word aligned */ 267 }; 268 269 270 /* 271 * Certain modules require additional memory (i.e. more than that 272 * provided by the HPA space). A Soft Physical Address (SPA) can be 273 * broken down as follows, on a module-type specific basis (either 274 * Memory SPA or I/O SPA). 275 * 276 * SPA space must be a power of 2, and aligned accordingly. The IODC 277 * provides all information needed by software to configure SPA space 278 * for a particular module. 279 */ 280 281 struct memspa { 282 u_int spa_page:21, /* page of memory */ 283 spa_off :11; /* offset into memory page */ 284 }; 285 286 struct iospa { 287 u_int spa_ones: 4, /* must be 1's; this is an I/O space addr */ 288 spa_iopg:17, /* page in I/O address space */ 289 spa_set : 5, /* register set */ 290 spa_reg : 4, /* register number within a register set */ 291 spa_mode: 2; /* aligned according to bus transaction mode */ 292 }; 293 294 295 /* 296 * It is possible to send a command to all modules on a particular bus 297 * (local broadcast), or all modules (global broadcast). A Broadcast 298 * Physical Address (BPA) can be broken down as follows. 299 * 300 * Read and Clear transactions are not allowed in BPA space. All pages 301 * in BPA space are privileged. 302 */ 303 304 struct bpa { 305 u_int bpa_ones:14, /* must be 1's; this is in BPA space */ 306 bpa_gbl : 1, /* 0 == local, 1 == global broadcast */ 307 bpa_page: 6, /* page in local/global BPA space */ 308 bpa_set : 5, /* register set */ 309 bpa_reg : 4, /* register number within a register set */ 310 bpa_zeros:2; /* must be 0's; addrs are word aligned */ 311 }; 312 313 314 /* 315 * All I/O and Memory modules have 4K-bytes of HPA space associated with 316 * it (described above), however not all modules implement every register. 317 * The first 2K-bytes of registers are "priviliged". 318 * 319 * (WO) == Write Only, (RO) == Read Only 320 */ 321 322 struct iomod { 323 /* SRS (Supervisor Register Set) */ 324 u_int io_eir; /* (WO) interrupt CPU; set bits in EIR CR */ 325 u_int io_eim; /* (WO) External Interrupt Message address */ 326 u_int io_dc_rw; /* write address of IODC to read IODC data */ 327 u_int io_ii_rw; /* read/clear external intrpt msg (bit-26) */ 328 caddr_t io_dma_link; /* pointer to "next quad" in DMA chain */ 329 u_int io_dma_command; /* (RO) chain command to exec on "next quad" */ 330 caddr_t io_dma_address; /* (RO) start of DMA */ 331 u_int io_dma_count; /* (RO) number of bytes remaining to xfer */ 332 caddr_t io_flex; /* (WO) HPA flex addr, LSB: bus master flag */ 333 caddr_t io_spa; /* (WO) SPA space; 0-20:addr, 24-31:iodc_spa */ 334 u_int resv1[2]; /* (reserved) */ 335 u_int io_command; /* (WO) module commands (see below) */ 336 u_int io_status; /* (RO) error returns (see below) */ 337 u_int io_control; /* memory err logging (bit-9), bc forwarding */ 338 u_int io_test; /* (RO) self-test information */ 339 /* ARS (Auxiliary Register Set) */ 340 u_int io_err_sadd; /* (RO) slave bus error or memory error addr */ 341 caddr_t chain_addr; /* start address of chain RAM */ 342 u_int sub_mask_clr; /* ignore intrpts on sub-channel (bitmask) */ 343 u_int sub_mask_set; /* service intrpts on sub-channel (bitmask) */ 344 u_int diagnostic; /* diagnostic use (reserved) */ 345 u_int resv2[2]; /* (reserved) */ 346 caddr_t nmi_address; /* address to send data to when NMI detected */ 347 caddr_t nmi_data; /* NMI data to be sent */ 348 u_int resv3[3]; /* (reserved) */ 349 u_int io_mem_low; /* bottom of memory address range */ 350 u_int io_mem_high; /* top of memory address range */ 351 u_int io_io_low; /* bottom of I/O HPA address Range */ 352 u_int io_io_high; /* top of I/O HPA address Range */ 353 354 u_int priv_trs[160]; /* TRSes (Type-dependent Reg Sets) */ 355 356 u_int priv_hvrs[320]; /* HVRSes (HVERSION-dependent Register Sets) */ 357 358 u_int hvrs[512]; /* HVRSes (HVERSION-dependent Register Sets) */ 359 }; 360 #endif /* !_LOCORE */ 361 362 /* primarily for a "reboot" and "_rtt" routines */ 363 #define iomod_command (4*12) 364 365 /* io_flex */ 366 #define DMA_ENABLE 0x1 /* flex register enable DMA bit */ 367 368 /* io_spa */ 369 #define IOSPA(spa,iodc_data) \ 370 ((volatile caddr_t) \ 371 (spa | iodc_data.iodc_spa_shift | iodc_data.iodc_spa_enb << 5 | \ 372 iodc_data.iodc_spa_pack << 6 | iodc_data.iodc_spa_io << 7)) 373 374 /* io_command */ 375 #define CMD_STOP 0 /* halt any I/O, enable diagnostic access */ 376 #define CMD_FLUSH 1 /* abort DMA */ 377 #define CMD_CHAIN 2 /* initiate DMA */ 378 #define CMD_CLEAR 3 /* clear errors */ 379 #define CMD_RESET 5 /* reset any module */ 380 381 /* io_status */ 382 #define IO_ERR_MEM_SL 0x10000 /* SPA space lost or corrupted */ 383 #define IO_ERR_MEM_SE 0x00200 /* severity: minor */ 384 #define IO_ERR_MEM_HE 0x00100 /* severity: affects invalid parts */ 385 #define IO_ERR_MEM_FE 0x00080 /* severity: bad */ 386 #define IO_ERR_MEM_RY 0x00040 /* IO_COMMAND register ready for command */ 387 #define IO_ERR_DMA_DG 0x00010 /* module in diagnostic mode */ 388 #define IO_ERR_DMA_PW 0x00004 /* Power Failing */ 389 #define IO_ERR_DMA_PL 0x00002 /* Power Lost */ 390 #define IO_ERR_VAL(x) (((x) >> 10) & 0x3f) 391 #define IO_ERR_DEPEND 0 /* unspecified error */ 392 #define IO_ERR_SPA 1 /* (module-type specific) */ 393 #define IO_ERR_INTERNAL 2 /* (module-type specific) */ 394 #define IO_ERR_MODE 3 /* invlaid mode or address space mapping */ 395 #define IO_ERR_ERROR_M 4 /* bus error (master detect) */ 396 #define IO_ERR_DPARITY_S 5 /* data parity (slave detect) */ 397 #define IO_ERR_PROTO_M 6 /* protocol error (master detect) */ 398 #define IO_ERR_ADDRESS 7 /* no slave acknowledgement in transaction */ 399 #define IO_ERR_MORE 8 /* device transfered more data than expected */ 400 #define IO_ERR_LESS 9 /* device transfered less data than expected */ 401 #define IO_ERR_SAPARITY 10 /* slave addrss phase parity */ 402 #define IO_ERR_MAPARITY 11 /* master address phase parity */ 403 #define IO_ERR_MDPARITY 12 /* mode phase parity */ 404 #define IO_ERR_STPARITY 13 /* status phase parity */ 405 #define IO_ERR_CMD 14 /* unimplemented I/O Command */ 406 #define IO_ERR_BUS 15 /* generic bus error */ 407 #define IO_ERR_CORR 24 /* correctable memory error */ 408 #define IO_ERR_UNCORR 25 /* uncorrectable memory error */ 409 #define IO_ERR_MAP 26 /* equivalent to IO_ERR_CORR */ 410 #define IO_ERR_LINK 28 /* Bus Converter "link" (connection) error */ 411 #define IO_ERR_CCMD 32 /* Illegal DMA command */ 412 #define IO_ERR_ERROR_S 52 /* bus error (slave detect) */ 413 #define IO_ERR_DPARITY_M 53 /* data parity (master detect) */ 414 #define IO_ERR_PROTOCOL 54 /* protocol error (slave detect) */ 415 #define IO_ERR_SELFTEST 58 /* (module-type specific) */ 416 #define IO_ERR_BUSY 59 /* slave was busy too often or too long */ 417 #define IO_ERR_RETRY 60 /* "busied" transaction not retried soon enuf */ 418 #define IO_ERR_ACCESS 61 /* illegal register access */ 419 #define IO_ERR_IMPROP 62 /* "improper" data written */ 420 #define IO_ERR_UNKNOWN 63 421 422 /* io_control (memory) */ 423 #define IO_CTL_MEMINIT 0x0 /* prevent some bus errors during memory init */ 424 #define IO_CTL_MEMOKAY 0x100 /* enable all bus error logging */ 425 426 /* io_spa */ 427 #define SPA_ENABLE 0x20 /* io_spa register enable spa bit */ 428 429 #define EIM_GRPMASK 0x1F /* EIM register group mask */ 430 #define EIEM_MASK(eim) (0x80000000 >> (eim & EIM_GRPMASK)) 431 #define EIEM_BITCNT 32 /* number of bits in EIEM register */ 432 433 #endif /* _MACHINE_IOMOD_H_ */ 434