1 /* $OpenBSD: cpufunc.h,v 1.22 2014/03/29 18:09:29 guenther Exp $ */ 2 /* $NetBSD: cpufunc.h,v 1.8 1994/10/27 04:15:59 cgd Exp $ */ 3 4 /* 5 * Copyright (c) 1993 Charles Hannum. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _MACHINE_CPUFUNC_H_ 35 #define _MACHINE_CPUFUNC_H_ 36 37 #ifdef _KERNEL 38 39 /* 40 * Functions to provide access to i386-specific instructions. 41 */ 42 43 #include <sys/types.h> 44 45 #include <machine/specialreg.h> 46 47 static __inline void invlpg(u_int); 48 static __inline void lidt(void *); 49 static __inline void lldt(u_short); 50 static __inline void ltr(u_short); 51 static __inline void lcr0(u_int); 52 static __inline u_int rcr0(void); 53 static __inline u_int rcr2(void); 54 static __inline void lcr3(u_int); 55 static __inline u_int rcr3(void); 56 static __inline void lcr4(u_int); 57 static __inline u_int rcr4(void); 58 static __inline void tlbflush(void); 59 static __inline void tlbflushg(void); 60 static __inline void disable_intr(void); 61 static __inline void enable_intr(void); 62 static __inline u_int read_eflags(void); 63 static __inline void write_eflags(u_int); 64 static __inline void wbinvd(void); 65 static __inline void clflush(u_int32_t addr); 66 static __inline void mfence(void); 67 static __inline void wrmsr(u_int, u_int64_t); 68 static __inline u_int64_t rdmsr(u_int); 69 static __inline void breakpoint(void); 70 71 static __inline void 72 invlpg(u_int addr) 73 { 74 __asm volatile("invlpg (%0)" : : "r" (addr) : "memory"); 75 } 76 77 static __inline void 78 lidt(void *p) 79 { 80 __asm volatile("lidt (%0)" : : "r" (p) : "memory"); 81 } 82 83 static __inline void 84 lldt(u_short sel) 85 { 86 __asm volatile("lldt %0" : : "r" (sel)); 87 } 88 89 static __inline void 90 ltr(u_short sel) 91 { 92 __asm volatile("ltr %0" : : "r" (sel)); 93 } 94 95 static __inline void 96 lcr0(u_int val) 97 { 98 __asm volatile("movl %0,%%cr0" : : "r" (val)); 99 } 100 101 static __inline u_int 102 rcr0(void) 103 { 104 u_int val; 105 __asm volatile("movl %%cr0,%0" : "=r" (val)); 106 return val; 107 } 108 109 static __inline u_int 110 rcr2(void) 111 { 112 u_int val; 113 __asm volatile("movl %%cr2,%0" : "=r" (val)); 114 return val; 115 } 116 117 static __inline void 118 lcr3(u_int val) 119 { 120 __asm volatile("movl %0,%%cr3" : : "r" (val)); 121 } 122 123 static __inline u_int 124 rcr3(void) 125 { 126 u_int val; 127 __asm volatile("movl %%cr3,%0" : "=r" (val)); 128 return val; 129 } 130 131 static __inline void 132 lcr4(u_int val) 133 { 134 __asm volatile("movl %0,%%cr4" : : "r" (val)); 135 } 136 137 static __inline u_int 138 rcr4(void) 139 { 140 u_int val; 141 __asm volatile("movl %%cr4,%0" : "=r" (val)); 142 return val; 143 } 144 145 static __inline void 146 tlbflush(void) 147 { 148 u_int val; 149 __asm volatile("movl %%cr3,%0" : "=r" (val)); 150 __asm volatile("movl %0,%%cr3" : : "r" (val)); 151 } 152 153 static __inline void 154 tlbflushg(void) 155 { 156 /* 157 * Big hammer: flush all TLB entries, including ones from PTE's 158 * with the G bit set. This should only be necessary if TLB 159 * shootdown falls far behind. 160 * 161 * Intel Architecture Software Developer's Manual, Volume 3, 162 * System Programming, section 9.10, "Invalidating the 163 * Translation Lookaside Buffers (TLBS)": 164 * "The following operations invalidate all TLB entries, irrespective 165 * of the setting of the G flag: 166 * ... 167 * "(P6 family processors only): Writing to control register CR4 to 168 * modify the PSE, PGE, or PAE flag." 169 * 170 * (the alternatives not quoted above are not an option here.) 171 * 172 * If PGE is not in use, we reload CR3 for the benefit of 173 * pre-P6-family processors. 174 */ 175 176 if (cpu_feature & CPUID_PGE) { 177 u_int cr4 = rcr4(); 178 lcr4(cr4 & ~CR4_PGE); 179 lcr4(cr4); 180 } else 181 tlbflush(); 182 } 183 184 #ifdef notyet 185 void setidt(int idx, /*XXX*/caddr_t func, int typ, int dpl); 186 #endif 187 188 189 /* XXXX ought to be in psl.h with spl() functions */ 190 191 static __inline void 192 disable_intr(void) 193 { 194 __asm volatile("cli"); 195 } 196 197 static __inline void 198 enable_intr(void) 199 { 200 __asm volatile("sti"); 201 } 202 203 static __inline u_int 204 read_eflags(void) 205 { 206 u_int ef; 207 208 __asm volatile("pushfl; popl %0" : "=r" (ef)); 209 return (ef); 210 } 211 212 static __inline void 213 write_eflags(u_int ef) 214 { 215 __asm volatile("pushl %0; popfl" : : "r" (ef)); 216 } 217 218 static __inline void 219 wbinvd(void) 220 { 221 __asm volatile("wbinvd"); 222 } 223 224 static __inline void 225 clflush(u_int32_t addr) 226 { 227 __asm volatile("clflush %0" : "+m" (*(volatile char *)addr)); 228 } 229 230 static __inline void 231 mfence(void) 232 { 233 __asm volatile("mfence" : : : "memory"); 234 } 235 236 static __inline void 237 wrmsr(u_int msr, u_int64_t newval) 238 { 239 __asm volatile("wrmsr" : : "A" (newval), "c" (msr)); 240 } 241 242 static __inline u_int64_t 243 rdmsr(u_int msr) 244 { 245 u_int64_t rv; 246 247 __asm volatile("rdmsr" : "=A" (rv) : "c" (msr)); 248 return (rv); 249 } 250 251 static __inline void 252 monitor(const volatile void *addr, u_long extensions, u_int hints) 253 { 254 __asm volatile("monitor" 255 : : "a" (addr), "c" (extensions), "d" (hints)); 256 } 257 258 static __inline void 259 mwait(u_long extensions, u_int hints) 260 { 261 __asm volatile("mwait" : : "a" (hints), "c" (extensions)); 262 } 263 264 /* 265 * Some of the undocumented AMD64 MSRs need a 'passcode' to access. 266 * 267 * See LinuxBIOSv2: src/cpu/amd/model_fxx/model_fxx_init.c 268 */ 269 270 #define OPTERON_MSR_PASSCODE 0x9c5a203a 271 272 static __inline u_int64_t 273 rdmsr_locked(u_int msr, u_int code) 274 { 275 uint64_t rv; 276 __asm volatile("rdmsr" 277 : "=A" (rv) 278 : "c" (msr), "D" (code)); 279 return (rv); 280 } 281 282 static __inline void 283 wrmsr_locked(u_int msr, u_int code, u_int64_t newval) 284 { 285 __asm volatile("wrmsr" 286 : 287 : "A" (newval), "c" (msr), "D" (code)); 288 } 289 290 /* Break into DDB/KGDB. */ 291 static __inline void 292 breakpoint(void) 293 { 294 __asm volatile("int $3"); 295 } 296 297 #define read_psl() read_eflags() 298 #define write_psl(x) write_eflags(x) 299 300 void amd64_errata(struct cpu_info *); 301 302 #endif /* _KERNEL */ 303 #endif /* !_MACHINE_CPUFUNC_H_ */ 304