1 /* $OpenBSD: intr.h,v 1.42 2011/03/23 16:54:35 pirofti Exp $ */ 2 /* $NetBSD: intr.h,v 1.5 1996/05/13 06:11:28 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _MACHINE_INTR_H_ 34 #define _MACHINE_INTR_H_ 35 36 #include <machine/intrdefs.h> 37 38 #ifndef _LOCORE 39 #include <sys/mutex.h> 40 #include <machine/cpu.h> 41 42 extern volatile u_int32_t lapic_tpr; /* Current interrupt priority level. */ 43 44 extern int imask[]; /* Bitmasks telling what interrupts are blocked. */ 45 extern int iunmask[]; /* Bitmasks telling what interrupts are accepted. */ 46 47 #define IMASK(level) imask[IPL(level)] 48 #define IUNMASK(level) iunmask[IPL(level)] 49 50 extern void Xspllower(void); 51 52 extern int splraise(int); 53 extern int spllower(int); 54 extern void splx(int); 55 extern void softintr(int); 56 57 /* 58 * compiler barrier: prevent reordering of instructions. 59 * XXX something similar will move to <sys/cdefs.h> 60 * or thereabouts. 61 * This prevents the compiler from reordering code around 62 * this "instruction", acting as a sequence point for code generation. 63 */ 64 65 #define __splbarrier() __asm __volatile("":::"memory") 66 67 /* SPL asserts */ 68 #ifdef DIAGNOSTIC 69 /* 70 * Although this function is implemented in MI code, it must be in this MD 71 * header because we don't want this header to include MI includes. 72 */ 73 void splassert_fail(int, int, const char *); 74 extern int splassert_ctl; 75 void splassert_check(int, const char *); 76 #define splassert(__wantipl) do { \ 77 if (splassert_ctl > 0) { \ 78 splassert_check(__wantipl, __func__); \ 79 } \ 80 } while (0) 81 #define splsoftassert(wantipl) splassert(wantipl) 82 #else 83 #define splassert(wantipl) do { /* nada */ } while (0) 84 #define splsoftassert(wantipl) do { /* nada */ } while (0) 85 #endif 86 87 /* 88 * Define the splraise and splx code in macros, so that the code can be 89 * reused in a profiling build in a way that does not cause recursion. 90 */ 91 #define _SPLRAISE(ocpl, ncpl) \ 92 ocpl = lapic_tpr; \ 93 if (ncpl > ocpl) \ 94 lapic_tpr = ncpl 95 96 97 #define _SPLX(ncpl) \ 98 lapic_tpr = ncpl; \ 99 if (curcpu()->ci_ipending & IUNMASK(ncpl)) \ 100 Xspllower() 101 102 /* 103 * Hardware interrupt masks 104 */ 105 #define splbio() splraise(IPL_BIO) 106 #define splnet() splraise(IPL_NET) 107 #define spltty() splraise(IPL_TTY) 108 #define splaudio() splraise(IPL_AUDIO) 109 #define splclock() splraise(IPL_CLOCK) 110 #define splstatclock() splhigh() 111 #define splipi() splraise(IPL_IPI) 112 113 /* 114 * Software interrupt masks 115 */ 116 #define splsoftclock() splraise(IPL_SOFTCLOCK) 117 #define splsoftnet() splraise(IPL_SOFTNET) 118 #define splsofttty() splraise(IPL_SOFTTTY) 119 120 /* 121 * Miscellaneous 122 */ 123 #define splvm() splraise(IPL_VM) 124 #define splhigh() splraise(IPL_HIGH) 125 #define splsched() splraise(IPL_SCHED) 126 #define spllock() splhigh() 127 #define spl0() spllower(IPL_NONE) 128 129 #include <machine/pic.h> 130 131 struct cpu_info; 132 133 #ifdef MULTIPROCESSOR 134 int i386_send_ipi(struct cpu_info *, int); 135 int i386_fast_ipi(struct cpu_info *, int); 136 void i386_broadcast_ipi(int); 137 void i386_ipi_handler(void); 138 void i386_intlock(int); 139 void i386_intunlock(int); 140 void i386_softintlock(void); 141 void i386_softintunlock(void); 142 void i386_setperf_ipi(struct cpu_info *); 143 144 extern void (*ipifunc[I386_NIPI])(struct cpu_info *); 145 #endif 146 147 #endif /* !_LOCORE */ 148 149 /* 150 * Generic software interrupt support. 151 */ 152 153 #define I386_SOFTINTR_SOFTCLOCK 0 154 #define I386_SOFTINTR_SOFTNET 1 155 #define I386_SOFTINTR_SOFTTTY 2 156 #define I386_NSOFTINTR 3 157 158 #ifndef _LOCORE 159 #include <sys/queue.h> 160 161 struct i386_soft_intrhand { 162 TAILQ_ENTRY(i386_soft_intrhand) 163 sih_q; 164 struct i386_soft_intr *sih_intrhead; 165 void (*sih_fn)(void *); 166 void *sih_arg; 167 int sih_pending; 168 }; 169 170 struct i386_soft_intr { 171 TAILQ_HEAD(, i386_soft_intrhand) 172 softintr_q; 173 int softintr_ssir; 174 struct mutex softintr_lock; 175 }; 176 177 void *softintr_establish(int, void (*)(void *), void *); 178 void softintr_disestablish(void *); 179 void softintr_init(void); 180 void softintr_dispatch(int); 181 182 #define softintr_schedule(arg) \ 183 do { \ 184 struct i386_soft_intrhand *__sih = (arg); \ 185 struct i386_soft_intr *__si = __sih->sih_intrhead; \ 186 \ 187 mtx_enter(&__si->softintr_lock); \ 188 if (__sih->sih_pending == 0) { \ 189 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 190 __sih->sih_pending = 1; \ 191 softintr(__si->softintr_ssir); \ 192 } \ 193 mtx_leave(&__si->softintr_lock); \ 194 } while (/*CONSTCOND*/ 0) 195 #endif /* _LOCORE */ 196 197 #endif /* !_MACHINE_INTR_H_ */ 198