1 /* $OpenBSD: smbiosvar.h,v 1.8 2010/08/02 16:57:53 marco Exp $ */ 2 /* 3 * Copyright (c) 2006 Gordon Willem Klok <gklok@cogeco.ca> 4 * Copyright (c) 2005 Jordan Hargrave 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 #ifndef _I386_SMBIOSVAR_ 29 #define _I386_SMBIOSVAR_ 30 31 #define SMBIOS_START 0xf0000 32 #define SMBIOS_END 0xfffff 33 34 #define SMBIOS_UUID_NPRESENT 0x1 35 #define SMBIOS_UUID_NSET 0x2 36 37 /* 38 * Section 3.5 of "UUIDs and GUIDs" found at 39 * http://www.opengroup.org/dce/info/draft-leach-uuids-guids-01.txt 40 * specifies the string repersentation of a UUID. 41 */ 42 #define SMBIOS_UUID_REP "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x" 43 #define SMBIOS_UUID_REPLEN 37 /* 16 zero padded values, 4 hyphens, 1 null */ 44 45 struct smbios_entry { 46 u_int8_t mjr; 47 u_int8_t min; 48 u_int8_t *addr; 49 u_int16_t len; 50 u_int16_t count; 51 }; 52 53 struct smbhdr { 54 u_int32_t sig; /* "_SM_" */ 55 u_int8_t checksum; /* Entry point checksum */ 56 u_int8_t len; /* Entry point structure length */ 57 u_int8_t majrev; /* Specification major revision */ 58 u_int8_t minrev; /* Specification minor revision */ 59 u_int16_t mss; /* Maximum Structure Size */ 60 u_int8_t epr; /* Entry Point Revision */ 61 u_int8_t fa[5]; /* value determined by EPR */ 62 u_int8_t sasig[5]; /* Secondary Anchor "_DMI_" */ 63 u_int8_t sachecksum; /* Secondary Checksum */ 64 u_int16_t size; /* Length of structure table in bytes */ 65 u_int32_t addr; /* Structure table address */ 66 u_int16_t count; /* Number of SMBIOS structures */ 67 u_int8_t rev; /* BCD revision */ 68 } __packed; 69 70 struct smbtblhdr { 71 u_int8_t type; 72 u_int8_t size; 73 u_int16_t handle; 74 } __packed; 75 76 struct smbtable { 77 struct smbtblhdr *hdr; 78 void *tblhdr; 79 u_int32_t cookie; 80 }; 81 82 #define SMBIOS_TYPE_BIOS 0 83 #define SMBIOS_TYPE_SYSTEM 1 84 #define SMBIOS_TYPE_BASEBOARD 2 85 #define SMBIOS_TYPE_ENCLOSURE 3 86 #define SMBIOS_TYPE_PROCESSOR 4 87 #define SMBIOS_TYPE_MEMCTRL 5 88 #define SMBIOS_TYPE_MEMMOD 6 89 #define SMBIOS_TYPE_CACHE 7 90 #define SMBIOS_TYPE_PORT 8 91 #define SMBIOS_TYPE_SLOTS 9 92 #define SMBIOS_TYPE_OBD 10 93 #define SMBIOS_TYPE_OEM 11 94 #define SMBIOS_TYPE_SYSCONFOPT 12 95 #define SMBIOS_TYPE_BIOSLANG 13 96 #define SMBIOS_TYPE_GROUPASSOC 14 97 #define SMBIOS_TYPE_SYSEVENTLOG 15 98 #define SMBIOS_TYPE_PHYMEM 16 99 #define SMBIOS_TYPE_MEMDEV 17 100 #define SMBIOS_TYPE_ECCINFO32 18 101 #define SMBIOS_TYPE_MEMMAPARRAYADDR 19 102 #define SMBIOS_TYPE_MEMMAPDEVADDR 20 103 #define SMBIOS_TYPE_INBUILTPOINT 21 104 #define SMBIOS_TYPE_PORTBATT 22 105 #define SMBIOS_TYPE_SYSRESET 23 106 #define SMBIOS_TYPE_HWSECUIRTY 24 107 #define SMBIOS_TYPE_PWRCTRL 25 108 #define SMBIOS_TYPE_VOLTPROBE 26 109 #define SMBIOS_TYPE_COOLING 27 110 #define SMBIOS_TYPE_TEMPPROBE 28 111 #define SMBIOS_TYPE_CURRENTPROBE 29 112 #define SMBIOS_TYPE_OOB_REMOTEACCESS 30 113 #define SMBIOS_TYPE_BIS 31 114 #define SMBIOS_TYPE_SBI 32 115 #define SMBIOS_TYPE_ECCINFO64 33 116 #define SMBIOS_TYPE_MGMTDEV 34 117 #define SMBIOS_TYPE_MGTDEVCOMP 35 118 #define SMBIOS_TYPE_MGTDEVTHRESH 36 119 #define SMBIOS_TYPE_MEMCHANNEL 37 120 #define SMBIOS_TYPE_IPMIDEV 38 121 #define SMBIOS_TYPE_SPS 39 122 #define SMBIOS_TYPE_INACTIVE 126 123 #define SMBIOS_TYPE_EOT 127 124 125 /* 126 * SMBIOS Structure Type 0 "BIOS Information" 127 * DMTF Specification DSP0134 Section: 3.3.1 p.g. 34 128 */ 129 struct smbios_struct_bios { 130 u_int8_t vendor; /* string */ 131 u_int8_t version; /* string */ 132 u_int16_t startaddr; 133 u_int8_t release; /* string */ 134 u_int8_t romsize; 135 u_int64_t characteristics; 136 u_int32_t charext; 137 u_int8_t major_rel; 138 u_int8_t minor_rel; 139 u_int8_t ecf_mjr_rel; /* embedded controler firmware */ 140 u_int8_t ecf_min_rel; /* embedded controler firmware */ 141 } __packed; 142 143 /* 144 * SMBIOS Structure Type 1 "System Information" 145 * DMTF Specification DSP0134 Section 3.3.2 p.g. 35 146 */ 147 148 struct smbios_sys { 149 /* SMBIOS spec 2.0+ */ 150 u_int8_t vendor; /* string */ 151 u_int8_t product; /* string */ 152 u_int8_t version; /* string */ 153 u_int8_t serial; /* string */ 154 /* SMBIOS spec 2.1+ */ 155 u_int8_t uuid[16]; 156 u_int8_t wakeup; 157 /* SMBIOS spec 2.4+ */ 158 u_int8_t sku; /* string */ 159 u_int8_t family; /* string */ 160 } __packed; 161 162 /* 163 * SMBIOS Structure Type 2 "Base Board (Module) Information" 164 * DMTF Specification DSP0134 Section 3.3.3 p.g. 37 165 */ 166 struct smbios_board { 167 u_int8_t vendor; /* string */ 168 u_int8_t product; /* string */ 169 u_int8_t version; /* string */ 170 u_int8_t serial; /* string */ 171 u_int8_t asset; /* stirng */ 172 u_int8_t feature; /* feature flags */ 173 u_int8_t location; /* location in chassis */ 174 u_int16_t handle; /* chassis handle */ 175 u_int8_t type; /* board type */ 176 u_int8_t noc; /* number of contained objects */ 177 } __packed; 178 179 /* 180 * SMBIOS Structure Type 3 "System Wnclosure or Chassis" 181 * DMTF Specification DSP0134 182 */ 183 struct smbios_enclosure { 184 /* SMBIOS spec 2.0+ */ 185 u_int8_t vendor; /* string */ 186 u_int8_t type; 187 u_int8_t version; /* string */ 188 u_int8_t serial; /* string */ 189 u_int8_t asset_tag; /* string */ 190 /* SMBIOS spec 2.1+ */ 191 u_int8_t boot_state; 192 u_int8_t psu_state; 193 u_int8_t thermal_state; 194 u_int8_t security_status; 195 /* SMBIOS spec 2.3+ */ 196 u_int16_t oem_defined; 197 u_int8_t height; 198 u_int8_t no_power_cords; 199 u_int8_t no_contained_element; 200 u_int8_t reclen_contained_element; 201 u_int8_t contained_elements; 202 /* SMBIOS spec 2.7+ */ 203 u_int8_t sku; /* string */ 204 } __packed; 205 206 /* 207 * SMBIOS Structure Type 4 "processor Information" 208 * DMTF Specification DSP0134 v2.5 Section 3.3.5 p.g. 24 209 */ 210 struct smbios_cpu { 211 u_int8_t cpu_socket_designation; /* string */ 212 u_int8_t cpu_type; 213 u_int8_t cpu_family; 214 u_int8_t cpu_mfg; /* string */ 215 u_int32_t cpu_id_eax; 216 u_int32_t cpu_id_edx; 217 u_int8_t cpu_version; /* string */ 218 u_int8_t cpu_voltage; 219 u_int16_t cpu_clock; 220 u_int16_t cpu_max_speed; 221 u_int16_t cpu_current_speed; 222 u_int8_t cpu_status; 223 #define SMBIOS_CPUST_POPULATED (1<<6) 224 #define SMBIOS_CPUST_STATUSMASK (0x07) 225 u_int8_t cpu_upgrade; 226 u_int16_t cpu_l1_handle; 227 u_int16_t cpu_l2_handle; 228 u_int16_t cpu_l3_handle; 229 u_int8_t cpu_serial; /* string */ 230 u_int8_t cpu_asset_tag; /* string */ 231 u_int8_t cpu_part_nr; /* string */ 232 /* following fields were added in smbios 2.5 */ 233 u_int8_t cpu_core_count; 234 u_int8_t cpu_core_enabled; 235 u_int8_t cpu_thread_count; 236 u_int16_t cpu_characteristics; 237 } __packed; 238 239 /* 240 * SMBIOS Structure Type 38 "IPMI Information" 241 * DMTF Specification DSP0134 Section 3.3.39 p.g. 91 242 */ 243 struct smbios_ipmi { 244 u_int8_t smipmi_if_type; /* IPMI Interface Type */ 245 u_int8_t smipmi_if_rev; /* BCD IPMI Revision */ 246 u_int8_t smipmi_i2c_address; /* I2C address of BMC */ 247 u_int8_t smipmi_nvram_address; /* I2C address of NVRAM 248 * storage */ 249 u_int64_t smipmi_base_address; /* Base address of BMC (BAR 250 * format */ 251 u_int8_t smipmi_base_flags; /* Flags field: 252 * bit 7:6 : register spacing 253 * 00 = byte 254 * 01 = dword 255 * 02 = word 256 * bit 4 : Lower bit BAR 257 * bit 3 : IRQ valid 258 * bit 2 : N/A 259 * bit 1 : Interrupt polarity 260 * bit 0 : Interrupt trigger */ 261 u_int8_t smipmi_irq; /* IRQ if applicable */ 262 } __packed; 263 264 int smbios_find_table(u_int8_t, struct smbtable *); 265 char *smbios_get_string(struct smbtable *, u_int8_t, char *, size_t); 266 267 #endif 268