1 /* $OpenBSD: specialreg.h,v 1.75 2019/12/20 07:55:30 jsg Exp $ */ 2 /* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */ 3 4 /*- 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 33 */ 34 35 /* 36 * Bits in 386 special registers: 37 */ 38 #define CR0_PE 0x00000001 /* Protected mode Enable */ 39 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 40 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 41 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 42 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 43 #define CR0_PG 0x80000000 /* PaGing enable */ 44 45 /* 46 * Bits in 486 special registers: 47 */ 48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 50 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 51 #define CR0_NW 0x20000000 /* Not Write-through */ 52 #define CR0_CD 0x40000000 /* Cache Disable */ 53 54 /* 55 * Cyrix 486 DLC special registers, accessable as IO ports. 56 */ 57 #define CCR0 0xc0 /* configuration control register 0 */ 58 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 59 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 60 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 61 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 62 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 63 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 64 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 65 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 66 67 #define CCR1 0xc1 /* configuration control register 1 */ 68 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 69 /* the remaining 7 bits of this register are reserved */ 70 71 /* 72 * bits in CR3 73 */ 74 #define CR3_PWT (1ULL << 3) 75 #define CR3_PCD (1ULL << 4) 76 77 /* 78 * bits in the pentiums %cr4 register: 79 */ 80 81 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 82 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 83 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */ 84 #define CR4_DE 0x00000008 /* debugging extension */ 85 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 86 #define CR4_PAE 0x00000020 /* physical address extension enable */ 87 #define CR4_MCE 0x00000040 /* machine check enable */ 88 #define CR4_PGE 0x00000080 /* page global enable */ 89 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 90 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 91 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 92 #define CR4_UMIP 0x00000800 /* user mode instruction prevention */ 93 #define CR4_VMXE 0x00002000 /* enable virtual machine operation */ 94 #define CR4_SMXE 0x00004000 /* enable safe mode operation */ 95 #define CR4_FSGSBASE 0x00010000 /* enable {RD,WR}{FS,GS}BASE ops */ 96 #define CR4_PCIDE 0x00020000 /* enable process-context IDs */ 97 #define CR4_OSXSAVE 0x00040000 /* enable XSAVE and extended states */ 98 #define CR4_SMEP 0x00100000 /* supervisor mode exec protection */ 99 #define CR4_SMAP 0x00200000 /* supervisor mode access prevention */ 100 #define CR4_PKE 0x00400000 /* protection key enable */ 101 102 /* 103 * CPUID "features" bits (CPUID function 0x1): 104 * EDX bits, then ECX bits 105 */ 106 107 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 108 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 109 #define CPUID_DE 0x00000004 /* has debugging extension */ 110 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 111 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 112 #define CPUID_MSR 0x00000020 /* has model specific registers */ 113 #define CPUID_PAE 0x00000040 /* has phys address extension */ 114 #define CPUID_MCE 0x00000080 /* has machine check exception */ 115 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 116 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 117 #define CPUID_SYS1 0x00000400 /* has SYSCALL/SYSRET inst. (Cyrix) */ 118 #define CPUID_SEP 0x00000800 /* has SYSCALL/SYSRET inst. (AMD/Intel) */ 119 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 120 #define CPUID_PGE 0x00002000 /* has page global extension */ 121 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 122 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 123 #define CPUID_PAT 0x00010000 /* has page attribute table */ 124 #define CPUID_PSE36 0x00020000 /* has 36bit page size extension */ 125 #define CPUID_PSN 0x00040000 /* has processor serial number */ 126 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ 127 #define CPUID_B20 0x00100000 /* reserved */ 128 #define CPUID_DS 0x00200000 /* Debug Store */ 129 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 130 #define CPUID_MMX 0x00800000 /* has MMX instructions */ 131 #define CPUID_FXSR 0x01000000 /* has FXRSTOR instruction */ 132 #define CPUID_SSE 0x02000000 /* has streaming SIMD extensions */ 133 #define CPUID_SSE2 0x04000000 /* has streaming SIMD extensions #2 */ 134 #define CPUID_SS 0x08000000 /* self-snoop */ 135 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 136 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 137 #define CPUID_B30 0x40000000 /* reserved */ 138 #define CPUID_PBE 0x80000000 /* Pending Break Enabled restarts clock */ 139 140 #define CPUIDECX_SSE3 0x00000001 /* streaming SIMD extensions #3 */ 141 #define CPUIDECX_PCLMUL 0x00000002 /* Carryless Multiplication */ 142 #define CPUIDECX_DTES64 0x00000004 /* 64bit debug store */ 143 #define CPUIDECX_MWAIT 0x00000008 /* Monitor/Mwait */ 144 #define CPUIDECX_DSCPL 0x00000010 /* CPL Qualified Debug Store */ 145 #define CPUIDECX_VMX 0x00000020 /* Virtual Machine Extensions */ 146 #define CPUIDECX_SMX 0x00000040 /* Safer Mode Extensions */ 147 #define CPUIDECX_EST 0x00000080 /* enhanced SpeedStep */ 148 #define CPUIDECX_TM2 0x00000100 /* thermal monitor 2 */ 149 #define CPUIDECX_SSSE3 0x00000200 /* Supplemental Streaming SIMD Ext. 3 */ 150 #define CPUIDECX_CNXTID 0x00000400 /* Context ID */ 151 #define CPUIDECX_SDBG 0x00000800 /* Silicon debug capability */ 152 #define CPUIDECX_FMA3 0x00001000 /* Fused Multiply Add */ 153 #define CPUIDECX_CX16 0x00002000 /* has CMPXCHG16B instruction */ 154 #define CPUIDECX_XTPR 0x00004000 /* xTPR Update Control */ 155 #define CPUIDECX_PDCM 0x00008000 /* Perfmon and Debug Capability */ 156 #define CPUIDECX_PCID 0x00020000 /* Process-context ID Capability */ 157 #define CPUIDECX_DCA 0x00040000 /* Direct Cache Access */ 158 #define CPUIDECX_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 159 #define CPUIDECX_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 160 #define CPUIDECX_X2APIC 0x00200000 /* Extended xAPIC Support */ 161 #define CPUIDECX_MOVBE 0x00400000 /* MOVBE Instruction */ 162 #define CPUIDECX_POPCNT 0x00800000 /* POPCNT Instruction */ 163 #define CPUIDECX_DEADLINE 0x01000000 /* APIC one-shot via deadline */ 164 #define CPUIDECX_AES 0x02000000 /* AES Instruction */ 165 #define CPUIDECX_XSAVE 0x04000000 /* XSAVE/XSTOR States */ 166 #define CPUIDECX_OSXSAVE 0x08000000 /* OSXSAVE */ 167 #define CPUIDECX_AVX 0x10000000 /* Advanced Vector Extensions */ 168 #define CPUIDECX_F16C 0x20000000 /* 16bit fp conversion */ 169 #define CPUIDECX_RDRAND 0x40000000 /* RDRAND instruction */ 170 #define CPUIDECX_HV 0x80000000 /* Running on hypervisor */ 171 172 /* 173 * "Structured Extended Feature Flags Parameters" (CPUID function 0x7, leaf 0) 174 * EBX bits 175 */ 176 #define SEFF0EBX_FSGSBASE 0x00000001 /* {RD,WR}[FG]SBASE instructions */ 177 #define SEFF0EBX_TSC_ADJUST 0x00000002 /* Has IA32_TSC_ADJUST MSR */ 178 #define SEFF0EBX_SGX 0x00000004 /* Software Guard Extensions */ 179 #define SEFF0EBX_BMI1 0x00000008 /* advanced bit manipulation */ 180 #define SEFF0EBX_HLE 0x00000010 /* Hardware Lock Elision */ 181 #define SEFF0EBX_AVX2 0x00000020 /* Advanced Vector Extensions 2 */ 182 #define SEFF0EBX_SMEP 0x00000080 /* Supervisor mode exec protection */ 183 #define SEFF0EBX_BMI2 0x00000100 /* advanced bit manipulation */ 184 #define SEFF0EBX_ERMS 0x00000200 /* Enhanced REP MOVSB/STOSB */ 185 #define SEFF0EBX_INVPCID 0x00000400 /* INVPCID instruction */ 186 #define SEFF0EBX_RTM 0x00000800 /* Restricted Transactional Memory */ 187 #define SEFF0EBX_PQM 0x00001000 /* Quality of Service Monitoring */ 188 #define SEFF0EBX_MPX 0x00004000 /* Memory Protection Extensions */ 189 #define SEFF0EBX_AVX512F 0x00010000 /* AVX-512 foundation inst */ 190 #define SEFF0EBX_AVX512DQ 0x00020000 /* AVX-512 double/quadword */ 191 #define SEFF0EBX_RDSEED 0x00040000 /* RDSEED instruction */ 192 #define SEFF0EBX_ADX 0x00080000 /* ADCX/ADOX instructions */ 193 #define SEFF0EBX_SMAP 0x00100000 /* Supervisor mode access prevent */ 194 #define SEFF0EBX_AVX512IFMA 0x00200000 /* AVX-512 integer mult-add */ 195 #define SEFF0EBX_PCOMMIT 0x00400000 /* Persistent commit inst */ 196 #define SEFF0EBX_CLFLUSHOPT 0x00800000 /* cache line flush */ 197 #define SEFF0EBX_CLWB 0x01000000 /* cache line write back */ 198 #define SEFF0EBX_PT 0x02000000 /* Processor Trace */ 199 #define SEFF0EBX_AVX512PF 0x04000000 /* AVX-512 prefetch */ 200 #define SEFF0EBX_AVX512ER 0x08000000 /* AVX-512 exp/reciprocal */ 201 #define SEFF0EBX_AVX512CD 0x10000000 /* AVX-512 conflict detection */ 202 #define SEFF0EBX_SHA 0x20000000 /* SHA Extensions */ 203 #define SEFF0EBX_AVX512BW 0x40000000 /* AVX-512 byte/word inst */ 204 #define SEFF0EBX_AVX512VL 0x80000000 /* AVX-512 vector len inst */ 205 /* SEFF ECX bits */ 206 #define SEFF0ECX_PREFETCHWT1 0x00000001 /* PREFETCHWT1 instruction */ 207 #define SEFF0ECX_AVX512VBMI 0x00000002 /* AVX-512 vector bit inst */ 208 #define SEFF0ECX_UMIP 0x00000004 /* UMIP support */ 209 #define SEFF0ECX_PKU 0x00000008 /* Page prot keys for user mode */ 210 /* SEFF EDX bits */ 211 #define SEFF0EDX_AVX512_4FNNIW 0x00000004 /* AVX-512 neural network insns */ 212 #define SEFF0EDX_AVX512_4FMAPS 0x00000008 /* AVX-512 mult accum single prec */ 213 #define SEFF0EDX_IBRS 0x04000000 /* IBRS / IBPB Speculation Control */ 214 #define SEFF0EDX_STIBP 0x08000000 /* STIBP Speculation Control */ 215 #define SEFF0EDX_L1DF 0x10000000 /* L1D_FLUSH */ 216 #define SEFF0EDX_ARCH_CAP 0x20000000 /* Has IA32_ARCH_CAPABILITIES MSR */ 217 #define SEFF0EDX_SSBD 0x80000000 /* Spec Store Bypass Disable */ 218 219 /* 220 * Thermal and Power Management (CPUID function 0x6) EAX bits 221 */ 222 #define TPM_SENSOR 0x00000001 /* Digital temp sensor */ 223 #define TPM_ARAT 0x00000004 /* APIC Timer Always Running */ 224 225 /* 226 * "Architectural Performance Monitoring" bits (CPUID function 0x0a): 227 * EAX bits 228 */ 229 230 #define CPUIDEAX_VERID 0x000000ff 231 #define CPUIDEAX_NUM_GC(cpuid) (((cpuid) >> 8) & 0x000000ff) 232 #define CPUIDEAX_BIT_GC(cpuid) (((cpuid) >> 16) & 0x000000ff) 233 #define CPUIDEAX_LEN_EBX(cpuid) (((cpuid) >> 24) & 0x000000ff) 234 235 #define CPUIDEBX_EVT_CORE (1 << 0) /* Core cycle */ 236 #define CPUIDEBX_EVT_INST (1 << 1) /* Instruction retired */ 237 #define CPUIDEBX_EVT_REFR (1 << 2) /* Reference cycles */ 238 #define CPUIDEBX_EVT_CACHE_REF (1 << 3) /* Last-level cache ref. */ 239 #define CPUIDEBX_EVT_CACHE_MIS (1 << 4) /* Last-level cache miss. */ 240 #define CPUIDEBX_EVT_BRANCH_INST (1 << 5) /* Branch instruction ret. */ 241 #define CPUIDEBX_EVT_BRANCH_MISP (1 << 6) /* Branch mispredict ret. */ 242 243 #define CPUIDEDX_NUM_FC(cpuid) (((cpuid) >> 0) & 0x0000001f) 244 #define CPUIDEDX_BIT_FC(cpuid) (((cpuid) >> 5) & 0x000000ff) 245 246 /* 247 * CPUID "extended features" bits (CPUID function 0x80000001): 248 * EDX bits, then ECX bits 249 */ 250 251 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 252 #define CPUID_NXE 0x00100000 /* No-Execute Extension */ 253 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 254 #define CPUID_FFXSR 0x02000000 /* fast FP/MMX save/restore */ 255 #define CPUID_PAGE1GB 0x04000000 /* 1-GByte pages */ 256 #define CPUID_RDTSCP 0x08000000 /* RDTSCP / IA32_TSC_AUX available */ 257 #define CPUID_LONG 0x20000000 /* long mode */ 258 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 259 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 260 261 #define CPUIDECX_LAHF 0x00000001 /* LAHF and SAHF instructions */ 262 #define CPUIDECX_CMPLEG 0x00000002 /* Core MP legacy mode */ 263 #define CPUIDECX_SVM 0x00000004 /* Secure Virtual Machine */ 264 #define CPUIDECX_EAPICSP 0x00000008 /* Extended APIC space */ 265 #define CPUIDECX_AMCR8 0x00000010 /* LOCK MOV CR0 means MOV CR8 */ 266 #define CPUIDECX_ABM 0x00000020 /* LZCNT instruction */ 267 #define CPUIDECX_SSE4A 0x00000040 /* SSE4-A instruction set */ 268 #define CPUIDECX_MASSE 0x00000080 /* Misaligned SSE mode */ 269 #define CPUIDECX_3DNOWP 0x00000100 /* 3DNowPrefetch */ 270 #define CPUIDECX_OSVW 0x00000200 /* OS visible workaround */ 271 #define CPUIDECX_IBS 0x00000400 /* Instruction based sampling */ 272 #define CPUIDECX_XOP 0x00000800 /* Extended operating support */ 273 #define CPUIDECX_SKINIT 0x00001000 /* SKINIT and STGI are supported */ 274 #define CPUIDECX_WDT 0x00002000 /* Watchdog timer */ 275 /* Reserved 0x00004000 */ 276 #define CPUIDECX_LWP 0x00008000 /* Lightweight profiling support */ 277 #define CPUIDECX_FMA4 0x00010000 /* 4-operand FMA instructions */ 278 #define CPUIDECX_TCE 0x00020000 /* Translation Cache Extension */ 279 /* Reserved 0x00040000 */ 280 #define CPUIDECX_NODEID 0x00080000 /* Support for MSRC001C */ 281 /* Reserved 0x00100000 */ 282 #define CPUIDECX_TBM 0x00200000 /* Trailing bit manipulation instruction */ 283 #define CPUIDECX_TOPEXT 0x00400000 /* Topology extensions support */ 284 #define CPUIDECX_CPCTR 0x00800000 /* core performance counter ext */ 285 #define CPUIDECX_DBKP 0x04000000 /* DataBreakpointExtension */ 286 #define CPUIDECX_PERFTSC 0x08000000 /* performance time-stamp counter */ 287 #define CPUIDECX_PCTRL3 0x10000000 /* L3 performance counter ext */ 288 #define CPUIDECX_MWAITX 0x20000000 /* MWAITX/MONITORX */ 289 290 /* 291 * "Advanced Power Management Information" bits (CPUID function 0x80000007): 292 * EDX bits. 293 */ 294 295 #define CPUIDEDX_ITSC (1 << 8) /* Invariant TSC */ 296 297 /* 298 * AMD CPUID function 0x80000008 EBX bits 299 */ 300 #define CPUIDEBX_IBPB (1ULL << 12) /* Speculation Control IBPB */ 301 #define CPUIDEBX_IBRS (1ULL << 14) /* Speculation Control IBRS */ 302 #define CPUIDEBX_STIBP (1ULL << 15) /* Speculation Control STIBP */ 303 #define CPUIDEBX_IBRS_ALWAYSON (1ULL << 16) /* IBRS always on mode */ 304 #define CPUIDEBX_STIBP_ALWAYSON (1ULL << 17) /* STIBP always on mode */ 305 #define CPUIDEBX_IBRS_PREF (1ULL << 18) /* IBRS preferred */ 306 #define CPUIDEBX_SSBD (1ULL << 24) /* Speculation Control SSBD */ 307 #define CPUIDEBX_VIRT_SSBD (1ULL << 25) /* Virt Spec Control SSBD */ 308 #define CPUIDEBX_SSBD_NOTREQ (1ULL << 26) /* SSBD not required */ 309 310 #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15) 311 #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15) 312 #define CPUID2STEPPING(cpuid) ((cpuid) & 15) 313 314 #define CPUID(code, eax, ebx, ecx, edx) \ 315 __asm volatile("cpuid" \ 316 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 317 : "a" (code)); 318 #define CPUID_LEAF(code, leaf, eax, ebx, ecx, edx) \ 319 __asm volatile("cpuid" \ 320 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 321 : "a" (code), "c" (leaf)); 322 323 324 /* 325 * Model-specific registers for the i386 family 326 */ 327 #define MSR_P5_MC_ADDR 0x000 328 #define MSR_P5_MC_TYPE 0x001 329 #define MSR_TSC 0x010 330 #define P5MSR_CTRSEL 0x011 /* P5 only (trap on P6) */ 331 #define P5MSR_CTR0 0x012 /* P5 only (trap on P6) */ 332 #define P5MSR_CTR1 0x013 /* P5 only (trap on P6) */ 333 #define MSR_PLATFORM_ID 0x017 /* Platform ID for microcode */ 334 #define MSR_APICBASE 0x01b 335 #define APICBASE_BSP 0x100 336 #define APICBASE_ENABLE_X2APIC 0x400 337 #define APICBASE_GLOBAL_ENABLE 0x800 338 #define MSR_EBL_CR_POWERON 0x02a 339 #define MSR_EBC_FREQUENCY_ID 0x02c /* Pentium 4 only */ 340 #define MSR_TEST_CTL 0x033 341 #define MSR_IA32_FEATURE_CONTROL 0x03a 342 #define MSR_SPEC_CTRL 0x048 /* Speculation Control IBRS / STIBP */ 343 #define SPEC_CTRL_IBRS (1ULL << 0) 344 #define SPEC_CTRL_STIBP (1ULL << 1) 345 #define SPEC_CTRL_SSBD (1ULL << 2) 346 #define MSR_PRED_CMD 0x049 /* Speculation Control IBPB */ 347 #define PRED_CMD_IBPB (1ULL << 0) 348 #define MSR_BIOS_UPDT_TRIG 0x079 349 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 350 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 351 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 352 #define MSR_BIOS_SIGN 0x08b 353 #define MSR_PERFCTR0 0x0c1 354 #define MSR_PERFCTR1 0x0c2 355 #define P6MSR_CTR0 0x0c1 356 #define P6MSR_CTR1 0x0c2 357 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 358 #define MSR_MTRRcap 0x0fe 359 #define MTRRcap_FIXED 0x100 /* bit 8 - fixed MTRRs supported */ 360 #define MTRRcap_WC 0x400 /* bit 10 - WC type supported */ 361 #define MTRRcap_SMRR 0x800 /* bit 11 - SMM range reg supported */ 362 #define MSR_ARCH_CAPABILITIES 0x10a 363 #define ARCH_CAPABILITIES_RDCL_NO (1 << 0) /* Meltdown safe */ 364 #define ARCH_CAPABILITIES_IBRS_ALL (1 << 1) /* enhanced IBRS */ 365 #define ARCH_CAPABILITIES_RSBA (1 << 2) /* RSB Alternate */ 366 #define ARCH_CAPABILITIES_SKIP_L1DFL_VMENTRY (1 << 3) 367 #define ARCH_CAPABILITIES_SSB_NO (1 << 4) /* Spec St Byp safe */ 368 #define ARCH_CAPABILITIES_MDS_NO (1 << 5) /* microarch data-sampling */ 369 #define ARCH_CAPABILITIES_IF_PSCHANGE_MC_NO (1 << 6) /* PS MCE safe */ 370 #define ARCH_CAPABILITIES_TSX_CTRL (1 << 7) /* has TSX_CTRL MSR */ 371 #define ARCH_CAPABILITIES_TAA_NO (1 << 8) /* TSX AA safe */ 372 #define MSR_FLUSH_CMD 0x10b 373 #define FLUSH_CMD_L1D_FLUSH (1ULL << 0) 374 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 375 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 376 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 377 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 378 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 379 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 380 #define MSR_TSX_CTRL 0x122 381 #define TSX_CTRL_RTM_DISABLE (1ULL << 0) 382 #define TSX_CTRL_TSX_CPUID_CLEAR (1ULL << 1) 383 #define MSR_SYSENTER_CS 0x174 384 #define MSR_SYSENTER_ESP 0x175 385 #define MSR_SYSENTER_EIP 0x176 386 #define MSR_MCG_CAP 0x179 387 #define MSR_MCG_STATUS 0x17a 388 #define MSR_MCG_CTL 0x17b 389 #define P6MSR_CTRSEL0 0x186 390 #define P6MSR_CTRSEL1 0x187 391 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 392 #define MSR_PERF_CTL 0x199 /* Pentium M */ 393 #define PERF_CTL_TURBO 0x100000000ULL /* bit 32 - turbo mode */ 394 #define MSR_THERM_CONTROL 0x19a 395 #define MSR_THERM_INTERRUPT 0x19b 396 #define MSR_THERM_STATUS 0x19c 397 #define MSR_THERM_STATUS_VALID_BIT 0x80000000 398 #define MSR_THERM_STATUS_TEMP(msr) ((msr >> 16) & 0x7f) 399 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 400 #define MSR_MISC_ENABLE 0x1a0 401 /* 402 * MSR_MISC_ENABLE (0x1a0) 403 * 404 * Enable Fast Strings: enables fast REP MOVS/REP STORS (R/W) 405 * Enable TCC: Enable automatic thermal control circuit (R/W) 406 * Performance monitoring available: 1 if enabled (R/O) 407 * Branch trace storage unavailable: 1 if unsupported (R/O) 408 * Processor event based sampling unavailable: 1 if unsupported (R/O) 409 * Enhanced Intel SpeedStep technology enable: 1 to enable (R/W) 410 * Enable monitor FSM: 1 to enable MONITOR/MWAIT (R/W) 411 * Limit CPUID maxval: 1 to limit CPUID leaf nodes to 0x2 and lower (R/W) 412 * Enable xTPR message disable: 1 to disable xTPR messages 413 * XD bit disable: 1 to disable NX capability (bit 34, or bit 2 of %edx/%rdx) 414 */ 415 #define MISC_ENABLE_FAST_STRINGS (1 << 0) 416 #define MISC_ENABLE_TCC (1 << 3) 417 #define MISC_ENABLE_PERF_MON_AVAILABLE (1 << 7) 418 #define MISC_ENABLE_BTS_UNAVAILABLE (1 << 11) 419 #define MISC_ENABLE_PEBS_UNAVAILABLE (1 << 12) 420 #define MISC_ENABLE_EIST_ENABLED (1 << 16) 421 #define MISC_ENABLE_ENABLE_MONITOR_FSM (1 << 18) 422 #define MISC_ENABLE_LIMIT_CPUID_MAXVAL (1 << 22) 423 #define MISC_ENABLE_xTPR_MESSAGE_DISABLE (1 << 23) 424 #define MISC_ENABLE_XD_BIT_DISABLE (1 << 2) 425 /* 426 * for Core i Series and newer Xeons, see 427 * http://www.intel.com/content/dam/www/public/us/en/ 428 * documents/white-papers/cpu-monitoring-dts-peci-paper.pdf 429 */ 430 #define MSR_TEMPERATURE_TARGET 0x1a2 /* Core i Series, Newer Xeons */ 431 #define MSR_TEMPERATURE_TARGET_TJMAX(r) (((r) >> 16) & 0xff) 432 /* 433 * not documented anywhere, see intelcore_update_sensor() 434 * only available Core Duo and Core Solo Processors 435 */ 436 #define MSR_TEMPERATURE_TARGET_UNDOCUMENTED 0x0ee 437 #define MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED 0x40000000 438 #define MSR_DEBUGCTLMSR 0x1d9 439 #define MSR_LASTBRANCHFROMIP 0x1db 440 #define MSR_LASTBRANCHTOIP 0x1dc 441 #define MSR_LASTINTFROMIP 0x1dd 442 #define MSR_LASTINTTOIP 0x1de 443 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 444 #define MSR_MTRRvarBase 0x200 445 #define MSR_MTRRfix64K_00000 0x250 446 #define MSR_MTRRfix16K_80000 0x258 447 #define MSR_MTRRfix4K_C0000 0x268 448 #define MSR_CR_PAT 0x277 449 #define MSR_MTRRdefType 0x2ff 450 #define MTRRdefType_FIXED_ENABLE 0x400 /* bit 10 - fixed MTRR enabled */ 451 #define MTRRdefType_ENABLE 0x800 /* bit 11 - MTRRs enabled */ 452 #define MSR_PERF_FIXED_CTR1 0x30a /* CPU_CLK_Unhalted.Core */ 453 #define MSR_PERF_FIXED_CTR2 0x30b /* CPU_CLK.Unhalted.Ref */ 454 #define MSR_PERF_FIXED_CTR_CTRL 0x38d 455 #define MSR_PERF_FIXED_CTR_FC_DIS 0x0 /* disable counter */ 456 #define MSR_PERF_FIXED_CTR_FC_1 0x1 /* count ring 1 */ 457 #define MSR_PERF_FIXED_CTR_FC_123 0x2 /* count rings 1,2,3 */ 458 #define MSR_PERF_FIXED_CTR_FC_ANY 0x3 /* count everything */ 459 #define MSR_PERF_FIXED_CTR_FC_MASK 0x3 460 #define MSR_PERF_FIXED_CTR_FC(_i, _v) ((_v) << (4 * (_i))) 461 #define MSR_PERF_FIXED_CTR_ANYTHR(_i) (0x4 << (4 * (_i))) 462 #define MSR_PERF_FIXED_CTR_INT(_i) (0x8 << (4 * (_i))) 463 #define MSR_PERF_GLOBAL_CTRL 0x38f 464 #define MSR_PERF_GLOBAL_CTR1_EN (1ULL << 33) 465 #define MSR_PERF_GLOBAL_CTR2_EN (1ULL << 34) 466 #define MSR_MC0_CTL 0x400 467 #define MSR_MC0_STATUS 0x401 468 #define MSR_MC0_ADDR 0x402 469 #define MSR_MC0_MISC 0x403 470 #define MSR_MC1_CTL 0x404 471 #define MSR_MC1_STATUS 0x405 472 #define MSR_MC1_ADDR 0x406 473 #define MSR_MC1_MISC 0x407 474 #define MSR_MC2_CTL 0x408 475 #define MSR_MC2_STATUS 0x409 476 #define MSR_MC2_ADDR 0x40a 477 #define MSR_MC2_MISC 0x40b 478 #define MSR_MC4_CTL 0x40c 479 #define MSR_MC4_STATUS 0x40d 480 #define MSR_MC4_ADDR 0x40e 481 #define MSR_MC4_MISC 0x40f 482 #define MSR_MC3_CTL 0x410 483 #define MSR_MC3_STATUS 0x411 484 #define MSR_MC3_ADDR 0x412 485 #define MSR_MC3_MISC 0x413 486 487 /* VIA MSRs */ 488 #define MSR_CENT_TMTEMPERATURE 0x1423 /* Thermal monitor temperature */ 489 #define MSR_C7M_TMTEMPERATURE 0x1169 490 491 /* AMD MSRs */ 492 #define MSR_K6_EPMR 0xc0000086 493 #define MSR_K7_EVNTSEL0 0xc0010000 494 #define MSR_K7_EVNTSEL1 0xc0010001 495 #define MSR_K7_EVNTSEL2 0xc0010002 496 #define MSR_K7_EVNTSEL3 0xc0010003 497 #define MSR_K7_PERFCTR0 0xc0010004 498 #define MSR_K7_PERFCTR1 0xc0010005 499 #define MSR_K7_PERFCTR2 0xc0010006 500 #define MSR_K7_PERFCTR3 0xc0010007 501 502 /* 503 * AMD K8 (Opteron) MSRs. 504 */ 505 #define MSR_PATCH_LEVEL 0x0000008b 506 #define MSR_SYSCFG 0xc0000010 507 508 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 509 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 510 #define EFER_LME 0x00000100 /* Long Mode Active */ 511 #define EFER_LMA 0x00000400 /* Long Mode Enabled */ 512 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 513 #define EFER_SVME 0x00001000 /* SVM Enabled */ 514 515 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 516 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 517 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 518 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 519 520 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 521 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 522 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 523 #define MSR_PATCH_LOADER 0xc0010020 524 #define MSR_INT_PEN_MSG 0xc0010055 /* Interrupt pending message */ 525 526 #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */ 527 #define DE_CFG_721 0x00000001 /* errata 721 */ 528 #define DE_CFG_SERIALIZE_LFENCE (1 << 1) /* Enable serializing lfence */ 529 530 #define IPM_C1E_CMP_HLT 0x10000000 531 #define IPM_SMI_CMP_HLT 0x08000000 532 533 /* 534 * These require a 'passcode' for access. See cpufunc.h. 535 */ 536 #define MSR_HWCR 0xc0010015 537 #define HWCR_FFDIS 0x00000040 538 539 #define MSR_NB_CFG 0xc001001f 540 #define NB_CFG_DISIOREQLOCK 0x0000000000000004ULL 541 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 542 543 #define MSR_LS_CFG 0xc0011020 544 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 545 546 #define MSR_IC_CFG 0xc0011021 547 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 548 549 #define MSR_DC_CFG 0xc0011022 550 #define DC_CFG_DIS_CNV_WC_SSO 0x00000004 551 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 552 553 #define MSR_BU_CFG 0xc0011023 554 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 555 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 556 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 557 558 /* 559 * Constants related to MTRRs 560 */ 561 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 562 #define MTRR_N16K 16 563 #define MTRR_N4K 64 564 565 /* 566 * the following four 3-byte registers control the non-cacheable regions. 567 * These registers must be written as three separate bytes. 568 * 569 * NCRx+0: A31-A24 of starting address 570 * NCRx+1: A23-A16 of starting address 571 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 572 * 573 * The non-cacheable region's starting address must be aligned to the 574 * size indicated by the NCR_SIZE_xx field. 575 */ 576 #define NCR1 0xc4 577 #define NCR2 0xc7 578 #define NCR3 0xca 579 #define NCR4 0xcd 580 581 #define NCR_SIZE_0K 0 582 #define NCR_SIZE_4K 1 583 #define NCR_SIZE_8K 2 584 #define NCR_SIZE_16K 3 585 #define NCR_SIZE_32K 4 586 #define NCR_SIZE_64K 5 587 #define NCR_SIZE_128K 6 588 #define NCR_SIZE_256K 7 589 #define NCR_SIZE_512K 8 590 #define NCR_SIZE_1M 9 591 #define NCR_SIZE_2M 10 592 #define NCR_SIZE_4M 11 593 #define NCR_SIZE_8M 12 594 #define NCR_SIZE_16M 13 595 #define NCR_SIZE_32M 14 596 #define NCR_SIZE_4G 15 597 598 /* 599 * Performance monitor events. 600 * 601 * Note that 586-class and 686-class CPUs have different performance 602 * monitors available, and they are accessed differently: 603 * 604 * 686-class: `rdpmc' instruction 605 * 586-class: `rdmsr' instruction, CESR MSR 606 * 607 * The descriptions of these events are too lenghy to include here. 608 * See Appendix A of "Intel Architecture Software Developer's 609 * Manual, Volume 3: System Programming" for more information. 610 */ 611 612 /* 613 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 614 * is CTR1. 615 */ 616 617 #define PMC5_CESR_EVENT 0x003f 618 #define PMC5_CESR_OS 0x0040 619 #define PMC5_CESR_USR 0x0080 620 #define PMC5_CESR_E 0x0100 621 #define PMC5_CESR_P 0x0200 622 623 /* 624 * 686-class Event Selector MSR format. 625 */ 626 627 #define PMC6_EVTSEL_EVENT 0x000000ff 628 #define PMC6_EVTSEL_UNIT 0x0000ff00 629 #define PMC6_EVTSEL_UNIT_SHIFT 8 630 #define PMC6_EVTSEL_USR (1 << 16) 631 #define PMC6_EVTSEL_OS (1 << 17) 632 #define PMC6_EVTSEL_E (1 << 18) 633 #define PMC6_EVTSEL_PC (1 << 19) 634 #define PMC6_EVTSEL_INT (1 << 20) 635 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 636 #define PMC6_EVTSEL_INV (1 << 23) 637 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 638 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 639 640 /* Data Cache Unit */ 641 #define PMC6_DATA_MEM_REFS 0x43 642 #define PMC6_DCU_LINES_IN 0x45 643 #define PMC6_DCU_M_LINES_IN 0x46 644 #define PMC6_DCU_M_LINES_OUT 0x47 645 #define PMC6_DCU_MISS_OUTSTANDING 0x48 646 647 /* Instruction Fetch Unit */ 648 #define PMC6_IFU_IFETCH 0x80 649 #define PMC6_IFU_IFETCH_MISS 0x81 650 #define PMC6_ITLB_MISS 0x85 651 #define PMC6_IFU_MEM_STALL 0x86 652 #define PMC6_ILD_STALL 0x87 653 654 /* L2 Cache */ 655 #define PMC6_L2_IFETCH 0x28 656 #define PMC6_L2_LD 0x29 657 #define PMC6_L2_ST 0x2a 658 #define PMC6_L2_LINES_IN 0x24 659 #define PMC6_L2_LINES_OUT 0x26 660 #define PMC6_L2_M_LINES_INM 0x25 661 #define PMC6_L2_M_LINES_OUTM 0x27 662 #define PMC6_L2_RQSTS 0x2e 663 #define PMC6_L2_ADS 0x21 664 #define PMC6_L2_DBUS_BUSY 0x22 665 #define PMC6_L2_DBUS_BUSY_RD 0x23 666 667 /* External Bus Logic */ 668 #define PMC6_BUS_DRDY_CLOCKS 0x62 669 #define PMC6_BUS_LOCK_CLOCKS 0x63 670 #define PMC6_BUS_REQ_OUTSTANDING 0x60 671 #define PMC6_BUS_TRAN_BRD 0x65 672 #define PMC6_BUS_TRAN_RFO 0x66 673 #define PMC6_BUS_TRANS_WB 0x67 674 #define PMC6_BUS_TRAN_IFETCH 0x68 675 #define PMC6_BUS_TRAN_INVAL 0x69 676 #define PMC6_BUS_TRAN_PWR 0x6a 677 #define PMC6_BUS_TRANS_P 0x6b 678 #define PMC6_BUS_TRANS_IO 0x6c 679 #define PMC6_BUS_TRAN_DEF 0x6d 680 #define PMC6_BUS_TRAN_BURST 0x6e 681 #define PMC6_BUS_TRAN_ANY 0x70 682 #define PMC6_BUS_TRAN_MEM 0x6f 683 #define PMC6_BUS_DATA_RCV 0x64 684 #define PMC6_BUS_BNR_DRV 0x61 685 #define PMC6_BUS_HIT_DRV 0x7a 686 #define PMC6_BUS_HITM_DRDV 0x7b 687 #define PMC6_BUS_SNOOP_STALL 0x7e 688 689 /* Floating Point Unit */ 690 #define PMC6_FLOPS 0xc1 691 #define PMC6_FP_COMP_OPS_EXE 0x10 692 #define PMC6_FP_ASSIST 0x11 693 #define PMC6_MUL 0x12 694 #define PMC6_DIV 0x12 695 #define PMC6_CYCLES_DIV_BUSY 0x14 696 697 /* Memory Ordering */ 698 #define PMC6_LD_BLOCKS 0x03 699 #define PMC6_SB_DRAINS 0x04 700 #define PMC6_MISALIGN_MEM_REF 0x05 701 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 702 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 703 704 /* Instruction Decoding and Retirement */ 705 #define PMC6_INST_RETIRED 0xc0 706 #define PMC6_UOPS_RETIRED 0xc2 707 #define PMC6_INST_DECODED 0xd0 708 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 709 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 710 711 /* Interrupts */ 712 #define PMC6_HW_INT_RX 0xc8 713 #define PMC6_CYCLES_INT_MASKED 0xc6 714 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 715 716 /* Branches */ 717 #define PMC6_BR_INST_RETIRED 0xc4 718 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 719 #define PMC6_BR_TAKEN_RETIRED 0xc9 720 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 721 #define PMC6_BR_INST_DECODED 0xe0 722 #define PMC6_BTB_MISSES 0xe2 723 #define PMC6_BR_BOGUS 0xe4 724 #define PMC6_BACLEARS 0xe6 725 726 /* Stalls */ 727 #define PMC6_RESOURCE_STALLS 0xa2 728 #define PMC6_PARTIAL_RAT_STALLS 0xd2 729 730 /* Segment Register Loads */ 731 #define PMC6_SEGMENT_REG_LOADS 0x06 732 733 /* Clocks */ 734 #define PMC6_CPU_CLK_UNHALTED 0x79 735 736 /* MMX Unit */ 737 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 738 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 739 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 740 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 741 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 742 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 743 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 744 745 /* Segment Register Renaming */ 746 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 747 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 748 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 749 750 /* VIA C3 crypto featureset: for i386_has_xcrypt */ 751 #define C3_HAS_AES 1 /* cpu has AES */ 752 #define C3_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 753 #define C3_HAS_MM 4 /* cpu has RSA instructions */ 754 #define C3_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 755 756 /* Centaur Extended Feature flags */ 757 #define C3_CPUID_HAS_RNG 0x000004 758 #define C3_CPUID_DO_RNG 0x000008 759 #define C3_CPUID_HAS_ACE 0x000040 760 #define C3_CPUID_DO_ACE 0x000080 761 #define C3_CPUID_HAS_ACE2 0x000100 762 #define C3_CPUID_DO_ACE2 0x000200 763 #define C3_CPUID_HAS_PHE 0x000400 764 #define C3_CPUID_DO_PHE 0x000800 765 #define C3_CPUID_HAS_PMM 0x001000 766 #define C3_CPUID_DO_PMM 0x002000 767 768 /* VIA C3 xcrypt-* instruction context control options */ 769 #define C3_CRYPT_CWLO_ROUND_M 0x0000000f 770 #define C3_CRYPT_CWLO_ALG_M 0x00000070 771 #define C3_CRYPT_CWLO_ALG_AES 0x00000000 772 #define C3_CRYPT_CWLO_KEYGEN_M 0x00000080 773 #define C3_CRYPT_CWLO_KEYGEN_HW 0x00000000 774 #define C3_CRYPT_CWLO_KEYGEN_SW 0x00000080 775 #define C3_CRYPT_CWLO_NORMAL 0x00000000 776 #define C3_CRYPT_CWLO_INTERMEDIATE 0x00000100 777 #define C3_CRYPT_CWLO_ENCRYPT 0x00000000 778 #define C3_CRYPT_CWLO_DECRYPT 0x00000200 779 #define C3_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 780 #define C3_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 781 #define C3_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 782 783 /* Intel Silicon Debug */ 784 #define IA32_DEBUG_INTERFACE 0xc80 785 #define IA32_DEBUG_INTERFACE_ENABLE 0x00000001 786 #define IA32_DEBUG_INTERFACE_LOCK 0x40000000 787 #define IA32_DEBUG_INTERFACE_MASK 0x80000000 788 789 /* 790 * PAT 791 */ 792 #define PATENTRY(n, type) ((uint64_t)type << ((n) * 8)) 793 #define PAT_UC 0x0UL 794 #define PAT_WC 0x1UL 795 #define PAT_WT 0x4UL 796 #define PAT_WP 0x5UL 797 #define PAT_WB 0x6UL 798 #define PAT_UCMINUS 0x7UL 799 800 /* 801 * XSAVE subfeatures (cpuid 0xd, leaf 1) 802 */ 803 #define XSAVE_XSAVEOPT 0x1UL 804 #define XSAVE_XSAVEC 0x2UL 805 #define XSAVE_XGETBV1 0x4UL 806 #define XSAVE_XSAVES 0x8UL 807