1*67218ad0Smickey /* $OpenBSD: amd756reg.h,v 1.1 2000/11/07 18:21:22 mickey Exp $ */ 2*67218ad0Smickey /* $NetBSD$ */ 3*67218ad0Smickey 4*67218ad0Smickey /* 5*67218ad0Smickey * Copyright (c) 1999, by UCHIYAMA Yasushi 6*67218ad0Smickey * All rights reserved. 7*67218ad0Smickey * 8*67218ad0Smickey * Redistribution and use in source and binary forms, with or without 9*67218ad0Smickey * modification, are permitted provided that the following conditions 10*67218ad0Smickey * are met: 11*67218ad0Smickey * 1. Redistributions of source code must retain the above copyright 12*67218ad0Smickey * notice, this list of conditions and the following disclaimer. 13*67218ad0Smickey * 2. The name of the developer may NOT be used to endorse or promote products 14*67218ad0Smickey * derived from this software without specific prior written permission. 15*67218ad0Smickey * 16*67218ad0Smickey * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17*67218ad0Smickey * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18*67218ad0Smickey * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19*67218ad0Smickey * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20*67218ad0Smickey * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21*67218ad0Smickey * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22*67218ad0Smickey * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23*67218ad0Smickey * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24*67218ad0Smickey * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25*67218ad0Smickey * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26*67218ad0Smickey * SUCH DAMAGE. 27*67218ad0Smickey */ 28*67218ad0Smickey 29*67218ad0Smickey /* 30*67218ad0Smickey * Register definitions for the AMD756 Peripheral Bus Controller. 31*67218ad0Smickey */ 32*67218ad0Smickey 33*67218ad0Smickey /* 34*67218ad0Smickey * Edge Triggered Interrupt Select register. (0x54) 35*67218ad0Smickey * bits 7-4: reserved 36*67218ad0Smickey * bit 3: Edge Triggered Interrupt Select for PCI Interrupt D 37*67218ad0Smickey * bit 2: Edge Triggered Interrupt Select for PCI Interrupt C 38*67218ad0Smickey * bit 1: Edge Triggered Interrupt Select for PCI Interrupt B 39*67218ad0Smickey * bit 0: Edge Triggered Interrupt Select for PCI Interrupt A 40*67218ad0Smickey * 0 = active Low and level triggered 41*67218ad0Smickey * 1 = active High and edge triggered 42*67218ad0Smickey * 43*67218ad0Smickey * PIRQ Select register. (0x56-57) 44*67218ad0Smickey * bits 15-12: PIRQD# Select 45*67218ad0Smickey * bits 11-8: PIRQD# Select 46*67218ad0Smickey * bits 7-4: PIRQD# Select 47*67218ad0Smickey * bits 3-0: PIRQD# Select 48*67218ad0Smickey * 0000: Reserved 0100: IRQ4 1000: Reserved 1100: IRQ12 49*67218ad0Smickey * 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved 50*67218ad0Smickey * 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14 51*67218ad0Smickey * 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15 52*67218ad0Smickey */ 53*67218ad0Smickey #define AMD756_CFG_PIR 0x54 54*67218ad0Smickey 55*67218ad0Smickey #define AMD756_GET_EDGESEL(ph) \ 56*67218ad0Smickey (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) & 0xff) 57*67218ad0Smickey 58*67218ad0Smickey #define AMD756_GET_PIIRQSEL(ph) \ 59*67218ad0Smickey (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) >> 16) 60*67218ad0Smickey 61*67218ad0Smickey #define AMD756_SET_EDGESEL(ph, n) \ 62*67218ad0Smickey pci_conf_write((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR, \ 63*67218ad0Smickey (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) \ 64*67218ad0Smickey & 0xffff0000) | (n)) 65*67218ad0Smickey 66*67218ad0Smickey #define AMD756_SET_PIIRQSEL(ph, n) \ 67*67218ad0Smickey pci_conf_write((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR, \ 68*67218ad0Smickey (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) \ 69*67218ad0Smickey & 0x000000ff) | ((n) << 16)) 70*67218ad0Smickey 71*67218ad0Smickey #define AMD756_PIRQ_MASK 0xdefa 72*67218ad0Smickey #define AMD756_LEGAL_LINK(link) ((link) >= 0 && (link) <= 3) 73*67218ad0Smickey #define AMD756_LEGAL_IRQ(irq) \ 74*67218ad0Smickey ((irq) >= 0 && (irq) <= 15 && ((1 << (irq)) & AMD756_PIRQ_MASK) != 0) 75*67218ad0Smickey 76