1 /* $OpenBSD: glxsb.c,v 1.28 2014/07/12 18:44:42 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Tom Cosgrove <tom@openbsd.org> 5 * Copyright (c) 2003, 2004 Theo de Raadt 6 * Copyright (c) 2003 Jason Wright 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for the security block on the AMD Geode LX processors 23 * http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33234d_lx_ds.pdf 24 */ 25 26 #include <sys/param.h> 27 #include <sys/systm.h> 28 #include <sys/device.h> 29 #include <sys/malloc.h> 30 #include <sys/mbuf.h> 31 #include <sys/types.h> 32 #include <sys/timeout.h> 33 34 #include <machine/bus.h> 35 #include <machine/cpufunc.h> 36 37 #include <dev/rndvar.h> 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 41 #ifdef CRYPTO 42 #include <crypto/cryptodev.h> 43 #include <crypto/rijndael.h> 44 #include <crypto/xform.h> 45 #include <crypto/cryptosoft.h> 46 #endif 47 48 #define SB_GLD_MSR_CAP 0x58002000 /* RO - Capabilities */ 49 #define SB_GLD_MSR_CONFIG 0x58002001 /* RW - Master Config */ 50 #define SB_GLD_MSR_SMI 0x58002002 /* RW - SMI */ 51 #define SB_GLD_MSR_ERROR 0x58002003 /* RW - Error */ 52 #define SB_GLD_MSR_PM 0x58002004 /* RW - Power Mgmt */ 53 #define SB_GLD_MSR_DIAG 0x58002005 /* RW - Diagnostic */ 54 #define SB_GLD_MSR_CTRL 0x58002006 /* RW - Security Block Cntrl */ 55 56 /* For GLD_MSR_CTRL: */ 57 #define SB_GMC_DIV0 0x0000 /* AES update divisor values */ 58 #define SB_GMC_DIV1 0x0001 59 #define SB_GMC_DIV2 0x0002 60 #define SB_GMC_DIV3 0x0003 61 #define SB_GMC_DIV_MASK 0x0003 62 #define SB_GMC_SBI 0x0004 /* AES swap bits */ 63 #define SB_GMC_SBY 0x0008 /* AES swap bytes */ 64 #define SB_GMC_TW 0x0010 /* Time write (EEPROM) */ 65 #define SB_GMC_T_SEL0 0x0000 /* RNG post-proc: none */ 66 #define SB_GMC_T_SEL1 0x0100 /* RNG post-proc: LFSR */ 67 #define SB_GMC_T_SEL2 0x0200 /* RNG post-proc: whitener */ 68 #define SB_GMC_T_SEL3 0x0300 /* RNG LFSR+whitener */ 69 #define SB_GMC_T_SEL_MASK 0x0300 70 #define SB_GMC_T_NE 0x0400 /* Noise (generator) Enable */ 71 #define SB_GMC_T_TM 0x0800 /* RNG test mode */ 72 /* (deterministic) */ 73 74 /* Security Block configuration/control registers (offsets from base) */ 75 76 #define SB_CTL_A 0x0000 /* RW - SB Control A */ 77 #define SB_CTL_B 0x0004 /* RW - SB Control B */ 78 #define SB_AES_INT 0x0008 /* RW - SB AES Interrupt */ 79 #define SB_SOURCE_A 0x0010 /* RW - Source A */ 80 #define SB_DEST_A 0x0014 /* RW - Destination A */ 81 #define SB_LENGTH_A 0x0018 /* RW - Length A */ 82 #define SB_SOURCE_B 0x0020 /* RW - Source B */ 83 #define SB_DEST_B 0x0024 /* RW - Destination B */ 84 #define SB_LENGTH_B 0x0028 /* RW - Length B */ 85 #define SB_WKEY 0x0030 /* WO - Writable Key 0-3 */ 86 #define SB_WKEY_0 0x0030 /* WO - Writable Key 0 */ 87 #define SB_WKEY_1 0x0034 /* WO - Writable Key 1 */ 88 #define SB_WKEY_2 0x0038 /* WO - Writable Key 2 */ 89 #define SB_WKEY_3 0x003C /* WO - Writable Key 3 */ 90 #define SB_CBC_IV 0x0040 /* RW - CBC IV 0-3 */ 91 #define SB_CBC_IV_0 0x0040 /* RW - CBC IV 0 */ 92 #define SB_CBC_IV_1 0x0044 /* RW - CBC IV 1 */ 93 #define SB_CBC_IV_2 0x0048 /* RW - CBC IV 2 */ 94 #define SB_CBC_IV_3 0x004C /* RW - CBC IV 3 */ 95 #define SB_RANDOM_NUM 0x0050 /* RW - Random Number */ 96 #define SB_RANDOM_NUM_STATUS 0x0054 /* RW - Random Number Status */ 97 #define SB_EEPROM_COMM 0x0800 /* RW - EEPROM Command */ 98 #define SB_EEPROM_ADDR 0x0804 /* RW - EEPROM Address */ 99 #define SB_EEPROM_DATA 0x0808 /* RW - EEPROM Data */ 100 #define SB_EEPROM_SEC_STATE 0x080C /* RW - EEPROM Security State */ 101 102 /* For SB_CTL_A and _B */ 103 #define SB_CTL_ST 0x0001 /* Start operation (enc/dec) */ 104 #define SB_CTL_ENC 0x0002 /* Encrypt (0 is decrypt) */ 105 #define SB_CTL_DEC 0x0000 /* Decrypt */ 106 #define SB_CTL_WK 0x0004 /* Use writable key (we set) */ 107 #define SB_CTL_DC 0x0008 /* Destination coherent */ 108 #define SB_CTL_SC 0x0010 /* Source coherent */ 109 #define SB_CTL_CBC 0x0020 /* CBC (0 is ECB) */ 110 111 /* For SB_AES_INT */ 112 #define SB_AI_DISABLE_AES_A 0x00001 /* Disable AES A compl int */ 113 #define SB_AI_ENABLE_AES_A 0x00000 /* Enable AES A compl int */ 114 #define SB_AI_DISABLE_AES_B 0x00002 /* Disable AES B compl int */ 115 #define SB_AI_ENABLE_AES_B 0x00000 /* Enable AES B compl int */ 116 #define SB_AI_DISABLE_EEPROM 0x00004 /* Disable EEPROM op comp int */ 117 #define SB_AI_ENABLE_EEPROM 0x00000 /* Enable EEPROM op compl int */ 118 #define SB_AI_AES_A_COMPLETE 0x10000 /* AES A operation complete */ 119 #define SB_AI_AES_B_COMPLETE 0x20000 /* AES B operation complete */ 120 #define SB_AI_EEPROM_COMPLETE 0x40000 /* EEPROM operation complete */ 121 122 #define SB_RNS_TRNG_VALID 0x0001 /* in SB_RANDOM_NUM_STATUS */ 123 124 #define SB_MEM_SIZE 0x0810 /* Size of memory block */ 125 126 #define SB_AES_ALIGN 0x0010 /* Source and dest buffers */ 127 /* must be 16-byte aligned */ 128 #define SB_AES_BLOCK_SIZE 0x0010 129 130 /* 131 * The Geode LX security block AES acceleration doesn't perform scatter- 132 * gather: it just takes source and destination addresses. Therefore the 133 * plain- and ciphertexts need to be contiguous. To this end, we allocate 134 * a buffer for both, and accept the overhead of copying in and out. If 135 * the number of bytes in one operation is bigger than allowed for by the 136 * buffer (buffer is twice the size of the max length, as it has both input 137 * and output) then we have to perform multiple encryptions/decryptions. 138 */ 139 #define GLXSB_MAX_AES_LEN 16384 140 141 #ifdef CRYPTO 142 struct glxsb_dma_map { 143 bus_dmamap_t dma_map; 144 bus_dma_segment_t dma_seg; 145 int dma_nsegs; 146 int dma_size; 147 caddr_t dma_vaddr; 148 uint32_t dma_paddr; 149 }; 150 struct glxsb_session { 151 uint32_t ses_key[4]; 152 int ses_klen; 153 int ses_used; 154 struct swcr_data *ses_swd_auth; 155 struct swcr_data *ses_swd_enc; 156 }; 157 #endif /* CRYPTO */ 158 159 struct glxsb_softc { 160 struct device sc_dev; 161 bus_space_tag_t sc_iot; 162 bus_space_handle_t sc_ioh; 163 struct timeout sc_to; 164 165 #ifdef CRYPTO 166 bus_dma_tag_t sc_dmat; 167 struct glxsb_dma_map sc_dma; 168 int32_t sc_cid; 169 int sc_nsessions; 170 struct glxsb_session *sc_sessions; 171 #endif /* CRYPTO */ 172 173 uint64_t save_gld_msr; 174 }; 175 176 int glxsb_match(struct device *, void *, void *); 177 void glxsb_attach(struct device *, struct device *, void *); 178 int glxsb_activate(struct device *, int); 179 void glxsb_rnd(void *); 180 181 struct cfattach glxsb_ca = { 182 sizeof(struct glxsb_softc), glxsb_match, glxsb_attach, NULL, 183 glxsb_activate 184 }; 185 186 struct cfdriver glxsb_cd = { 187 NULL, "glxsb", DV_DULL 188 }; 189 190 191 #ifdef CRYPTO 192 193 #define GLXSB_SESSION(sid) ((sid) & 0x0fffffff) 194 #define GLXSB_SID(crd,ses) (((crd) << 28) | ((ses) & 0x0fffffff)) 195 196 static struct glxsb_softc *glxsb_sc; 197 198 int glxsb_crypto_setup(struct glxsb_softc *); 199 int glxsb_crypto_newsession(uint32_t *, struct cryptoini *); 200 int glxsb_crypto_process(struct cryptop *); 201 int glxsb_crypto_freesession(uint64_t); 202 static __inline void glxsb_aes(struct glxsb_softc *, uint32_t, uint32_t, 203 uint32_t, void *, int, void *); 204 205 int glxsb_dma_alloc(struct glxsb_softc *, int, struct glxsb_dma_map *); 206 void glxsb_dma_pre_op(struct glxsb_softc *, struct glxsb_dma_map *); 207 void glxsb_dma_post_op(struct glxsb_softc *, struct glxsb_dma_map *); 208 void glxsb_dma_free(struct glxsb_softc *, struct glxsb_dma_map *); 209 210 #endif /* CRYPTO */ 211 212 213 int 214 glxsb_match(struct device *parent, void *match, void *aux) 215 { 216 struct pci_attach_args *pa = aux; 217 218 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 219 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_GEODE_LX_CRYPTO) 220 return (1); 221 222 return (0); 223 } 224 225 void 226 glxsb_attach(struct device *parent, struct device *self, void *aux) 227 { 228 struct glxsb_softc *sc = (void *) self; 229 struct pci_attach_args *pa = aux; 230 bus_addr_t membase; 231 bus_size_t memsize; 232 uint64_t msr; 233 #ifdef CRYPTO 234 uint32_t intr; 235 #endif 236 237 msr = rdmsr(SB_GLD_MSR_CAP); 238 if ((msr & 0xFFFF00) != 0x130400) { 239 printf(": unknown ID 0x%x\n", (int) ((msr & 0xFFFF00) >> 16)); 240 return; 241 } 242 243 /* printf(": revision %d", (int) (msr & 0xFF)); */ 244 245 /* Map in the security block configuration/control registers */ 246 if (pci_mapreg_map(pa, PCI_MAPREG_START, 247 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_iot, 248 &sc->sc_ioh, &membase, &memsize, SB_MEM_SIZE)) { 249 printf(": can't find mem space\n"); 250 return; 251 } 252 253 /* 254 * Configure the Security Block. 255 * 256 * We want to enable the noise generator (T_NE), and enable the 257 * linear feedback shift register and whitener post-processing 258 * (T_SEL = 3). Also ensure that test mode (deterministic values) 259 * is disabled. 260 */ 261 msr = rdmsr(SB_GLD_MSR_CTRL); 262 msr &= ~(SB_GMC_T_TM | SB_GMC_T_SEL_MASK); 263 msr |= SB_GMC_T_NE | SB_GMC_T_SEL3; 264 #if 0 265 msr |= SB_GMC_SBI | SB_GMC_SBY; /* for AES, if necessary */ 266 #endif 267 wrmsr(SB_GLD_MSR_CTRL, msr); 268 269 /* Install a periodic collector for the "true" (AMD's word) RNG */ 270 timeout_set(&sc->sc_to, glxsb_rnd, sc); 271 glxsb_rnd(sc); 272 printf(": RNG"); 273 274 #ifdef CRYPTO 275 /* We don't have an interrupt handler, so disable completion INTs */ 276 intr = SB_AI_DISABLE_AES_A | SB_AI_DISABLE_AES_B | 277 SB_AI_DISABLE_EEPROM | SB_AI_AES_A_COMPLETE | 278 SB_AI_AES_B_COMPLETE | SB_AI_EEPROM_COMPLETE; 279 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_AES_INT, intr); 280 281 sc->sc_dmat = pa->pa_dmat; 282 283 if (glxsb_crypto_setup(sc)) 284 printf(" AES"); 285 #endif 286 287 printf("\n"); 288 } 289 290 int 291 glxsb_activate(struct device *self, int act) 292 { 293 struct glxsb_softc *sc = (struct glxsb_softc *)self; 294 295 switch (act) { 296 case DVACT_QUIESCE: 297 /* XXX should wait for current crypto op to finish */ 298 break; 299 case DVACT_SUSPEND: 300 sc->save_gld_msr = rdmsr(SB_GLD_MSR_CTRL); 301 break; 302 case DVACT_RESUME: 303 wrmsr(SB_GLD_MSR_CTRL, sc->save_gld_msr); 304 break; 305 } 306 return (0); 307 } 308 309 void 310 glxsb_rnd(void *v) 311 { 312 struct glxsb_softc *sc = v; 313 uint32_t status, value; 314 315 status = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SB_RANDOM_NUM_STATUS); 316 if (status & SB_RNS_TRNG_VALID) { 317 value = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SB_RANDOM_NUM); 318 add_true_randomness(value); 319 } 320 321 timeout_add_msec(&sc->sc_to, 10); 322 } 323 324 #ifdef CRYPTO 325 int 326 glxsb_crypto_setup(struct glxsb_softc *sc) 327 { 328 int algs[CRYPTO_ALGORITHM_MAX + 1]; 329 330 /* Allocate a contiguous DMA-able buffer to work in */ 331 if (glxsb_dma_alloc(sc, GLXSB_MAX_AES_LEN * 2, &sc->sc_dma) != 0) 332 return 0; 333 334 bzero(algs, sizeof(algs)); 335 algs[CRYPTO_AES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED; 336 algs[CRYPTO_MD5_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED; 337 algs[CRYPTO_SHA1_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED; 338 algs[CRYPTO_RIPEMD160_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED; 339 algs[CRYPTO_SHA2_256_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED; 340 algs[CRYPTO_SHA2_384_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED; 341 algs[CRYPTO_SHA2_512_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED; 342 343 sc->sc_cid = crypto_get_driverid(0); 344 if (sc->sc_cid < 0) 345 return 0; 346 347 crypto_register(sc->sc_cid, algs, glxsb_crypto_newsession, 348 glxsb_crypto_freesession, glxsb_crypto_process); 349 350 sc->sc_nsessions = 0; 351 352 glxsb_sc = sc; 353 354 return 1; 355 } 356 357 int 358 glxsb_crypto_newsession(uint32_t *sidp, struct cryptoini *cri) 359 { 360 struct glxsb_softc *sc = glxsb_sc; 361 struct glxsb_session *ses = NULL; 362 struct auth_hash *axf; 363 struct enc_xform *txf; 364 struct cryptoini *c; 365 struct swcr_data *swd; 366 int sesn, i; 367 368 if (sc == NULL || sidp == NULL || cri == NULL) 369 return (EINVAL); 370 371 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 372 if (sc->sc_sessions[sesn].ses_used == 0) { 373 ses = &sc->sc_sessions[sesn]; 374 break; 375 } 376 } 377 378 if (ses == NULL) { 379 sesn = sc->sc_nsessions; 380 ses = malloc((sesn + 1) * sizeof(*ses), M_DEVBUF, M_NOWAIT); 381 if (ses == NULL) 382 return (ENOMEM); 383 if (sesn != 0) { 384 bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); 385 explicit_bzero(sc->sc_sessions, sesn * sizeof(*ses)); 386 free(sc->sc_sessions, M_DEVBUF, 0); 387 } 388 sc->sc_sessions = ses; 389 ses = &sc->sc_sessions[sesn]; 390 sc->sc_nsessions++; 391 } 392 393 bzero(ses, sizeof(*ses)); 394 ses->ses_used = 1; 395 396 for (c = cri; c != NULL; c = c->cri_next) { 397 switch (c->cri_alg) { 398 case CRYPTO_AES_CBC: 399 400 if (c->cri_klen != 128) { 401 swd = malloc(sizeof(struct swcr_data), 402 M_CRYPTO_DATA, M_NOWAIT|M_ZERO); 403 if (swd == NULL) { 404 glxsb_crypto_freesession(sesn); 405 return (ENOMEM); 406 } 407 ses->ses_swd_enc = swd; 408 txf = &enc_xform_rijndael128; 409 if (txf->ctxsize > 0) { 410 swd->sw_kschedule = 411 malloc(txf->ctxsize, 412 M_CRYPTO_DATA, 413 M_NOWAIT|M_ZERO); 414 if (swd->sw_kschedule == NULL) { 415 glxsb_crypto_freesession(sesn); 416 return (EINVAL); 417 } 418 } 419 if (txf->setkey(swd->sw_kschedule, c->cri_key, 420 c->cri_klen / 8) < 0) { 421 glxsb_crypto_freesession(sesn); 422 return (EINVAL); 423 } 424 swd->sw_exf = txf; 425 break; 426 } 427 428 ses->ses_klen = c->cri_klen; 429 430 /* Copy the key (Geode LX wants the primary key only) */ 431 bcopy(c->cri_key, ses->ses_key, sizeof(ses->ses_key)); 432 break; 433 434 case CRYPTO_MD5_HMAC: 435 axf = &auth_hash_hmac_md5_96; 436 goto authcommon; 437 case CRYPTO_SHA1_HMAC: 438 axf = &auth_hash_hmac_sha1_96; 439 goto authcommon; 440 case CRYPTO_RIPEMD160_HMAC: 441 axf = &auth_hash_hmac_ripemd_160_96; 442 goto authcommon; 443 case CRYPTO_SHA2_256_HMAC: 444 axf = &auth_hash_hmac_sha2_256_128; 445 goto authcommon; 446 case CRYPTO_SHA2_384_HMAC: 447 axf = &auth_hash_hmac_sha2_384_192; 448 goto authcommon; 449 case CRYPTO_SHA2_512_HMAC: 450 axf = &auth_hash_hmac_sha2_512_256; 451 authcommon: 452 swd = malloc(sizeof(struct swcr_data), M_CRYPTO_DATA, 453 M_NOWAIT|M_ZERO); 454 if (swd == NULL) { 455 glxsb_crypto_freesession(sesn); 456 return (ENOMEM); 457 } 458 ses->ses_swd_auth = swd; 459 460 swd->sw_ictx = malloc(axf->ctxsize, M_CRYPTO_DATA, 461 M_NOWAIT); 462 if (swd->sw_ictx == NULL) { 463 glxsb_crypto_freesession(sesn); 464 return (ENOMEM); 465 } 466 467 swd->sw_octx = malloc(axf->ctxsize, M_CRYPTO_DATA, 468 M_NOWAIT); 469 if (swd->sw_octx == NULL) { 470 glxsb_crypto_freesession(sesn); 471 return (ENOMEM); 472 } 473 474 for (i = 0; i < c->cri_klen / 8; i++) 475 c->cri_key[i] ^= HMAC_IPAD_VAL; 476 477 axf->Init(swd->sw_ictx); 478 axf->Update(swd->sw_ictx, c->cri_key, c->cri_klen / 8); 479 axf->Update(swd->sw_ictx, hmac_ipad_buffer, 480 axf->blocksize - (c->cri_klen / 8)); 481 482 for (i = 0; i < c->cri_klen / 8; i++) 483 c->cri_key[i] ^= (HMAC_IPAD_VAL ^ 484 HMAC_OPAD_VAL); 485 486 axf->Init(swd->sw_octx); 487 axf->Update(swd->sw_octx, c->cri_key, c->cri_klen / 8); 488 axf->Update(swd->sw_octx, hmac_opad_buffer, 489 axf->blocksize - (c->cri_klen / 8)); 490 491 for (i = 0; i < c->cri_klen / 8; i++) 492 c->cri_key[i] ^= HMAC_OPAD_VAL; 493 494 swd->sw_axf = axf; 495 swd->sw_alg = c->cri_alg; 496 497 break; 498 default: 499 glxsb_crypto_freesession(sesn); 500 return (EINVAL); 501 } 502 } 503 504 *sidp = GLXSB_SID(0, sesn); 505 return (0); 506 } 507 508 int 509 glxsb_crypto_freesession(uint64_t tid) 510 { 511 struct glxsb_softc *sc = glxsb_sc; 512 struct swcr_data *swd; 513 struct auth_hash *axf; 514 struct enc_xform *txf; 515 int sesn; 516 uint32_t sid = ((uint32_t)tid) & 0xffffffff; 517 518 if (sc == NULL) 519 return (EINVAL); 520 sesn = GLXSB_SESSION(sid); 521 if (sesn >= sc->sc_nsessions) 522 return (EINVAL); 523 if ((swd = sc->sc_sessions[sesn].ses_swd_enc)) { 524 txf = swd->sw_exf; 525 526 if (swd->sw_kschedule) { 527 explicit_bzero(swd->sw_kschedule, txf->ctxsize); 528 free(swd->sw_kschedule, M_CRYPTO_DATA, 0); 529 } 530 free(swd, M_CRYPTO_DATA, 0); 531 } 532 if ((swd = sc->sc_sessions[sesn].ses_swd_auth)) { 533 axf = swd->sw_axf; 534 535 if (swd->sw_ictx) { 536 explicit_bzero(swd->sw_ictx, axf->ctxsize); 537 free(swd->sw_ictx, M_CRYPTO_DATA, 0); 538 } 539 if (swd->sw_octx) { 540 explicit_bzero(swd->sw_octx, axf->ctxsize); 541 free(swd->sw_octx, M_CRYPTO_DATA, 0); 542 } 543 free(swd, M_CRYPTO_DATA, 0); 544 } 545 explicit_bzero(&sc->sc_sessions[sesn], sizeof(sc->sc_sessions[sesn])); 546 return (0); 547 } 548 549 /* 550 * Must be called at splnet() or higher 551 */ 552 static __inline void 553 glxsb_aes(struct glxsb_softc *sc, uint32_t control, uint32_t psrc, 554 uint32_t pdst, void *key, int len, void *iv) 555 { 556 uint32_t status; 557 int i; 558 559 if (len & 0xF) { 560 printf("%s: len must be a multiple of 16 (not %d)\n", 561 sc->sc_dev.dv_xname, len); 562 return; 563 } 564 565 /* Set the source */ 566 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_SOURCE_A, psrc); 567 568 /* Set the destination address */ 569 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_DEST_A, pdst); 570 571 /* Set the data length */ 572 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_LENGTH_A, len); 573 574 /* Set the IV */ 575 if (iv != NULL) { 576 bus_space_write_region_4(sc->sc_iot, sc->sc_ioh, 577 SB_CBC_IV, iv, 4); 578 control |= SB_CTL_CBC; 579 } 580 581 /* Set the key */ 582 bus_space_write_region_4(sc->sc_iot, sc->sc_ioh, SB_WKEY, key, 4); 583 584 /* Ask the security block to do it */ 585 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_CTL_A, 586 control | SB_CTL_WK | SB_CTL_DC | SB_CTL_SC | SB_CTL_ST); 587 588 /* 589 * Now wait until it is done. 590 * 591 * We do a busy wait. Obviously the number of iterations of 592 * the loop required to perform the AES operation depends upon 593 * the number of bytes to process. 594 * 595 * On a 500 MHz Geode LX we see 596 * 597 * length (bytes) typical max iterations 598 * 16 12 599 * 64 22 600 * 256 59 601 * 1024 212 602 * 8192 1,537 603 * 604 * Since we have a maximum size of operation defined in 605 * GLXSB_MAX_AES_LEN, we use this constant to decide how long 606 * to wait. Allow an order of magnitude longer than it should 607 * really take, just in case. 608 */ 609 for (i = 0; i < GLXSB_MAX_AES_LEN * 10; i++) { 610 status = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SB_CTL_A); 611 612 if ((status & SB_CTL_ST) == 0) /* Done */ 613 return; 614 } 615 616 printf("%s: operation failed to complete\n", sc->sc_dev.dv_xname); 617 } 618 619 static int 620 glxsb_crypto_swauth(struct cryptop *crp, struct cryptodesc *crd, 621 struct swcr_data *sw, caddr_t buf) 622 { 623 int type; 624 625 if (crp->crp_flags & CRYPTO_F_IMBUF) 626 type = CRYPTO_BUF_MBUF; 627 else 628 type = CRYPTO_BUF_IOV; 629 630 return (swcr_authcompute(crp, crd, sw, buf, type)); 631 } 632 633 static int 634 glxsb_crypto_swenc(struct cryptop *crp, struct cryptodesc *crd, 635 struct swcr_data *sw, caddr_t buf) 636 { 637 int type; 638 639 if (crp->crp_flags & CRYPTO_F_IMBUF) 640 type = CRYPTO_BUF_MBUF; 641 else 642 type = CRYPTO_BUF_IOV; 643 644 return (swcr_encdec(crd, sw, buf, type)); 645 } 646 647 static int 648 glxsb_crypto_encdec(struct cryptop *crp, struct cryptodesc *crd, 649 struct glxsb_session *ses, struct glxsb_softc *sc, caddr_t buf) 650 { 651 char *op_src, *op_dst; 652 uint32_t op_psrc, op_pdst; 653 uint8_t op_iv[SB_AES_BLOCK_SIZE]; 654 int err = 0; 655 int len, tlen, xlen; 656 int offset; 657 uint32_t control; 658 659 if (crd == NULL || (crd->crd_len % SB_AES_BLOCK_SIZE) != 0) { 660 err = EINVAL; 661 goto out; 662 } 663 664 /* How much of our buffer will we need to use? */ 665 xlen = crd->crd_len > GLXSB_MAX_AES_LEN ? 666 GLXSB_MAX_AES_LEN : crd->crd_len; 667 668 /* 669 * XXX Check if we can have input == output on Geode LX. 670 * XXX In the meantime, use two separate (adjacent) buffers. 671 */ 672 op_src = sc->sc_dma.dma_vaddr; 673 op_dst = sc->sc_dma.dma_vaddr + xlen; 674 675 op_psrc = sc->sc_dma.dma_paddr; 676 op_pdst = sc->sc_dma.dma_paddr + xlen; 677 678 if (crd->crd_flags & CRD_F_ENCRYPT) { 679 control = SB_CTL_ENC; 680 if (crd->crd_flags & CRD_F_IV_EXPLICIT) 681 bcopy(crd->crd_iv, op_iv, sizeof(op_iv)); 682 else 683 arc4random_buf(op_iv, sizeof(op_iv)); 684 685 if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { 686 if (crp->crp_flags & CRYPTO_F_IMBUF) 687 err = m_copyback((struct mbuf *)crp->crp_buf, 688 crd->crd_inject, sizeof(op_iv), op_iv, 689 M_NOWAIT); 690 else if (crp->crp_flags & CRYPTO_F_IOV) 691 cuio_copyback((struct uio *)crp->crp_buf, 692 crd->crd_inject, sizeof(op_iv), op_iv); 693 else 694 bcopy(op_iv, 695 crp->crp_buf + crd->crd_inject, sizeof(op_iv)); 696 if (err) 697 goto out; 698 } 699 } else { 700 control = SB_CTL_DEC; 701 if (crd->crd_flags & CRD_F_IV_EXPLICIT) 702 bcopy(crd->crd_iv, op_iv, sizeof(op_iv)); 703 else { 704 if (crp->crp_flags & CRYPTO_F_IMBUF) 705 m_copydata((struct mbuf *)crp->crp_buf, 706 crd->crd_inject, sizeof(op_iv), op_iv); 707 else if (crp->crp_flags & CRYPTO_F_IOV) 708 cuio_copydata((struct uio *)crp->crp_buf, 709 crd->crd_inject, sizeof(op_iv), op_iv); 710 else 711 bcopy(crp->crp_buf + crd->crd_inject, 712 op_iv, sizeof(op_iv)); 713 } 714 } 715 716 offset = 0; 717 tlen = crd->crd_len; 718 719 /* Process the data in GLXSB_MAX_AES_LEN chunks */ 720 while (tlen > 0) { 721 len = (tlen > GLXSB_MAX_AES_LEN) ? GLXSB_MAX_AES_LEN : tlen; 722 723 if (crp->crp_flags & CRYPTO_F_IMBUF) 724 m_copydata((struct mbuf *)crp->crp_buf, 725 crd->crd_skip + offset, len, op_src); 726 else if (crp->crp_flags & CRYPTO_F_IOV) 727 cuio_copydata((struct uio *)crp->crp_buf, 728 crd->crd_skip + offset, len, op_src); 729 else 730 bcopy(crp->crp_buf + crd->crd_skip + offset, op_src, 731 len); 732 733 glxsb_dma_pre_op(sc, &sc->sc_dma); 734 735 glxsb_aes(sc, control, op_psrc, op_pdst, ses->ses_key, 736 len, op_iv); 737 738 glxsb_dma_post_op(sc, &sc->sc_dma); 739 740 if (crp->crp_flags & CRYPTO_F_IMBUF) 741 err = m_copyback((struct mbuf *)crp->crp_buf, 742 crd->crd_skip + offset, len, op_dst, M_NOWAIT); 743 else if (crp->crp_flags & CRYPTO_F_IOV) 744 cuio_copyback((struct uio *)crp->crp_buf, 745 crd->crd_skip + offset, len, op_dst); 746 else 747 bcopy(op_dst, crp->crp_buf + crd->crd_skip + offset, 748 len); 749 if (err) 750 break; 751 752 offset += len; 753 tlen -= len; 754 755 if (tlen > 0) { 756 /* Copy out last block for use as next iteration */ 757 if (crd->crd_flags & CRD_F_ENCRYPT) 758 bcopy(op_dst + len - sizeof(op_iv), op_iv, 759 sizeof(op_iv)); 760 else 761 bcopy(op_src + len - sizeof(op_iv), op_iv, 762 sizeof(op_iv)); 763 } 764 } 765 766 /* All AES processing has now been done. */ 767 explicit_bzero(sc->sc_dma.dma_vaddr, xlen * 2); 768 769 out: 770 return (err); 771 } 772 773 int 774 glxsb_crypto_process(struct cryptop *crp) 775 { 776 struct glxsb_softc *sc = glxsb_sc; 777 struct glxsb_session *ses; 778 struct cryptodesc *crd; 779 int sesn,err = 0; 780 int s; 781 782 s = splnet(); 783 784 if (crp == NULL || crp->crp_callback == NULL) { 785 err = EINVAL; 786 goto out; 787 } 788 crd = crp->crp_desc; 789 if (crd == NULL) { 790 err = EINVAL; 791 goto out; 792 } 793 794 sesn = GLXSB_SESSION(crp->crp_sid); 795 if (sesn >= sc->sc_nsessions) { 796 err = EINVAL; 797 goto out; 798 } 799 ses = &sc->sc_sessions[sesn]; 800 if (ses->ses_used == 0) { 801 err = EINVAL; 802 goto out; 803 } 804 805 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 806 switch (crd->crd_alg) { 807 case CRYPTO_AES_CBC: 808 if (ses->ses_swd_enc) { 809 if ((err = glxsb_crypto_swenc(crp, crd, ses->ses_swd_enc, 810 crp->crp_buf)) != 0) 811 goto out; 812 } else if ((err = glxsb_crypto_encdec(crp, crd, ses, sc, 813 crp->crp_buf)) != 0) 814 goto out; 815 break; 816 817 case CRYPTO_MD5_HMAC: 818 case CRYPTO_SHA1_HMAC: 819 case CRYPTO_RIPEMD160_HMAC: 820 case CRYPTO_SHA2_256_HMAC: 821 case CRYPTO_SHA2_384_HMAC: 822 case CRYPTO_SHA2_512_HMAC: 823 if ((err = glxsb_crypto_swauth(crp, crd, ses->ses_swd_auth, 824 crp->crp_buf)) != 0) 825 goto out; 826 break; 827 828 default: 829 err = EINVAL; 830 goto out; 831 } 832 } 833 834 out: 835 crp->crp_etype = err; 836 crypto_done(crp); 837 splx(s); 838 return (err); 839 } 840 841 int 842 glxsb_dma_alloc(struct glxsb_softc *sc, int size, struct glxsb_dma_map *dma) 843 { 844 int rc; 845 846 dma->dma_nsegs = 1; 847 dma->dma_size = size; 848 849 rc = bus_dmamap_create(sc->sc_dmat, size, dma->dma_nsegs, size, 850 0, BUS_DMA_NOWAIT, &dma->dma_map); 851 if (rc != 0) { 852 printf("%s: couldn't create DMA map for %d bytes (%d)\n", 853 sc->sc_dev.dv_xname, size, rc); 854 855 goto fail0; 856 } 857 858 rc = bus_dmamem_alloc(sc->sc_dmat, size, SB_AES_ALIGN, 0, 859 &dma->dma_seg, dma->dma_nsegs, &dma->dma_nsegs, BUS_DMA_NOWAIT); 860 if (rc != 0) { 861 printf("%s: couldn't allocate DMA memory of %d bytes (%d)\n", 862 sc->sc_dev.dv_xname, size, rc); 863 864 goto fail1; 865 } 866 867 rc = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, 1, size, 868 &dma->dma_vaddr, BUS_DMA_NOWAIT); 869 if (rc != 0) { 870 printf("%s: couldn't map DMA memory for %d bytes (%d)\n", 871 sc->sc_dev.dv_xname, size, rc); 872 873 goto fail2; 874 } 875 876 rc = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 877 size, NULL, BUS_DMA_NOWAIT); 878 if (rc != 0) { 879 printf("%s: couldn't load DMA memory for %d bytes (%d)\n", 880 sc->sc_dev.dv_xname, size, rc); 881 882 goto fail3; 883 } 884 885 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 886 887 return 0; 888 889 fail3: 890 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 891 fail2: 892 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nsegs); 893 fail1: 894 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 895 fail0: 896 return rc; 897 } 898 899 void 900 glxsb_dma_pre_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 901 { 902 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 0, dma->dma_size, 903 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 904 } 905 906 void 907 glxsb_dma_post_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 908 { 909 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 0, dma->dma_size, 910 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 911 } 912 913 void 914 glxsb_dma_free(struct glxsb_softc *sc, struct glxsb_dma_map *dma) 915 { 916 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 917 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 918 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nsegs); 919 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 920 } 921 922 #endif /* CRYPTO */ 923