1 /* $OpenBSD: pci_intr_fixup.c,v 1.64 2023/01/30 10:49:05 jsg Exp $ */ 2 /* $NetBSD: pci_intr_fixup.c,v 1.10 2000/08/10 21:18:27 soda Exp $ */ 3 4 /* 5 * Copyright (c) 2001 Michael Shalayeff 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 21 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /*- 30 * Copyright (c) 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 35 * NASA Ames Research Center. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 47 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 48 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 49 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 50 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 51 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 52 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 53 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 54 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 55 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 56 * POSSIBILITY OF SUCH DAMAGE. 57 */ 58 /* 59 * Copyright (c) 1999, by UCHIYAMA Yasushi 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions 64 * are met: 65 * 1. Redistributions of source code must retain the above copyright 66 * notice, this list of conditions and the following disclaimer. 67 * 2. The name of the developer may NOT be used to endorse or promote products 68 * derived from this software without specific prior written permission. 69 * 70 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 71 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 73 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 74 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 75 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 76 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 77 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 78 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 79 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 80 * SUCH DAMAGE. 81 */ 82 83 /* 84 * PCI Interrupt Router support. 85 */ 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/malloc.h> 90 #include <sys/queue.h> 91 #include <sys/device.h> 92 93 #include <machine/bus.h> 94 #include <machine/intr.h> 95 #include <machine/i82093var.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 #include <dev/pci/pcidevs.h> 100 101 #include <i386/pci/pcibiosvar.h> 102 103 struct pciintr_link_map { 104 int link, clink, irq, fixup_stage; 105 u_int16_t bitmap; 106 SIMPLEQ_ENTRY(pciintr_link_map) list; 107 }; 108 109 pciintr_icu_tag_t pciintr_icu_tag = NULL; 110 pciintr_icu_handle_t pciintr_icu_handle; 111 112 #ifdef PCIBIOS_IRQS_HINT 113 int pcibios_irqs_hint = PCIBIOS_IRQS_HINT; 114 #endif 115 116 struct pciintr_link_map *pciintr_link_lookup(int); 117 struct pcibios_intr_routing *pciintr_pir_lookup(int, int); 118 int pciintr_bitmap_count_irq(int, int *); 119 120 SIMPLEQ_HEAD(, pciintr_link_map) pciintr_link_map_list; 121 122 const struct pciintr_icu_table { 123 pci_vendor_id_t piit_vendor; 124 pci_product_id_t piit_product; 125 int (*piit_init)(pci_chipset_tag_t, 126 bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *, 127 pciintr_icu_handle_t *); 128 } pciintr_icu_table[] = { 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 130 piix_init }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_LPC, 132 piix_init }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371MX, 134 piix_init }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_ISA, 136 piix_init }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371FB_ISA, 138 piix_init }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371SB_ISA, 140 piix_init }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ISA, 142 piix_init }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 144 piix_init }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 146 piix_init }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 148 piix_init }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 150 piix_init }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 152 piix_init }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 154 piix_init }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 156 piix_init }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 158 piix_init }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 160 piix_init }, 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 162 piix_init }, 163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 164 piix_init }, 165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 166 piix_init }, 167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_LPC, 168 piix_init }, 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 170 piix_init }, 171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 172 piix_init }, 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 174 piix_init }, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 176 piix_init }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 178 piix_init }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 180 piix_init }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 182 piix_init }, 183 184 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558, 185 opti82c558_init }, 186 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C700, 187 opti82c700_init }, 188 189 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_OSB4, 190 osb4_init }, 191 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_CSB5, 192 osb4_init }, 193 194 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_ISA, 195 via82c586_init, }, 196 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C596A, 197 via82c586_init, }, 198 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C686A_ISA, 199 via82c586_init }, 200 201 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8231_ISA, 202 via8231_init }, 203 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233_ISA, 204 via8231_init }, 205 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233A_ISA, 206 via8231_init }, 207 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8235_ISA, 208 via8231_init }, 209 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237_ISA, 210 via8231_init }, 211 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237A_ISA, 212 via8231_init }, 213 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237S_ISA, 214 via8231_init }, 215 216 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503, 217 sis85c503_init }, 218 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_962, 219 sis85c503_init }, 220 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_963, 221 sis85c503_init }, 222 223 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC756_PMC, 224 amd756_init }, 225 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_766_PMC, 226 amd756_init }, 227 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_PMC, 228 amd756_init }, 229 230 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1533, 231 ali1543_init }, 232 233 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1543, 234 ali1543_init }, 235 236 { 0, 0, 237 NULL }, 238 }; 239 240 const struct pciintr_icu_table *pciintr_icu_lookup(pcireg_t); 241 242 const struct pciintr_icu_table * 243 pciintr_icu_lookup(pcireg_t id) 244 { 245 const struct pciintr_icu_table *piit; 246 247 for (piit = pciintr_icu_table; piit->piit_init != NULL; piit++) 248 if (PCI_VENDOR(id) == piit->piit_vendor && 249 PCI_PRODUCT(id) == piit->piit_product) 250 return (piit); 251 252 return (NULL); 253 } 254 255 struct pciintr_link_map * 256 pciintr_link_lookup(int link) 257 { 258 struct pciintr_link_map *l; 259 260 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 261 l = SIMPLEQ_NEXT(l, list)) 262 if (l->link == link) 263 return (l); 264 265 return (NULL); 266 } 267 268 static __inline struct pciintr_link_map * 269 pciintr_link_alloc(pci_chipset_tag_t pc, struct pcibios_intr_routing *pir, int pin) 270 { 271 int link = pir->linkmap[pin].link, clink, irq; 272 struct pciintr_link_map *l, *lstart; 273 274 if (pciintr_icu_tag != NULL) { 275 /* 276 * Get the canonical link value for this entry. 277 */ 278 if (pciintr_icu_getclink(pciintr_icu_tag, pciintr_icu_handle, 279 link, &clink) != 0) { 280 /* 281 * ICU doesn't understand the link value. 282 * Just ignore this PIR entry. 283 */ 284 PCIBIOS_PRINTV(("pciintr_link_alloc: bus %d device %d: " 285 "ignoring link 0x%02x\n", pir->bus, 286 PIR_DEVFUNC_DEVICE(pir->device), link)); 287 return (NULL); 288 } 289 290 /* 291 * Check the link value by asking the ICU for the 292 * canonical link value. 293 * Also, determine if this PIRQ is mapped to an IRQ. 294 */ 295 if (pciintr_icu_get_intr(pciintr_icu_tag, pciintr_icu_handle, 296 clink, &irq) != 0) { 297 /* 298 * ICU doesn't understand the canonical link value. 299 * Just ignore this PIR entry. 300 */ 301 PCIBIOS_PRINTV(("pciintr_link_alloc: " 302 "bus %d device %d link 0x%02x: " 303 "ignoring PIRQ 0x%02x\n", pir->bus, 304 PIR_DEVFUNC_DEVICE(pir->device), link, clink)); 305 return (NULL); 306 } 307 } 308 309 if ((l = malloc(sizeof(*l), M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) 310 return (NULL); 311 312 l->link = link; 313 l->bitmap = pir->linkmap[pin].bitmap; 314 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 315 l->clink = clink; 316 l->irq = irq; /* maybe I386_PCI_INTERRUPT_LINE_NO_CONNECTION */ 317 } else { 318 l->clink = link; 319 l->irq = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 320 } 321 322 lstart = SIMPLEQ_FIRST(&pciintr_link_map_list); 323 if (lstart == NULL || lstart->link < l->link) 324 SIMPLEQ_INSERT_TAIL(&pciintr_link_map_list, l, list); 325 else 326 SIMPLEQ_INSERT_HEAD(&pciintr_link_map_list, l, list); 327 328 return (l); 329 } 330 331 struct pcibios_intr_routing * 332 pciintr_pir_lookup(int bus, int device) 333 { 334 struct pcibios_intr_routing *pir; 335 int entry; 336 337 if (pcibios_pir_table == NULL) 338 return (NULL); 339 340 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 341 pir = &pcibios_pir_table[entry]; 342 if (pir->bus == bus && 343 PIR_DEVFUNC_DEVICE(pir->device) == device) 344 return (pir); 345 } 346 347 return (NULL); 348 } 349 350 int 351 pciintr_bitmap_count_irq(int irq_bitmap, int *irqp) 352 { 353 int i, bit, count = 0, irq = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 354 355 if (irq_bitmap != 0) 356 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) 357 if (irq_bitmap & bit) { 358 irq = i; 359 count++; 360 } 361 362 *irqp = irq; 363 return (count); 364 } 365 366 static __inline int 367 pciintr_link_init(pci_chipset_tag_t pc) 368 { 369 int entry, pin, link; 370 struct pcibios_intr_routing *pir; 371 struct pciintr_link_map *l; 372 373 if (pcibios_pir_table == NULL) { 374 /* No PIR table; can't do anything. */ 375 printf("pciintr_link_init: no PIR table\n"); 376 return (1); 377 } 378 379 SIMPLEQ_INIT(&pciintr_link_map_list); 380 381 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 382 pir = &pcibios_pir_table[entry]; 383 for (pin = 0; pin < PCI_INTERRUPT_PIN_MAX; pin++) { 384 if ((link = pir->linkmap[pin].link) == 0) 385 /* No connection for this pin. */ 386 continue; 387 388 /* 389 * Multiple devices may be wired to the same 390 * interrupt; check to see if we've seen this 391 * one already. If not, allocate a new link 392 * map entry and stuff it in the map. 393 */ 394 if ((l = pciintr_link_lookup(link)) == NULL) 395 pciintr_link_alloc(pc, pir, pin); 396 else if (pir->linkmap[pin].bitmap != l->bitmap) { 397 /* 398 * violates PCI IRQ Routing Table Specification 399 */ 400 PCIBIOS_PRINTV(("pciintr_link_init: " 401 "bus %d device %d link 0x%02x: " 402 "bad irq bitmap 0x%04x, " 403 "should be 0x%04x\n", pir->bus, 404 PIR_DEVFUNC_DEVICE(pir->device), link, 405 pir->linkmap[pin].bitmap, l->bitmap)); 406 /* safer value. */ 407 l->bitmap &= pir->linkmap[pin].bitmap; 408 /* XXX - or, should ignore this entry? */ 409 } 410 } 411 } 412 413 return (0); 414 } 415 416 /* 417 * No compatible PCI ICU found. 418 * Hopes the BIOS already setup the ICU. 419 */ 420 static __inline int 421 pciintr_guess_irq(void) 422 { 423 struct pciintr_link_map *l; 424 int irq, guessed = 0; 425 426 /* 427 * Stage 1: If only one IRQ is available for the link, use it. 428 */ 429 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 430 l = SIMPLEQ_NEXT(l, list)) { 431 if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 432 continue; 433 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 434 l->irq = irq; 435 l->fixup_stage = 1; 436 if (pcibios_flags & PCIBIOS_INTRDEBUG) 437 printf("pciintr_guess_irq (stage 1): " 438 "guessing PIRQ 0x%02x to be IRQ %d\n", 439 l->clink, l->irq); 440 guessed = 1; 441 } 442 } 443 444 return (guessed ? 0 : -1); 445 } 446 447 static __inline int 448 pciintr_link_fixup(void) 449 { 450 struct pciintr_link_map *l; 451 u_int16_t pciirq = 0; 452 int irq; 453 454 /* 455 * First stage: Attempt to connect PIRQs which aren't 456 * yet connected. 457 */ 458 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 459 l = SIMPLEQ_NEXT(l, list)) { 460 if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 461 /* 462 * Interrupt is already connected. Don't do 463 * anything to it. 464 * In this case, l->fixup_stage == 0. 465 */ 466 pciirq |= 1 << l->irq; 467 if (pcibios_flags & PCIBIOS_INTRDEBUG) 468 printf("pciintr_link_fixup: PIRQ 0x%02x is " 469 "already connected to IRQ %d\n", 470 l->clink, l->irq); 471 continue; 472 } 473 /* 474 * Interrupt isn't connected. Attempt to assign it to an IRQ. 475 */ 476 if (pcibios_flags & PCIBIOS_INTRDEBUG) 477 printf("pciintr_link_fixup: PIRQ 0x%02x not connected", 478 l->clink); 479 480 /* 481 * Just do the easy case now; we'll defer the harder ones 482 * to Stage 2. 483 */ 484 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 485 l->irq = irq; 486 l->fixup_stage = 1; 487 pciirq |= 1 << irq; 488 if (pcibios_flags & PCIBIOS_INTRDEBUG) 489 printf(", assigning IRQ %d", l->irq); 490 } 491 if (pcibios_flags & PCIBIOS_INTRDEBUG) 492 printf("\n"); 493 } 494 495 /* 496 * Stage 2: Attempt to connect PIRQs which we didn't 497 * connect in Stage 1. 498 */ 499 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 500 l = SIMPLEQ_NEXT(l, list)) 501 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION && 502 (irq = ffs(l->bitmap & pciirq)) > 0) { 503 /* 504 * This IRQ is a valid PCI IRQ already 505 * connected to another PIRQ, and also an 506 * IRQ our PIRQ can use; connect it up! 507 */ 508 l->fixup_stage = 2; 509 l->irq = irq - 1; 510 if (pcibios_flags & PCIBIOS_INTRDEBUG) 511 printf("pciintr_link_fixup (stage 2): " 512 "assigning IRQ %d to PIRQ 0x%02x\n", 513 l->irq, l->clink); 514 } 515 516 #ifdef PCIBIOS_IRQS_HINT 517 /* 518 * Stage 3: The worst case. I need configuration hint that 519 * user supplied a mask for the PCI irqs 520 */ 521 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 522 l = SIMPLEQ_NEXT(l, list)) { 523 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION && 524 (irq = ffs(l->bitmap & pcibios_irqs_hint)) > 0) { 525 l->fixup_stage = 3; 526 l->irq = irq - 1; 527 if (pcibios_flags & PCIBIOS_INTRDEBUG) 528 printf("pciintr_link_fixup (stage 3): " 529 "assigning IRQ %d to PIRQ 0x%02x\n", 530 l->irq, l->clink); 531 } 532 } 533 #endif /* PCIBIOS_IRQS_HINT */ 534 535 if (pcibios_flags & PCIBIOS_INTRDEBUG) 536 printf("pciintr_link_fixup: piirq 0x%04x\n", pciirq); 537 538 return (0); 539 } 540 541 int 542 pci_intr_route_link(pci_chipset_tag_t pc, pci_intr_handle_t *ihp) 543 { 544 struct pciintr_link_map *l; 545 pcireg_t intr; 546 int irq, rv = 1; 547 char *p = NULL; 548 549 if (pcibios_flags & PCIBIOS_INTR_FIXUP) 550 return 1; 551 552 irq = ihp->line & APIC_INT_LINE_MASK; 553 if (irq != 0 && irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 554 pcibios_pir_header.exclusive_irq |= 1 << irq; 555 556 l = ihp->link; 557 if (!l || pciintr_icu_tag == NULL) 558 return (1); 559 560 if (l->fixup_stage == 0) { 561 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 562 /* Appropriate interrupt was not found. */ 563 if (pcibios_flags & PCIBIOS_INTRDEBUG) 564 printf("pci_intr_route_link: PIRQ 0x%02x: " 565 "no IRQ, try " 566 "\"option PCIBIOS_IRQS_HINT=0x%04x\"\n", 567 l->clink, 568 /* suggest irq 9/10/11, if possible */ 569 (l->bitmap & 0x0e00) ? (l->bitmap & 0x0e00) 570 : l->bitmap); 571 } else 572 p = " preserved BIOS setting"; 573 } else { 574 575 if (pciintr_icu_set_intr(pciintr_icu_tag, pciintr_icu_handle, 576 l->clink, l->irq) != 0 || 577 pciintr_icu_set_trigger(pciintr_icu_tag, pciintr_icu_handle, 578 l->irq, IST_LEVEL) != 0) { 579 p = " failed"; 580 rv = 0; 581 } else 582 p = ""; 583 } 584 if (p && pcibios_flags & PCIBIOS_INTRDEBUG) 585 printf("pci_intr_route_link: route PIRQ 0x%02x -> IRQ %d%s\n", 586 l->clink, l->irq, p); 587 588 if (!rv) 589 return (0); 590 591 /* 592 * IRQs 14 and 15 are reserved for PCI IDE interrupts; don't muck 593 * with them. 594 */ 595 if (irq == 14 || irq == 15) 596 return (1); 597 598 intr = pci_conf_read(pc, ihp->tag, PCI_INTERRUPT_REG); 599 if (irq != PCI_INTERRUPT_LINE(intr)) { 600 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 601 intr |= irq << PCI_INTERRUPT_LINE_SHIFT; 602 pci_conf_write(pc, ihp->tag, PCI_INTERRUPT_REG, intr); 603 } 604 605 return (1); 606 } 607 608 int 609 pci_intr_post_fixup(void) 610 { 611 struct pciintr_link_map *l; 612 int i, pciirq; 613 614 if (pcibios_flags & PCIBIOS_INTR_FIXUP) 615 return 1; 616 617 if (!pciintr_icu_handle) 618 return 0; 619 620 pciirq = pcibios_pir_header.exclusive_irq; 621 if (pcibios_flags & PCIBIOS_INTRDEBUG) 622 printf("pci_intr_post_fixup: PCI IRQs:"); 623 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); 624 l != NULL; l = SIMPLEQ_NEXT(l, list)) 625 if (l->fixup_stage == 0 && l->irq != 0 && 626 l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 627 if (pcibios_flags & PCIBIOS_INTRDEBUG) 628 printf(" %d", l->irq); 629 pciirq |= (1 << l->irq); 630 } 631 632 if (pcibios_flags & PCIBIOS_INTRDEBUG) 633 printf("; ISA IRQs:"); 634 for (i = 0; i < 16; i++) 635 if (!(pciirq & (1 << i))) { 636 if (pcibios_flags & PCIBIOS_INTRDEBUG) 637 printf(" %d", i); 638 pciintr_icu_set_trigger(pciintr_icu_tag, 639 pciintr_icu_handle, i, IST_EDGE); 640 } 641 642 if (pcibios_flags & PCIBIOS_INTRDEBUG) 643 printf("\n"); 644 645 return (0); 646 } 647 648 int 649 pci_intr_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, 650 pci_intr_handle_t *ihp) 651 { 652 struct pcibios_intr_routing *pir; 653 struct pciintr_link_map *l; 654 int irq, link, bus, device, function; 655 char *p = NULL; 656 657 if (pcibios_flags & PCIBIOS_INTR_FIXUP) 658 return 1; 659 660 irq = ihp->line & APIC_INT_LINE_MASK; 661 ihp->link = NULL; 662 pci_decompose_tag(pc, tag, &bus, &device, &function); 663 664 if ((pir = pciintr_pir_lookup(bus, device)) == NULL || 665 (link = pir->linkmap[ihp->pin - 1].link) == 0) { 666 PCIBIOS_PRINTV(("Interrupt not connected; no need to change.")); 667 return 1; 668 } 669 670 if ((l = pciintr_link_lookup(link)) == NULL) { 671 /* 672 * No link map entry. 673 * Probably pciintr_icu_getclink() or pciintr_icu_get_intr() 674 * has failed. 675 */ 676 if (pcibios_flags & PCIBIOS_INTRDEBUG) 677 printf("pci_intr_header_fixup: no entry for link " 678 "0x%02x (%d:%d:%d:%c)\n", 679 link, bus, device, function, '@' + ihp->pin); 680 return 1; 681 } 682 683 ihp->link = l; 684 if (irq == 14 || irq == 15) { 685 p = " WARNING: ignored"; 686 ihp->link = NULL; 687 } else if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 688 689 /* Appropriate interrupt was not found. */ 690 if (pciintr_icu_tag == NULL && irq != 0 && 691 irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 692 /* 693 * Do not print warning, 694 * if no compatible PCI ICU found, 695 * but the irq is already assigned by BIOS. 696 */ 697 p = ""; 698 else 699 p = " WARNING: missing"; 700 } else if (irq == 0 || irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 701 702 p = " fixed up"; 703 ihp->line = irq = l->irq; 704 705 } else if (pcibios_flags & PCIBIOS_FIXUP_FORCE) { 706 /* routed by BIOS, but inconsistent */ 707 /* believe PCI IRQ Routing table */ 708 p = " WARNING: overriding"; 709 ihp->line = irq = l->irq; 710 } else { 711 /* believe PCI Interrupt Configuration Register (default) */ 712 p = " WARNING: preserving"; 713 ihp->line = (l->irq = irq) | (l->clink & PCI_INT_VIA_ISA); 714 } 715 716 if (pcibios_flags & PCIBIOS_INTRDEBUG) { 717 pcireg_t id = pci_conf_read(pc, tag, PCI_ID_REG); 718 719 printf("\n%d:%d:%d %04x:%04x pin %c clink 0x%02x irq %d " 720 "stage %d %s irq %d\n", bus, device, function, 721 PCI_VENDOR(id), PCI_PRODUCT(id), '@' + ihp->pin, l->clink, 722 ((l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION)? 723 -1 : l->irq), l->fixup_stage, p, irq); 724 } 725 726 return (1); 727 } 728 729 int 730 pci_intr_fixup(struct pcibios_softc *sc, pci_chipset_tag_t pc, 731 bus_space_tag_t iot) 732 { 733 struct pcibios_pir_header *pirh = &pcibios_pir_header; 734 const struct pciintr_icu_table *piit = NULL; 735 pcitag_t icutag; 736 737 /* 738 * Attempt to initialize our PCI interrupt router. If 739 * the PIR Table is present in ROM, use the location 740 * specified by the PIR Table, and use the compat ID, 741 * if present. Otherwise, we have to look for the router 742 * ourselves (the PCI-ISA bridge). 743 * 744 * A number of buggy BIOS implementations leave the router 745 * entry as 000:00:0, which is typically not the correct 746 * device/function. If the router device address is set to 747 * this value, and the compatible router entry is undefined 748 * (zero is the correct value to indicate undefined), then we 749 * work on the basis it is most likely an error, and search 750 * the entire device-space of bus 0 (but obviously starting 751 * with 000:00:0, in case that really is the right one). 752 */ 753 if (pirh->signature != 0 && (pirh->router_bus != 0 || 754 pirh->router_devfunc != 0 || pirh->compat_router != 0)) { 755 756 icutag = pci_make_tag(pc, pirh->router_bus, 757 PIR_DEVFUNC_DEVICE(pirh->router_devfunc), 758 PIR_DEVFUNC_FUNCTION(pirh->router_devfunc)); 759 if (pirh->compat_router == 0 || 760 (piit = pciintr_icu_lookup(pirh->compat_router)) == NULL) { 761 /* 762 * No compat ID, or don't know the compat ID? Read 763 * it from the configuration header. 764 */ 765 pirh->compat_router = pci_conf_read(pc, icutag, 766 PCI_ID_REG); 767 } 768 if (piit == NULL) 769 piit = pciintr_icu_lookup(pirh->compat_router); 770 } else { 771 int device, maxdevs = pci_bus_maxdevs(pc, 0); 772 773 /* 774 * Search configuration space for a known interrupt 775 * router. 776 */ 777 for (device = 0; device < maxdevs; device++) { 778 const struct pci_quirkdata *qd; 779 int function, nfuncs; 780 pcireg_t icuid; 781 pcireg_t bhlcr; 782 783 icutag = pci_make_tag(pc, 0, device, 0); 784 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 785 786 /* Invalid vendor ID value? */ 787 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 788 continue; 789 /* XXX Not invalid, but we've done this ~forever. */ 790 if (PCI_VENDOR(icuid) == 0) 791 continue; 792 793 qd = pci_lookup_quirkdata(PCI_VENDOR(icuid), 794 PCI_PRODUCT(icuid)); 795 796 bhlcr = pci_conf_read(pc, icutag, PCI_BHLC_REG); 797 if (PCI_HDRTYPE_MULTIFN(bhlcr) || (qd != NULL && 798 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 799 nfuncs = 8; 800 else 801 nfuncs = 1; 802 803 for (function = 0; function < nfuncs; function++) { 804 icutag = pci_make_tag(pc, 0, device, function); 805 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 806 807 /* Invalid vendor ID value? */ 808 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 809 continue; 810 /* Not invalid, but we've done this ~forever. */ 811 if (PCI_VENDOR(icuid) == 0) 812 continue; 813 814 if ((piit = pciintr_icu_lookup(icuid))) { 815 pirh->compat_router = icuid; 816 pirh->router_bus = 0; 817 pirh->router_devfunc = 818 PIR_DEVFUNC_COMPOSE(device, 0); 819 break; 820 } 821 } 822 823 if (piit != NULL) 824 break; 825 } 826 } 827 828 if (piit == NULL) { 829 printf("%s: no compatible PCI ICU found", sc->sc_dev.dv_xname); 830 if (pirh->signature != 0 && pirh->compat_router != 0) 831 printf(": ICU vendor 0x%04x product 0x%04x", 832 PCI_VENDOR(pirh->compat_router), 833 PCI_PRODUCT(pirh->compat_router)); 834 printf("\n"); 835 if (!(pcibios_flags & PCIBIOS_INTR_GUESS)) { 836 if (pciintr_link_init(pc)) 837 return (-1); /* non-fatal */ 838 if (pciintr_guess_irq()) 839 return (-1); /* non-fatal */ 840 } 841 return (0); 842 } else { 843 char devinfo[256]; 844 845 printf("%s: PCI Interrupt Router at %03d:%02d:%01d", 846 sc->sc_dev.dv_xname, pirh->router_bus, 847 PIR_DEVFUNC_DEVICE(pirh->router_devfunc), 848 PIR_DEVFUNC_FUNCTION(pirh->router_devfunc)); 849 if (pirh->compat_router != 0) { 850 pci_devinfo(pirh->compat_router, 0, 0, devinfo, 851 sizeof devinfo); 852 printf(" (%s)", devinfo); 853 } 854 printf("\n"); 855 } 856 857 /* 858 * Initialize the PCI ICU. 859 */ 860 if ((*piit->piit_init)(pc, iot, icutag, &pciintr_icu_tag, 861 &pciintr_icu_handle) != 0) 862 return (-1); /* non-fatal */ 863 864 /* 865 * Initialize the PCI interrupt link map. 866 */ 867 if (pciintr_link_init(pc)) 868 return (-1); /* non-fatal */ 869 870 /* 871 * Fix up the link->IRQ mappings. 872 */ 873 if (pciintr_link_fixup() != 0) 874 return (-1); /* non-fatal */ 875 876 return (0); 877 } 878