1 /* $OpenBSD: pci_machdep.c,v 1.63 2011/06/08 22:57:59 kettenis Exp $ */ 2 /* $NetBSD: pci_machdep.c,v 1.28 1997/06/06 23:29:17 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1997 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * Copyright (c) 1994 Charles Hannum. All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Charles Hannum. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Machine-specific functions for PCI autoconfiguration. 66 * 67 * On PCs, there are two methods of generating PCI configuration cycles. 68 * We try to detect the appropriate mechanism for this machine and set 69 * up a few function pointers to access the correct method directly. 70 * 71 * The configuration method can be hard-coded in the config file by 72 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 73 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 74 */ 75 76 #include <sys/types.h> 77 #include <sys/param.h> 78 #include <sys/time.h> 79 #include <sys/systm.h> 80 #include <sys/errno.h> 81 #include <sys/device.h> 82 #include <sys/extent.h> 83 #include <sys/malloc.h> 84 85 #include <uvm/uvm_extern.h> 86 87 #include <machine/bus.h> 88 #include <machine/pio.h> 89 #include <machine/i8259.h> 90 #include <machine/biosvar.h> 91 92 #include "bios.h" 93 #if NBIOS > 0 94 extern bios_pciinfo_t *bios_pciinfo; 95 #endif 96 97 #include <dev/isa/isavar.h> 98 #include <dev/pci/pcivar.h> 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/ppbreg.h> 102 103 #include "ioapic.h" 104 105 #include <machine/i82093var.h> 106 #include <machine/i82489reg.h> 107 #include <machine/i82489var.h> 108 #if NIOAPIC > 0 109 #include <machine/mpbiosvar.h> 110 #endif 111 112 #include "pcibios.h" 113 #if NPCIBIOS > 0 114 #include <i386/pci/pcibiosvar.h> 115 #endif 116 117 int pci_mode = -1; 118 119 /* 120 * Memory Mapped Configuration space access. 121 * 122 * Since mapping the whole configuration space will cost us up to 123 * 256MB of kernel virtual memory, we use seperate mappings per bus. 124 * The mappings are created on-demand, such that we only use kernel 125 * virtual memory for busses that are actually present. 126 */ 127 bus_addr_t pci_mcfg_addr; 128 int pci_mcfg_min_bus, pci_mcfg_max_bus; 129 bus_space_tag_t pci_mcfgt = I386_BUS_SPACE_MEM; 130 bus_space_handle_t pci_mcfgh[256]; 131 void pci_mcfg_map_bus(int); 132 133 struct mutex pci_conf_lock = MUTEX_INITIALIZER(IPL_HIGH); 134 135 #define PCI_CONF_LOCK() \ 136 do { \ 137 mtx_enter(&pci_conf_lock); \ 138 } while (0) 139 140 #define PCI_CONF_UNLOCK() \ 141 do { \ 142 mtx_leave(&pci_conf_lock); \ 143 } while (0) 144 145 #define PCI_MODE1_ENABLE 0x80000000UL 146 #define PCI_MODE1_ADDRESS_REG 0x0cf8 147 #define PCI_MODE1_DATA_REG 0x0cfc 148 149 #define PCI_MODE2_ENABLE_REG 0x0cf8 150 #define PCI_MODE2_FORWARD_REG 0x0cfa 151 152 #define _m1tag(b, d, f) \ 153 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 154 #define _qe(bus, dev, fcn, vend, prod) \ 155 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 156 struct { 157 u_int32_t tag; 158 pcireg_t id; 159 } pcim1_quirk_tbl[] = { 160 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 161 /* XXX Triflex2 not tested */ 162 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 163 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 164 /* Triton needed for Connectix Virtual PC */ 165 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 166 /* Connectix Virtual PC 5 has a 440BX */ 167 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 168 {0, 0xffffffff} /* patchable */ 169 }; 170 #undef _m1tag 171 #undef _qe 172 173 /* 174 * PCI doesn't have any special needs; just use the generic versions 175 * of these functions. 176 */ 177 struct bus_dma_tag pci_bus_dma_tag = { 178 NULL, /* _cookie */ 179 _bus_dmamap_create, 180 _bus_dmamap_destroy, 181 _bus_dmamap_load, 182 _bus_dmamap_load_mbuf, 183 _bus_dmamap_load_uio, 184 _bus_dmamap_load_raw, 185 _bus_dmamap_unload, 186 _bus_dmamap_sync, 187 _bus_dmamem_alloc, 188 _bus_dmamem_free, 189 _bus_dmamem_map, 190 _bus_dmamem_unmap, 191 _bus_dmamem_mmap, 192 }; 193 194 void 195 pci_attach_hook(struct device *parent, struct device *self, 196 struct pcibus_attach_args *pba) 197 { 198 pci_chipset_tag_t pc = pba->pba_pc; 199 pcitag_t tag; 200 pcireg_t id, class; 201 202 #if NBIOS > 0 203 if (pba->pba_bus == 0) 204 printf(": configuration mode %d (%s)", 205 pci_mode, (bios_pciinfo?"bios":"no bios")); 206 #else 207 if (pba->pba_bus == 0) 208 printf(": configuration mode %d", pci_mode); 209 #endif 210 211 if (pba->pba_bus != 0) 212 return; 213 214 /* 215 * In order to decide whether the system supports MSI we look 216 * at the host bridge, which should be device 0 function 0 on 217 * bus 0. It is better to not enable MSI on systems that 218 * support it than the other way around, so be conservative 219 * here. So we don't enable MSI if we don't find a host 220 * bridge there. We also deliberately don't enable MSI on 221 * chipsets from low-end manifacturers like VIA and SiS. 222 */ 223 tag = pci_make_tag(pc, 0, 0, 0); 224 id = pci_conf_read(pc, tag, PCI_ID_REG); 225 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 226 227 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 228 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST) 229 return; 230 231 switch (PCI_VENDOR(id)) { 232 case PCI_VENDOR_INTEL: 233 /* 234 * For Intel platforms, MSI support was introduced 235 * with the new Pentium 4 processor interrupt delivery 236 * mechanism, so we blacklist all PCI chipsets that 237 * support Pentium III and earlier CPUs. 238 */ 239 switch (PCI_PRODUCT(id)) { 240 case PCI_PRODUCT_INTEL_PCMC: /* 82434LX/NX */ 241 case PCI_PRODUCT_INTEL_82437FX: 242 case PCI_PRODUCT_INTEL_82437MX: 243 case PCI_PRODUCT_INTEL_82437VX: 244 case PCI_PRODUCT_INTEL_82439HX: 245 case PCI_PRODUCT_INTEL_82439TX: 246 case PCI_PRODUCT_INTEL_82440BX: 247 case PCI_PRODUCT_INTEL_82440BX_AGP: 248 case PCI_PRODUCT_INTEL_82440MX_HB: 249 case PCI_PRODUCT_INTEL_82441FX: 250 case PCI_PRODUCT_INTEL_82443BX: 251 case PCI_PRODUCT_INTEL_82443BX_AGP: 252 case PCI_PRODUCT_INTEL_82443BX_NOAGP: 253 case PCI_PRODUCT_INTEL_82443GX: 254 case PCI_PRODUCT_INTEL_82443LX: 255 case PCI_PRODUCT_INTEL_82443LX_AGP: 256 case PCI_PRODUCT_INTEL_82810_HB: 257 case PCI_PRODUCT_INTEL_82810E_HB: 258 case PCI_PRODUCT_INTEL_82815_HB: 259 case PCI_PRODUCT_INTEL_82820_HB: 260 case PCI_PRODUCT_INTEL_82830M_HB: 261 case PCI_PRODUCT_INTEL_82840_HB: 262 break; 263 default: 264 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 265 break; 266 } 267 break; 268 case PCI_VENDOR_NVIDIA: 269 /* 270 * Since NVIDIA chipsets are completely undocumented, 271 * we have to make a guess here. We assume that all 272 * chipsets that support PCIe include support for MSI, 273 * since support for MSI is mandated by the PCIe 274 * standard. 275 */ 276 switch (PCI_PRODUCT(id)) { 277 case PCI_PRODUCT_NVIDIA_NFORCE_PCHB: 278 case PCI_PRODUCT_NVIDIA_NFORCE2_PCHB: 279 break; 280 default: 281 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 282 break; 283 } 284 break; 285 case PCI_VENDOR_AMD: 286 /* 287 * The AMD-750 and AMD-760 chipsets don't support MSI. 288 */ 289 switch (PCI_PRODUCT(id)) { 290 case PCI_PRODUCT_AMD_SC751_SC: 291 case PCI_PRODUCT_AMD_761_PCHB: 292 case PCI_PRODUCT_AMD_762_PCHB: 293 break; 294 default: 295 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 296 break; 297 } 298 break; 299 } 300 301 /* 302 * Don't enable MSI on a HyperTransport bus. In order to 303 * determine that bus 0 is a HyperTransport bus, we look at 304 * device 24 function 0, which is the HyperTransport 305 * host/primary interface integrated on most 64-bit AMD CPUs. 306 * If that device has a HyperTransport capability, bus 0 must 307 * be a HyperTransport bus and we disable MSI. 308 */ 309 tag = pci_make_tag(pc, 0, 24, 0); 310 if (pci_get_capability(pc, tag, PCI_CAP_HT, NULL, NULL)) 311 pba->pba_flags &= ~PCI_FLAGS_MSI_ENABLED; 312 } 313 314 int 315 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 316 { 317 318 /* 319 * Bus number is irrelevant. If Configuration Mechanism 2 is in 320 * use, can only have devices 0-15 on any bus. If Configuration 321 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 322 * range). 323 */ 324 if (pci_mode == 2) 325 return (16); 326 else 327 return (32); 328 } 329 330 pcitag_t 331 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 332 { 333 pcitag_t tag; 334 335 switch (pci_mode) { 336 case 1: 337 if (bus >= 256 || device >= 32 || function >= 8) 338 panic("pci_make_tag: bad request"); 339 340 tag.mode1 = PCI_MODE1_ENABLE | 341 (bus << 16) | (device << 11) | (function << 8); 342 break; 343 case 2: 344 if (bus >= 256 || device >= 16 || function >= 8) 345 panic("pci_make_tag: bad request"); 346 347 tag.mode2.port = 0xc000 | (device << 8); 348 tag.mode2.enable = 0xf0 | (function << 1); 349 tag.mode2.forward = bus; 350 break; 351 default: 352 panic("pci_make_tag: mode not configured"); 353 } 354 355 return tag; 356 } 357 358 void 359 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 360 { 361 switch (pci_mode) { 362 case 1: 363 if (bp != NULL) 364 *bp = (tag.mode1 >> 16) & 0xff; 365 if (dp != NULL) 366 *dp = (tag.mode1 >> 11) & 0x1f; 367 if (fp != NULL) 368 *fp = (tag.mode1 >> 8) & 0x7; 369 break; 370 case 2: 371 if (bp != NULL) 372 *bp = tag.mode2.forward & 0xff; 373 if (dp != NULL) 374 *dp = (tag.mode2.port >> 8) & 0xf; 375 if (fp != NULL) 376 *fp = (tag.mode2.enable >> 1) & 0x7; 377 break; 378 default: 379 panic("pci_decompose_tag: mode not configured"); 380 } 381 } 382 383 int 384 pci_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 385 { 386 int bus; 387 388 if (pci_mcfg_addr) { 389 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 390 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) 391 return PCIE_CONFIG_SPACE_SIZE; 392 } 393 394 return PCI_CONFIG_SPACE_SIZE; 395 } 396 397 void 398 pci_mcfg_map_bus(int bus) 399 { 400 if (pci_mcfgh[bus]) 401 return; 402 403 if (bus_space_map(pci_mcfgt, pci_mcfg_addr + (bus << 20), 1 << 20, 404 0, &pci_mcfgh[bus])) 405 panic("pci_conf_read: cannot map mcfg space"); 406 } 407 408 pcireg_t 409 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 410 { 411 pcireg_t data; 412 int bus; 413 414 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 415 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 416 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 417 pci_mcfg_map_bus(bus); 418 data = bus_space_read_4(pci_mcfgt, pci_mcfgh[bus], 419 (tag.mode1 & 0x000ff00) << 4 | reg); 420 return data; 421 } 422 } 423 424 PCI_CONF_LOCK(); 425 switch (pci_mode) { 426 case 1: 427 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 428 data = inl(PCI_MODE1_DATA_REG); 429 outl(PCI_MODE1_ADDRESS_REG, 0); 430 break; 431 case 2: 432 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 433 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 434 data = inl(tag.mode2.port | reg); 435 outb(PCI_MODE2_ENABLE_REG, 0); 436 break; 437 default: 438 panic("pci_conf_read: mode not configured"); 439 } 440 PCI_CONF_UNLOCK(); 441 442 return data; 443 } 444 445 void 446 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 447 { 448 int bus; 449 450 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 451 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 452 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 453 pci_mcfg_map_bus(bus); 454 bus_space_write_4(pci_mcfgt, pci_mcfgh[bus], 455 (tag.mode1 & 0x000ff00) << 4 | reg, data); 456 return; 457 } 458 } 459 460 PCI_CONF_LOCK(); 461 switch (pci_mode) { 462 case 1: 463 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 464 outl(PCI_MODE1_DATA_REG, data); 465 outl(PCI_MODE1_ADDRESS_REG, 0); 466 break; 467 case 2: 468 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 469 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 470 outl(tag.mode2.port | reg, data); 471 outb(PCI_MODE2_ENABLE_REG, 0); 472 break; 473 default: 474 panic("pci_conf_write: mode not configured"); 475 } 476 PCI_CONF_UNLOCK(); 477 } 478 479 int 480 pci_mode_detect(void) 481 { 482 483 #ifdef PCI_CONF_MODE 484 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 485 return (pci_mode = PCI_CONF_MODE); 486 #else 487 #error Invalid PCI configuration mode. 488 #endif 489 #else 490 u_int32_t sav, val; 491 int i; 492 pcireg_t idreg; 493 494 if (pci_mode != -1) 495 return (pci_mode); 496 497 #if NBIOS > 0 498 /* 499 * If we have PCI info passed from the BIOS, use the mode given there 500 * for all of this code. If not, pass on through to the previous tests 501 * to try and divine the correct mode. 502 */ 503 if (bios_pciinfo != NULL) { 504 if (bios_pciinfo->pci_chars & 0x2) 505 return (pci_mode = 2); 506 507 if (bios_pciinfo->pci_chars & 0x1) 508 return (pci_mode = 1); 509 510 /* We should never get here, but if we do, fall through... */ 511 } 512 #endif 513 514 /* 515 * We try to divine which configuration mode the host bridge wants. 516 * 517 * This should really be done using the PCI BIOS. If we get here, the 518 * PCI BIOS does not exist, or the boot blocks did not provide the 519 * information. 520 */ 521 522 sav = inl(PCI_MODE1_ADDRESS_REG); 523 524 pci_mode = 1; /* assume this for now */ 525 /* 526 * catch some known buggy implementations of mode 1 527 */ 528 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]); 529 i++) { 530 pcitag_t t; 531 532 if (!pcim1_quirk_tbl[i].tag) 533 break; 534 t.mode1 = pcim1_quirk_tbl[i].tag; 535 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 536 if (idreg == pcim1_quirk_tbl[i].id) { 537 #ifdef DEBUG 538 printf("known mode 1 PCI chipset (%08x)\n", 539 idreg); 540 #endif 541 return (pci_mode); 542 } 543 } 544 545 /* 546 * Strong check for standard compliant mode 1: 547 * 1. bit 31 ("enable") can be set 548 * 2. byte/word access does not affect register 549 */ 550 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 551 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 552 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 553 val = inl(PCI_MODE1_ADDRESS_REG); 554 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 555 #ifdef DEBUG 556 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 557 val); 558 #endif 559 goto not1; 560 } 561 outl(PCI_MODE1_ADDRESS_REG, 0); 562 val = inl(PCI_MODE1_ADDRESS_REG); 563 if ((val & 0x80fffffc) != 0) 564 goto not1; 565 return (pci_mode); 566 not1: 567 outl(PCI_MODE1_ADDRESS_REG, sav); 568 569 /* 570 * This mode 2 check is quite weak (and known to give false 571 * positives on some Compaq machines). 572 * However, this doesn't matter, because this is the 573 * last test, and simply no PCI devices will be found if 574 * this happens. 575 */ 576 outb(PCI_MODE2_ENABLE_REG, 0); 577 outb(PCI_MODE2_FORWARD_REG, 0); 578 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 579 inb(PCI_MODE2_FORWARD_REG) != 0) 580 goto not2; 581 return (pci_mode = 2); 582 not2: 583 return (pci_mode = 0); 584 #endif 585 } 586 587 int 588 pci_intr_map_msi(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 589 { 590 pci_chipset_tag_t pc = pa->pa_pc; 591 pcitag_t tag = pa->pa_tag; 592 593 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL || 594 pci_get_capability(pc, tag, PCI_CAP_MSI, NULL, NULL) == 0) 595 return 1; 596 597 ihp->tag = tag; 598 ihp->line = APIC_INT_VIA_MSG; 599 ihp->pin = 0; 600 return 0; 601 } 602 603 int 604 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 605 { 606 int pin = pa->pa_rawintrpin; 607 int line = pa->pa_intrline; 608 #if NIOAPIC > 0 609 struct mp_intr_map *mip; 610 int bus, dev, func; 611 #endif 612 613 if (pin == 0) { 614 /* No IRQ used. */ 615 goto bad; 616 } 617 618 if (pin > PCI_INTERRUPT_PIN_MAX) { 619 printf("pci_intr_map: bad interrupt pin %d\n", pin); 620 goto bad; 621 } 622 623 ihp->tag = pa->pa_tag; 624 ihp->line = line; 625 ihp->pin = pin; 626 627 #if NIOAPIC > 0 628 pci_decompose_tag (pa->pa_pc, pa->pa_tag, &bus, &dev, &func); 629 630 if (!(ihp->line & PCI_INT_VIA_ISA) && mp_busses != NULL) { 631 /* 632 * Assumes 1:1 mapping between PCI bus numbers and 633 * the numbers given by the MP bios. 634 * XXX Is this a valid assumption? 635 */ 636 int mpspec_pin = (dev<<2)|(pin-1); 637 638 for (mip = mp_busses[bus].mb_intrs; mip != NULL; mip=mip->next) { 639 if (mip->bus_pin == mpspec_pin) { 640 ihp->line = mip->ioapic_ih | line; 641 return 0; 642 } 643 } 644 645 if (pa->pa_bridgetag) { 646 int swizpin = PPB_INTERRUPT_SWIZZLE(pin, dev); 647 if (pa->pa_bridgeih[swizpin - 1].line != -1) { 648 ihp->line = pa->pa_bridgeih[swizpin - 1].line; 649 ihp->line |= line; 650 return 0; 651 } 652 } 653 /* 654 * No explicit PCI mapping found. This is not fatal, 655 * we'll try the ISA (or possibly EISA) mappings next. 656 */ 657 } 658 #endif 659 660 #if NPCIBIOS > 0 661 pci_intr_header_fixup(pa->pa_pc, pa->pa_tag, ihp); 662 line = ihp->line & APIC_INT_LINE_MASK; 663 #endif 664 665 /* 666 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 667 * `unknown' or `no connection' on a PC. We assume that a device with 668 * `no connection' either doesn't have an interrupt (in which case the 669 * pin number should be 0, and would have been noticed above), or 670 * wasn't configured by the BIOS (in which case we punt, since there's 671 * no real way we can know how the interrupt lines are mapped in the 672 * hardware). 673 * 674 * XXX 675 * Since IRQ 0 is only used by the clock, and we can't actually be sure 676 * that the BIOS did its job, we also recognize that as meaning that 677 * the BIOS has not configured the device. 678 */ 679 if (line == 0 || line == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 680 goto bad; 681 682 if (line >= ICU_LEN) { 683 printf("pci_intr_map: bad interrupt line %d\n", line); 684 goto bad; 685 } 686 if (line == 2) { 687 printf("pci_intr_map: changed line 2 to line 9\n"); 688 line = 9; 689 } 690 691 #if NIOAPIC > 0 692 if (!(ihp->line & PCI_INT_VIA_ISA) && mp_busses != NULL) { 693 if (mip == NULL && mp_isa_bus) { 694 for (mip = mp_isa_bus->mb_intrs; mip != NULL; 695 mip = mip->next) { 696 if (mip->bus_pin == line) { 697 ihp->line = mip->ioapic_ih | line; 698 return 0; 699 } 700 } 701 } 702 if (mip == NULL && mp_eisa_bus) { 703 for (mip = mp_eisa_bus->mb_intrs; mip != NULL; 704 mip = mip->next) { 705 if (mip->bus_pin == line) { 706 ihp->line = mip->ioapic_ih | line; 707 return 0; 708 } 709 } 710 } 711 if (mip == NULL) { 712 printf("pci_intr_map: " 713 "bus %d dev %d func %d pin %d; line %d\n", 714 bus, dev, func, pin, line); 715 printf("pci_intr_map: no MP mapping found\n"); 716 } 717 } 718 #endif 719 720 return 0; 721 722 bad: 723 ihp->line = -1; 724 return 1; 725 } 726 727 const char * 728 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 729 { 730 static char irqstr[64]; 731 int line = ih.line & APIC_INT_LINE_MASK; 732 733 if (ih.line & APIC_INT_VIA_MSG) 734 return ("msi"); 735 736 #if NIOAPIC > 0 737 if (ih.line & APIC_INT_VIA_APIC) { 738 snprintf(irqstr, sizeof irqstr, "apic %d int %d", 739 APIC_IRQ_APIC(ih.line), APIC_IRQ_PIN(ih.line)); 740 return (irqstr); 741 } 742 #endif 743 744 if (line == 0 || line >= ICU_LEN || line == 2) 745 panic("pci_intr_string: bogus handle 0x%x", line); 746 747 snprintf(irqstr, sizeof irqstr, "irq %d", line); 748 return (irqstr); 749 } 750 751 #include "acpiprt.h" 752 #if NACPIPRT > 0 753 void acpiprt_route_interrupt(int bus, int dev, int pin); 754 #endif 755 756 extern struct intrhand *apic_intrhand[256]; 757 extern int apic_maxlevel[256]; 758 759 void * 760 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 761 int (*func)(void *), void *arg, const char *what) 762 { 763 void *ret; 764 int bus, dev; 765 int l = ih.line & APIC_INT_LINE_MASK; 766 pcitag_t tag = ih.tag; 767 int irq = ih.line; 768 769 if (ih.line & APIC_INT_VIA_MSG) { 770 struct intrhand *ih; 771 pcireg_t reg; 772 int off, vec; 773 774 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 775 panic("%s: no msi capability", __func__); 776 777 vec = idt_vec_alloc(level, level + 15); 778 if (vec == 0) 779 return (NULL); 780 781 ih = malloc(sizeof(*ih), M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 782 if (ih == NULL) 783 panic("%s: can't malloc handler info", __func__); 784 785 ih->ih_fun = func; 786 ih->ih_arg = arg; 787 ih->ih_next = NULL; 788 ih->ih_level = level; 789 ih->ih_irq = irq; 790 ih->ih_pin = tag.mode1; 791 ih->ih_vec = vec; 792 evcount_attach(&ih->ih_count, what, &ih->ih_vec); 793 794 apic_maxlevel[vec] = level; 795 apic_intrhand[vec] = ih; 796 idt_vec_set(vec, apichandler[vec & 0xf]); 797 798 if (reg & PCI_MSI_MC_C64) { 799 pci_conf_write(pc, tag, off + PCI_MSI_MA, 0xfee00000); 800 pci_conf_write(pc, tag, off + PCI_MSI_MAU32, 0); 801 pci_conf_write(pc, tag, off + PCI_MSI_MD64, vec); 802 } else { 803 pci_conf_write(pc, tag, off + PCI_MSI_MA, 0xfee00000); 804 pci_conf_write(pc, tag, off + PCI_MSI_MD32, vec); 805 } 806 pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE); 807 return (ih); 808 } 809 810 pci_decompose_tag(pc, ih.tag, &bus, &dev, NULL); 811 #if NACPIPRT > 0 812 acpiprt_route_interrupt(bus, dev, ih.pin); 813 #endif 814 815 #if NIOAPIC > 0 816 if (l != -1 && ih.line & APIC_INT_VIA_APIC) 817 return (apic_intr_establish(ih.line, IST_LEVEL, level, func, 818 arg, what)); 819 #endif 820 if (l == 0 || l >= ICU_LEN || l == 2) 821 panic("pci_intr_establish: bogus handle 0x%x", l); 822 823 ret = isa_intr_establish(NULL, l, IST_LEVEL, level, func, arg, what); 824 #if NPCIBIOS > 0 825 if (ret) 826 pci_intr_route_link(pc, &ih); 827 #endif 828 return (ret); 829 } 830 831 void 832 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 833 { 834 struct intrhand *ih = cookie; 835 836 if (ih->ih_irq & APIC_INT_VIA_MSG) { 837 pcitag_t tag = { .mode1 = ih->ih_pin }; 838 pcireg_t reg; 839 int off; 840 841 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 842 panic("%s: no msi capability", __func__); 843 844 pci_conf_write(pc, tag, off, reg &= ~PCI_MSI_MC_MSIE); 845 846 apic_maxlevel[ih->ih_vec] = 0; 847 apic_intrhand[ih->ih_vec] = NULL; 848 idt_vec_free(ih->ih_vec); 849 850 evcount_detach(&ih->ih_count); 851 free(ih, M_DEVBUF); 852 return; 853 } 854 855 /* XXX oh, unroute the pci int link? */ 856 isa_intr_disestablish(NULL, cookie); 857 } 858 859 struct extent *pciio_ex; 860 struct extent *pcimem_ex; 861 862 void 863 pci_init_extents(void) 864 { 865 bios_memmap_t *bmp; 866 u_int64_t size; 867 868 if (pciio_ex == NULL) { 869 /* 870 * We only have 64K of addressable I/O space. 871 * However, since BARs may contain garbage, we cover 872 * the full 32-bit address space defined by PCI of 873 * which we only make the first 64K available. 874 */ 875 pciio_ex = extent_create("pciio", 0, 0xffffffff, M_DEVBUF, 876 NULL, 0, EX_NOWAIT | EX_FILLED); 877 if (pciio_ex == NULL) 878 return; 879 extent_free(pciio_ex, 0, 0x10000, M_NOWAIT); 880 } 881 882 if (pcimem_ex == NULL) { 883 pcimem_ex = extent_create("pcimem", 0, 0xffffffff, M_DEVBUF, 884 NULL, 0, EX_NOWAIT); 885 if (pcimem_ex == NULL) 886 return; 887 888 for (bmp = bios_memmap; bmp->type != BIOS_MAP_END; bmp++) { 889 /* 890 * Ignore address space beyond 4G. 891 */ 892 if (bmp->addr >= 0x100000000ULL) 893 continue; 894 size = bmp->size; 895 if (bmp->addr + size >= 0x100000000ULL) 896 size = 0x100000000ULL - bmp->addr; 897 898 /* Ignore zero-sized regions. */ 899 if (size == 0) 900 continue; 901 902 if (extent_alloc_region(pcimem_ex, bmp->addr, size, 903 EX_NOWAIT)) 904 printf("memory map conflict 0x%llx/0x%llx\n", 905 bmp->addr, bmp->size); 906 } 907 908 /* Take out the video buffer area and BIOS areas. */ 909 extent_alloc_region(pcimem_ex, IOM_BEGIN, IOM_SIZE, 910 EX_CONFLICTOK | EX_NOWAIT); 911 } 912 } 913 914 #include "acpi.h" 915 #if NACPI > 0 916 void acpi_pci_match(struct device *, struct pci_attach_args *); 917 #endif 918 919 void 920 pci_dev_postattach(struct device *dev, struct pci_attach_args *pa) 921 { 922 #if NACPI > 0 923 acpi_pci_match(dev, pa); 924 #endif 925 } 926