1 /* $OpenBSD: pci_machdep.c,v 1.87 2021/03/11 11:16:57 jsg Exp $ */ 2 /* $NetBSD: pci_machdep.c,v 1.28 1997/06/06 23:29:17 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1997 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * Copyright (c) 1994 Charles Hannum. All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Charles Hannum. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Machine-specific functions for PCI autoconfiguration. 66 * 67 * On PCs, there are two methods of generating PCI configuration cycles. 68 * We try to detect the appropriate mechanism for this machine and set 69 * up a few function pointers to access the correct method directly. 70 * 71 * The configuration method can be hard-coded in the config file by 72 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 73 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 74 */ 75 76 #include <sys/param.h> 77 #include <sys/time.h> 78 #include <sys/systm.h> 79 #include <sys/errno.h> 80 #include <sys/device.h> 81 #include <sys/extent.h> 82 #include <sys/malloc.h> 83 84 #include <uvm/uvm_extern.h> 85 86 #include <machine/bus.h> 87 #include <machine/pio.h> 88 #include <machine/i8259.h> 89 #include <machine/biosvar.h> 90 91 #include "bios.h" 92 #if NBIOS > 0 93 extern bios_pciinfo_t *bios_pciinfo; 94 #endif 95 96 #include <dev/isa/isavar.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pcidevs.h> 100 #include <dev/pci/ppbreg.h> 101 102 #include "ioapic.h" 103 104 #include <machine/i82093var.h> 105 #include <machine/i82489reg.h> 106 #include <machine/i82489var.h> 107 #if NIOAPIC > 0 108 #include <machine/mpbiosvar.h> 109 #endif 110 111 #include "pcibios.h" 112 #if NPCIBIOS > 0 113 #include <i386/pci/pcibiosvar.h> 114 #endif 115 116 int pci_mode = -1; 117 118 /* 119 * Memory Mapped Configuration space access. 120 * 121 * Since mapping the whole configuration space will cost us up to 122 * 256MB of kernel virtual memory, we use separate mappings per bus. 123 * The mappings are created on-demand, such that we only use kernel 124 * virtual memory for busses that are actually present. 125 */ 126 bus_addr_t pci_mcfg_addr; 127 int pci_mcfg_min_bus, pci_mcfg_max_bus; 128 bus_space_tag_t pci_mcfgt = I386_BUS_SPACE_MEM; 129 bus_space_handle_t pci_mcfgh[256]; 130 void pci_mcfg_map_bus(int); 131 132 struct mutex pci_conf_lock = MUTEX_INITIALIZER(IPL_HIGH); 133 134 #define PCI_CONF_LOCK() \ 135 do { \ 136 mtx_enter(&pci_conf_lock); \ 137 } while (0) 138 139 #define PCI_CONF_UNLOCK() \ 140 do { \ 141 mtx_leave(&pci_conf_lock); \ 142 } while (0) 143 144 #define PCI_MODE1_ENABLE 0x80000000UL 145 #define PCI_MODE1_ADDRESS_REG 0x0cf8 146 #define PCI_MODE1_DATA_REG 0x0cfc 147 148 #define PCI_MODE2_ENABLE_REG 0x0cf8 149 #define PCI_MODE2_FORWARD_REG 0x0cfa 150 151 #define _m1tag(b, d, f) \ 152 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 153 #define _qe(bus, dev, fcn, vend, prod) \ 154 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 155 struct { 156 u_int32_t tag; 157 pcireg_t id; 158 } pcim1_quirk_tbl[] = { 159 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 160 /* XXX Triflex2 not tested */ 161 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 162 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 163 /* Triton needed for Connectix Virtual PC */ 164 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 165 /* Connectix Virtual PC 5 has a 440BX */ 166 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 167 {0, 0xffffffff} /* patchable */ 168 }; 169 #undef _m1tag 170 #undef _qe 171 172 /* 173 * PCI doesn't have any special needs; just use the generic versions 174 * of these functions. 175 */ 176 struct bus_dma_tag pci_bus_dma_tag = { 177 NULL, /* _cookie */ 178 _bus_dmamap_create, 179 _bus_dmamap_destroy, 180 _bus_dmamap_load, 181 _bus_dmamap_load_mbuf, 182 _bus_dmamap_load_uio, 183 _bus_dmamap_load_raw, 184 _bus_dmamap_unload, 185 _bus_dmamap_sync, 186 _bus_dmamem_alloc, 187 _bus_dmamem_alloc_range, 188 _bus_dmamem_free, 189 _bus_dmamem_map, 190 _bus_dmamem_unmap, 191 _bus_dmamem_mmap, 192 }; 193 194 void 195 pci_mcfg_init(bus_space_tag_t iot, bus_addr_t addr, int segment, 196 int min_bus, int max_bus) 197 { 198 if (segment == 0) { 199 pci_mcfgt = iot; 200 pci_mcfg_addr = addr; 201 pci_mcfg_min_bus = min_bus; 202 pci_mcfg_max_bus = max_bus; 203 } 204 } 205 206 pci_chipset_tag_t 207 pci_lookup_segment(int segment) 208 { 209 KASSERT(segment == 0); 210 return NULL; 211 } 212 213 void 214 pci_attach_hook(struct device *parent, struct device *self, 215 struct pcibus_attach_args *pba) 216 { 217 pci_chipset_tag_t pc = pba->pba_pc; 218 pcitag_t tag; 219 pcireg_t id, class; 220 221 #if NBIOS > 0 222 if (pba->pba_bus == 0) 223 printf(": configuration mode %d (%s)", 224 pci_mode, (bios_pciinfo?"bios":"no bios")); 225 #else 226 if (pba->pba_bus == 0) 227 printf(": configuration mode %d", pci_mode); 228 #endif 229 230 if (pba->pba_bus != 0) 231 return; 232 233 /* 234 * Machines that use the non-standard method of generating PCI 235 * configuration cycles are way too old to support MSI. 236 */ 237 if (pci_mode == 2) 238 return; 239 240 /* 241 * In order to decide whether the system supports MSI we look 242 * at the host bridge, which should be device 0 function 0 on 243 * bus 0. It is better to not enable MSI on systems that 244 * support it than the other way around, so be conservative 245 * here. So we don't enable MSI if we don't find a host 246 * bridge there. We also deliberately don't enable MSI on 247 * chipsets from low-end manufacturers like VIA and SiS. 248 */ 249 tag = pci_make_tag(pc, 0, 0, 0); 250 id = pci_conf_read(pc, tag, PCI_ID_REG); 251 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 252 253 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 254 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST) 255 return; 256 257 switch (PCI_VENDOR(id)) { 258 case PCI_VENDOR_INTEL: 259 /* 260 * For Intel platforms, MSI support was introduced 261 * with the new Pentium 4 processor interrupt delivery 262 * mechanism, so we blacklist all PCI chipsets that 263 * support Pentium III and earlier CPUs. 264 */ 265 switch (PCI_PRODUCT(id)) { 266 case PCI_PRODUCT_INTEL_PCMC: /* 82434LX/NX */ 267 case PCI_PRODUCT_INTEL_82437FX: 268 case PCI_PRODUCT_INTEL_82437MX: 269 case PCI_PRODUCT_INTEL_82437VX: 270 case PCI_PRODUCT_INTEL_82439HX: 271 case PCI_PRODUCT_INTEL_82439TX: 272 case PCI_PRODUCT_INTEL_82440BX: 273 case PCI_PRODUCT_INTEL_82440BX_AGP: 274 case PCI_PRODUCT_INTEL_82440MX_HB: 275 case PCI_PRODUCT_INTEL_82441FX: 276 case PCI_PRODUCT_INTEL_82443BX: 277 case PCI_PRODUCT_INTEL_82443BX_AGP: 278 case PCI_PRODUCT_INTEL_82443BX_NOAGP: 279 case PCI_PRODUCT_INTEL_82443GX: 280 case PCI_PRODUCT_INTEL_82443LX: 281 case PCI_PRODUCT_INTEL_82443LX_AGP: 282 case PCI_PRODUCT_INTEL_82810_HB: 283 case PCI_PRODUCT_INTEL_82810E_HB: 284 case PCI_PRODUCT_INTEL_82815_HB: 285 case PCI_PRODUCT_INTEL_82820_HB: 286 case PCI_PRODUCT_INTEL_82830M_HB: 287 case PCI_PRODUCT_INTEL_82840_HB: 288 break; 289 default: 290 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 291 break; 292 } 293 break; 294 case PCI_VENDOR_NVIDIA: 295 /* 296 * Since NVIDIA chipsets are completely undocumented, 297 * we have to make a guess here. We assume that all 298 * chipsets that support PCIe include support for MSI, 299 * since support for MSI is mandated by the PCIe 300 * standard. 301 */ 302 switch (PCI_PRODUCT(id)) { 303 case PCI_PRODUCT_NVIDIA_NFORCE_PCHB: 304 case PCI_PRODUCT_NVIDIA_NFORCE2_PCHB: 305 break; 306 default: 307 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 308 break; 309 } 310 break; 311 case PCI_VENDOR_AMD: 312 /* 313 * The AMD-750 and AMD-760 chipsets don't support MSI. 314 */ 315 switch (PCI_PRODUCT(id)) { 316 case PCI_PRODUCT_AMD_SC751_SC: 317 case PCI_PRODUCT_AMD_761_PCHB: 318 case PCI_PRODUCT_AMD_762_PCHB: 319 break; 320 default: 321 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 322 break; 323 } 324 break; 325 } 326 327 /* 328 * Don't enable MSI on a HyperTransport bus. In order to 329 * determine that bus 0 is a HyperTransport bus, we look at 330 * device 24 function 0, which is the HyperTransport 331 * host/primary interface integrated on most 64-bit AMD CPUs. 332 * If that device has a HyperTransport capability, bus 0 must 333 * be a HyperTransport bus and we disable MSI. 334 */ 335 tag = pci_make_tag(pc, 0, 24, 0); 336 if (pci_get_capability(pc, tag, PCI_CAP_HT, NULL, NULL)) 337 pba->pba_flags &= ~PCI_FLAGS_MSI_ENABLED; 338 } 339 340 int 341 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 342 { 343 344 /* 345 * Bus number is irrelevant. If Configuration Mechanism 2 is in 346 * use, can only have devices 0-15 on any bus. If Configuration 347 * Mechanism 1 is in use, can have devices 0-31 (i.e. the `normal' 348 * range). 349 */ 350 if (pci_mode == 2) 351 return (16); 352 else 353 return (32); 354 } 355 356 pcitag_t 357 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 358 { 359 pcitag_t tag; 360 361 switch (pci_mode) { 362 case 1: 363 if (bus >= 256 || device >= 32 || function >= 8) 364 panic("pci_make_tag: bad request"); 365 366 tag.mode1 = PCI_MODE1_ENABLE | 367 (bus << 16) | (device << 11) | (function << 8); 368 break; 369 case 2: 370 if (bus >= 256 || device >= 16 || function >= 8) 371 panic("pci_make_tag: bad request"); 372 373 tag.mode2.port = 0xc000 | (device << 8); 374 tag.mode2.enable = 0xf0 | (function << 1); 375 tag.mode2.forward = bus; 376 break; 377 default: 378 panic("pci_make_tag: mode not configured"); 379 } 380 381 return tag; 382 } 383 384 void 385 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 386 { 387 switch (pci_mode) { 388 case 1: 389 if (bp != NULL) 390 *bp = (tag.mode1 >> 16) & 0xff; 391 if (dp != NULL) 392 *dp = (tag.mode1 >> 11) & 0x1f; 393 if (fp != NULL) 394 *fp = (tag.mode1 >> 8) & 0x7; 395 break; 396 case 2: 397 if (bp != NULL) 398 *bp = tag.mode2.forward & 0xff; 399 if (dp != NULL) 400 *dp = (tag.mode2.port >> 8) & 0xf; 401 if (fp != NULL) 402 *fp = (tag.mode2.enable >> 1) & 0x7; 403 break; 404 default: 405 panic("pci_decompose_tag: mode not configured"); 406 } 407 } 408 409 int 410 pci_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 411 { 412 int bus; 413 414 if (pci_mcfg_addr) { 415 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 416 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) 417 return PCIE_CONFIG_SPACE_SIZE; 418 } 419 420 return PCI_CONFIG_SPACE_SIZE; 421 } 422 423 void 424 pci_mcfg_map_bus(int bus) 425 { 426 if (pci_mcfgh[bus]) 427 return; 428 429 if (bus_space_map(pci_mcfgt, pci_mcfg_addr + (bus << 20), 1 << 20, 430 0, &pci_mcfgh[bus])) 431 panic("pci_conf_read: cannot map mcfg space"); 432 } 433 434 pcireg_t 435 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 436 { 437 pcireg_t data; 438 int bus; 439 440 KASSERT((reg & 0x3) == 0); 441 442 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 443 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 444 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 445 pci_mcfg_map_bus(bus); 446 data = bus_space_read_4(pci_mcfgt, pci_mcfgh[bus], 447 (tag.mode1 & 0x000ff00) << 4 | reg); 448 return data; 449 } 450 } 451 452 PCI_CONF_LOCK(); 453 switch (pci_mode) { 454 case 1: 455 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 456 data = inl(PCI_MODE1_DATA_REG); 457 outl(PCI_MODE1_ADDRESS_REG, 0); 458 break; 459 case 2: 460 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 461 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 462 data = inl(tag.mode2.port | reg); 463 outb(PCI_MODE2_ENABLE_REG, 0); 464 break; 465 default: 466 panic("pci_conf_read: mode not configured"); 467 } 468 PCI_CONF_UNLOCK(); 469 470 return data; 471 } 472 473 void 474 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 475 { 476 int bus; 477 478 KASSERT((reg & 0x3) == 0); 479 480 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 481 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 482 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 483 pci_mcfg_map_bus(bus); 484 bus_space_write_4(pci_mcfgt, pci_mcfgh[bus], 485 (tag.mode1 & 0x000ff00) << 4 | reg, data); 486 return; 487 } 488 } 489 490 PCI_CONF_LOCK(); 491 switch (pci_mode) { 492 case 1: 493 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 494 outl(PCI_MODE1_DATA_REG, data); 495 outl(PCI_MODE1_ADDRESS_REG, 0); 496 break; 497 case 2: 498 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 499 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 500 outl(tag.mode2.port | reg, data); 501 outb(PCI_MODE2_ENABLE_REG, 0); 502 break; 503 default: 504 panic("pci_conf_write: mode not configured"); 505 } 506 PCI_CONF_UNLOCK(); 507 } 508 509 int 510 pci_mode_detect(void) 511 { 512 513 #ifdef PCI_CONF_MODE 514 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 515 return (pci_mode = PCI_CONF_MODE); 516 #else 517 #error Invalid PCI configuration mode. 518 #endif 519 #else 520 u_int32_t sav, val; 521 int i; 522 pcireg_t idreg; 523 524 if (pci_mode != -1) 525 return (pci_mode); 526 527 #if NBIOS > 0 528 /* 529 * If we have PCI info passed from the BIOS, use the mode given there 530 * for all of this code. If not, pass on through to the previous tests 531 * to try and divine the correct mode. 532 */ 533 if (bios_pciinfo != NULL) { 534 if (bios_pciinfo->pci_chars & 0x2) 535 return (pci_mode = 2); 536 537 if (bios_pciinfo->pci_chars & 0x1) 538 return (pci_mode = 1); 539 540 /* We should never get here, but if we do, fall through... */ 541 } 542 #endif 543 544 /* 545 * We try to divine which configuration mode the host bridge wants. 546 * 547 * This should really be done using the PCI BIOS. If we get here, the 548 * PCI BIOS does not exist, or the boot blocks did not provide the 549 * information. 550 */ 551 552 sav = inl(PCI_MODE1_ADDRESS_REG); 553 554 pci_mode = 1; /* assume this for now */ 555 /* 556 * catch some known buggy implementations of mode 1 557 */ 558 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]); 559 i++) { 560 pcitag_t t; 561 562 if (!pcim1_quirk_tbl[i].tag) 563 break; 564 t.mode1 = pcim1_quirk_tbl[i].tag; 565 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 566 if (idreg == pcim1_quirk_tbl[i].id) { 567 #ifdef DEBUG 568 printf("known mode 1 PCI chipset (%08x)\n", 569 idreg); 570 #endif 571 return (pci_mode); 572 } 573 } 574 575 /* 576 * Strong check for standard compliant mode 1: 577 * 1. bit 31 ("enable") can be set 578 * 2. byte/word access does not affect register 579 */ 580 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 581 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 582 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 583 val = inl(PCI_MODE1_ADDRESS_REG); 584 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 585 #ifdef DEBUG 586 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 587 val); 588 #endif 589 goto not1; 590 } 591 outl(PCI_MODE1_ADDRESS_REG, 0); 592 val = inl(PCI_MODE1_ADDRESS_REG); 593 if ((val & 0x80fffffc) != 0) 594 goto not1; 595 return (pci_mode); 596 not1: 597 outl(PCI_MODE1_ADDRESS_REG, sav); 598 599 /* 600 * This mode 2 check is quite weak (and known to give false 601 * positives on some Compaq machines). 602 * However, this doesn't matter, because this is the 603 * last test, and simply no PCI devices will be found if 604 * this happens. 605 */ 606 outb(PCI_MODE2_ENABLE_REG, 0); 607 outb(PCI_MODE2_FORWARD_REG, 0); 608 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 609 inb(PCI_MODE2_FORWARD_REG) != 0) 610 goto not2; 611 return (pci_mode = 2); 612 not2: 613 return (pci_mode = 0); 614 #endif 615 } 616 617 int 618 pci_intr_map_msi(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 619 { 620 pci_chipset_tag_t pc = pa->pa_pc; 621 pcitag_t tag = pa->pa_tag; 622 623 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL || 624 pci_get_capability(pc, tag, PCI_CAP_MSI, NULL, NULL) == 0) 625 return 1; 626 627 ihp->tag = tag; 628 ihp->line = APIC_INT_VIA_MSG; 629 ihp->pin = 0; 630 return 0; 631 } 632 633 int 634 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 635 { 636 int pin = pa->pa_rawintrpin; 637 int line = pa->pa_intrline; 638 #if NIOAPIC > 0 639 struct mp_intr_map *mip; 640 int bus, dev, func; 641 #endif 642 643 if (pin == 0) { 644 /* No IRQ used. */ 645 goto bad; 646 } 647 648 if (pin > PCI_INTERRUPT_PIN_MAX) { 649 printf("pci_intr_map: bad interrupt pin %d\n", pin); 650 goto bad; 651 } 652 653 ihp->tag = pa->pa_tag; 654 ihp->line = line; 655 ihp->pin = pin; 656 657 #if NIOAPIC > 0 658 pci_decompose_tag (pa->pa_pc, pa->pa_tag, &bus, &dev, &func); 659 660 if (!(ihp->line & PCI_INT_VIA_ISA) && mp_busses != NULL) { 661 int mpspec_pin = (dev << 2) | (pin - 1); 662 663 if (bus < mp_nbusses) { 664 for (mip = mp_busses[bus].mb_intrs; 665 mip != NULL; mip = mip->next) { 666 if (&mp_busses[bus] == mp_isa_bus || 667 &mp_busses[bus] == mp_eisa_bus) 668 continue; 669 if (mip->bus_pin == mpspec_pin) { 670 ihp->line = mip->ioapic_ih | line; 671 return 0; 672 } 673 } 674 } 675 676 if (pa->pa_bridgetag) { 677 int swizpin = PPB_INTERRUPT_SWIZZLE(pin, dev); 678 if (pa->pa_bridgeih[swizpin - 1].line != -1) { 679 ihp->line = pa->pa_bridgeih[swizpin - 1].line; 680 ihp->line |= line; 681 return 0; 682 } 683 } 684 /* 685 * No explicit PCI mapping found. This is not fatal, 686 * we'll try the ISA (or possibly EISA) mappings next. 687 */ 688 } 689 #endif 690 691 #if NPCIBIOS > 0 692 pci_intr_header_fixup(pa->pa_pc, pa->pa_tag, ihp); 693 line = ihp->line & APIC_INT_LINE_MASK; 694 #endif 695 696 /* 697 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 698 * `unknown' or `no connection' on a PC. We assume that a device with 699 * `no connection' either doesn't have an interrupt (in which case the 700 * pin number should be 0, and would have been noticed above), or 701 * wasn't configured by the BIOS (in which case we punt, since there's 702 * no real way we can know how the interrupt lines are mapped in the 703 * hardware). 704 * 705 * XXX 706 * Since IRQ 0 is only used by the clock, and we can't actually be sure 707 * that the BIOS did its job, we also recognize that as meaning that 708 * the BIOS has not configured the device. 709 */ 710 if (line == 0 || line == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 711 goto bad; 712 713 if (line >= ICU_LEN) { 714 printf("pci_intr_map: bad interrupt line %d\n", line); 715 goto bad; 716 } 717 if (line == 2) { 718 printf("pci_intr_map: changed line 2 to line 9\n"); 719 line = 9; 720 } 721 722 #if NIOAPIC > 0 723 if (!(ihp->line & PCI_INT_VIA_ISA) && mp_busses != NULL) { 724 if (mip == NULL && mp_isa_bus) { 725 for (mip = mp_isa_bus->mb_intrs; mip != NULL; 726 mip = mip->next) { 727 if (mip->bus_pin == line) { 728 ihp->line = mip->ioapic_ih | line; 729 return 0; 730 } 731 } 732 } 733 if (mip == NULL && mp_eisa_bus) { 734 for (mip = mp_eisa_bus->mb_intrs; mip != NULL; 735 mip = mip->next) { 736 if (mip->bus_pin == line) { 737 ihp->line = mip->ioapic_ih | line; 738 return 0; 739 } 740 } 741 } 742 if (mip == NULL) { 743 printf("pci_intr_map: " 744 "bus %d dev %d func %d pin %d; line %d\n", 745 bus, dev, func, pin, line); 746 printf("pci_intr_map: no MP mapping found\n"); 747 } 748 } 749 #endif 750 751 return 0; 752 753 bad: 754 ihp->line = -1; 755 return 1; 756 } 757 758 const char * 759 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 760 { 761 static char irqstr[64]; 762 int line = ih.line & APIC_INT_LINE_MASK; 763 764 if (ih.line & APIC_INT_VIA_MSG) 765 return ("msi"); 766 767 #if NIOAPIC > 0 768 if (ih.line & APIC_INT_VIA_APIC) { 769 snprintf(irqstr, sizeof irqstr, "apic %d int %d", 770 APIC_IRQ_APIC(ih.line), APIC_IRQ_PIN(ih.line)); 771 return (irqstr); 772 } 773 #endif 774 775 if (line == 0 || line >= ICU_LEN || line == 2) 776 panic("pci_intr_string: bogus handle 0x%x", line); 777 778 snprintf(irqstr, sizeof irqstr, "irq %d", line); 779 return (irqstr); 780 } 781 782 #include "acpiprt.h" 783 #if NACPIPRT > 0 784 void acpiprt_route_interrupt(int bus, int dev, int pin); 785 #endif 786 787 extern struct intrhand *apic_intrhand[256]; 788 extern int apic_maxlevel[256]; 789 790 void * 791 pci_intr_establish_cpu(pci_chipset_tag_t pc, pci_intr_handle_t ih, 792 int level, struct cpu_info *ci, 793 int (*func)(void *), void *arg, const char *what) 794 { 795 if (ci != NULL && ci != &cpu_info_primary) 796 return (NULL); 797 798 return pci_intr_establish(pc, ih, level, func, arg, what); 799 } 800 801 void * 802 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 803 int (*func)(void *), void *arg, const char *what) 804 { 805 void *ret; 806 int bus, dev; 807 int l = ih.line & APIC_INT_LINE_MASK; 808 pcitag_t tag = ih.tag; 809 int irq = ih.line; 810 811 if (ih.line & APIC_INT_VIA_MSG) { 812 struct intrhand *ih; 813 pcireg_t reg, addr; 814 int off, vec; 815 int flags; 816 817 flags = level & IPL_MPSAFE; 818 level &= ~IPL_MPSAFE; 819 820 KASSERT(level <= IPL_TTY || flags & IPL_MPSAFE); 821 822 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 823 panic("%s: no msi capability", __func__); 824 825 vec = idt_vec_alloc(level, level + 15); 826 if (vec == 0) 827 return (NULL); 828 829 ih = malloc(sizeof(*ih), M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 830 if (ih == NULL) 831 panic("%s: can't malloc handler info", __func__); 832 833 ih->ih_fun = func; 834 ih->ih_arg = arg; 835 ih->ih_next = NULL; 836 ih->ih_level = level; 837 ih->ih_flags = flags; 838 ih->ih_irq = irq; 839 ih->ih_pin = tag.mode1; 840 ih->ih_vec = vec; 841 evcount_attach(&ih->ih_count, what, &ih->ih_vec); 842 843 apic_maxlevel[vec] = level; 844 apic_intrhand[vec] = ih; 845 idt_vec_set(vec, apichandler[vec & 0xf]); 846 847 addr = 0xfee00000UL | (cpu_info_primary.ci_apicid << 12); 848 849 if (reg & PCI_MSI_MC_C64) { 850 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr); 851 pci_conf_write(pc, tag, off + PCI_MSI_MAU32, 0); 852 pci_conf_write(pc, tag, off + PCI_MSI_MD64, vec); 853 } else { 854 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr); 855 pci_conf_write(pc, tag, off + PCI_MSI_MD32, vec); 856 } 857 pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE); 858 return (ih); 859 } 860 861 pci_decompose_tag(pc, ih.tag, &bus, &dev, NULL); 862 #if NACPIPRT > 0 863 acpiprt_route_interrupt(bus, dev, ih.pin); 864 #endif 865 866 #if NIOAPIC > 0 867 if (l != -1 && ih.line & APIC_INT_VIA_APIC) 868 return (apic_intr_establish(ih.line, IST_LEVEL, level, func, 869 arg, what)); 870 #endif 871 if (l == 0 || l >= ICU_LEN || l == 2) 872 panic("pci_intr_establish: bogus handle 0x%x", l); 873 874 ret = isa_intr_establish(NULL, l, IST_LEVEL, level, func, arg, what); 875 #if NPCIBIOS > 0 876 if (ret) 877 pci_intr_route_link(pc, &ih); 878 #endif 879 return (ret); 880 } 881 882 void 883 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 884 { 885 struct intrhand *ih = cookie; 886 887 if (ih->ih_irq & APIC_INT_VIA_MSG) { 888 pcitag_t tag = { .mode1 = ih->ih_pin }; 889 pcireg_t reg; 890 int off; 891 892 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) 893 pci_conf_write(pc, tag, off, reg &= ~PCI_MSI_MC_MSIE); 894 895 apic_maxlevel[ih->ih_vec] = 0; 896 apic_intrhand[ih->ih_vec] = NULL; 897 idt_vec_free(ih->ih_vec); 898 899 evcount_detach(&ih->ih_count); 900 free(ih, M_DEVBUF, sizeof *ih); 901 return; 902 } 903 904 /* XXX oh, unroute the pci int link? */ 905 isa_intr_disestablish(NULL, cookie); 906 } 907 908 struct extent *pciio_ex; 909 struct extent *pcimem_ex; 910 struct extent *pcibus_ex; 911 912 void 913 pci_init_extents(void) 914 { 915 bios_memmap_t *bmp; 916 u_int64_t size; 917 918 if (pciio_ex == NULL) { 919 /* 920 * We only have 64K of addressable I/O space. 921 * However, since BARs may contain garbage, we cover 922 * the full 32-bit address space defined by PCI of 923 * which we only make the first 64K available. 924 */ 925 pciio_ex = extent_create("pciio", 0, 0xffffffff, M_DEVBUF, 926 NULL, 0, EX_NOWAIT | EX_FILLED); 927 if (pciio_ex == NULL) 928 return; 929 extent_free(pciio_ex, 0, 0x10000, EX_NOWAIT); 930 } 931 932 if (pcimem_ex == NULL) { 933 pcimem_ex = extent_create("pcimem", 0, 0xffffffff, M_DEVBUF, 934 NULL, 0, EX_NOWAIT); 935 if (pcimem_ex == NULL) 936 return; 937 938 for (bmp = bios_memmap; bmp->type != BIOS_MAP_END; bmp++) { 939 /* 940 * Ignore address space beyond 4G. 941 */ 942 if (bmp->addr >= 0x100000000ULL) 943 continue; 944 size = bmp->size; 945 if (bmp->addr + size >= 0x100000000ULL) 946 size = 0x100000000ULL - bmp->addr; 947 948 /* Ignore zero-sized regions. */ 949 if (size == 0) 950 continue; 951 952 if (extent_alloc_region(pcimem_ex, bmp->addr, size, 953 EX_NOWAIT)) 954 printf("memory map conflict 0x%llx/0x%llx\n", 955 bmp->addr, bmp->size); 956 } 957 958 /* Take out the video buffer area and BIOS areas. */ 959 extent_alloc_region(pcimem_ex, IOM_BEGIN, IOM_SIZE, 960 EX_CONFLICTOK | EX_NOWAIT); 961 } 962 963 if (pcibus_ex == NULL) { 964 pcibus_ex = extent_create("pcibus", 0, 0xff, M_DEVBUF, 965 NULL, 0, EX_NOWAIT); 966 } 967 } 968 969 #include "acpi.h" 970 #if NACPI > 0 971 void acpi_pci_match(struct device *, struct pci_attach_args *); 972 pcireg_t acpi_pci_min_powerstate(pci_chipset_tag_t, pcitag_t); 973 void acpi_pci_set_powerstate(pci_chipset_tag_t, pcitag_t, int, int); 974 #endif 975 976 void 977 pci_dev_postattach(struct device *dev, struct pci_attach_args *pa) 978 { 979 #if NACPI > 0 980 acpi_pci_match(dev, pa); 981 #endif 982 } 983 984 pcireg_t 985 pci_min_powerstate(pci_chipset_tag_t pc, pcitag_t tag) 986 { 987 #if NACPI > 0 988 return acpi_pci_min_powerstate(pc, tag); 989 #else 990 return pci_get_powerstate(pc, tag); 991 #endif 992 } 993 994 void 995 pci_set_powerstate_md(pci_chipset_tag_t pc, pcitag_t tag, int state, int pre) 996 { 997 #if NACPI > 0 998 acpi_pci_set_powerstate(pc, tag, state, pre); 999 #endif 1000 } 1001