xref: /openbsd/sys/arch/i386/pci/piix.c (revision 404b540a)
1 /*	$OpenBSD: piix.c,v 1.9 2008/06/26 05:42:11 ray Exp $	*/
2 /*	$NetBSD: piix.c,v 1.1 1999/11/17 01:21:20 thorpej Exp $	*/
3 
4 /*-
5  * Copyright (c) 1999 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to The NetBSD Foundation
9  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10  * NASA Ames Research Center.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 /*
35  * Copyright (c) 1999, by UCHIYAMA Yasushi
36  * All rights reserved.
37  *
38  * Redistribution and use in source and binary forms, with or without
39  * modification, are permitted provided that the following conditions
40  * are met:
41  * 1. Redistributions of source code must retain the above copyright
42  *    notice, this list of conditions and the following disclaimer.
43  * 2. The name of the developer may NOT be used to endorse or promote products
44  *    derived from this software without specific prior written permission.
45  *
46  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
47  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
48  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
49  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
50  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
51  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
52  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
53  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
54  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
55  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56  * SUCH DAMAGE.
57  */
58 
59 /*
60  * Support for the Intel PIIX PCI-ISA bridge interrupt controller.
61  */
62 
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/device.h>
66 #include <sys/malloc.h>
67 
68 #include <machine/intr.h>
69 #include <machine/bus.h>
70 
71 #include <dev/pci/pcivar.h>
72 #include <dev/pci/pcireg.h>
73 #include <dev/pci/pcidevs.h>
74 
75 #include <i386/pci/pcibiosvar.h>
76 #include <i386/pci/piixreg.h>
77 #include <i386/pci/piixvar.h>
78 
79 #ifdef PIIX_DEBUG
80 #define	DPRINTF(arg) printf arg
81 #else
82 #define	DPRINTF(arg)
83 #endif
84 
85 int	piix_getclink(pciintr_icu_handle_t, int, int *);
86 int	piix_get_intr(pciintr_icu_handle_t, int, int *);
87 int	piix_set_intr(pciintr_icu_handle_t, int, int);
88 #ifdef PIIX_DEBUG
89 void	piix_pir_dump(struct piix_handle *);
90 #endif
91 
92 const struct pciintr_icu piix_pci_icu = {
93 	piix_getclink,
94 	piix_get_intr,
95 	piix_set_intr,
96 	piix_get_trigger,
97 	piix_set_trigger,
98 };
99 
100 int
101 piix_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag,
102     pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp)
103 {
104 	struct piix_handle *ph;
105 
106 	ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT);
107 	if (ph == NULL)
108 		return (1);
109 
110 	ph->ph_iot = iot;
111 	ph->ph_pc = pc;
112 	ph->ph_tag = tag;
113 
114 	if (bus_space_map(iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0,
115 	    &ph->ph_elcr_ioh) != 0) {
116 		free(ph, M_DEVBUF);
117 		return (1);
118 	}
119 
120 #ifdef PIIX_DEBUG
121 	piix_pir_dump(ph);
122 #endif
123 	*ptagp = &piix_pci_icu;
124 	*phandp = ph;
125 	return (0);
126 }
127 
128 int
129 piix_getclink(pciintr_icu_handle_t v, int link, int *clinkp)
130 {
131 	DPRINTF(("PIIX link value 0x%x: ", link));
132 
133 	/* Pattern 1: simple. */
134 	if (PIIX_LEGAL_LINK(link - 1)) {
135 		*clinkp = link - 1;
136 		DPRINTF(("PIRQ %d (simple)\n", *clinkp));
137 		return (0);
138 	}
139 
140 	/* Pattern 2: configuration register offset */
141 	if (link >= 0x60 && link <= 0x63) {
142 		*clinkp = link - 0x60;
143 		DPRINTF(("PIRQ %d (register offset)\n", *clinkp));
144 		return (0);
145 	}
146 
147 	/* Pattern 3: configuration register offset, PIRQE# - PIRQH# */
148 	if (link >= 0x68 && link <= 0x6b) {
149 		*clinkp = link - 0x64;
150 		DPRINTF(("PIRQ %d (high register offset)\n", *clinkp));
151 		return (0);
152 	}
153 
154 	DPRINTF(("bogus IRQ selection source\n"));
155 	return (1);
156 }
157 
158 int
159 piix_get_intr(pciintr_icu_handle_t v, int clink, int *irqp)
160 {
161 	struct piix_handle *ph = v;
162 	int shift, off;
163 	pcireg_t reg;
164 
165 	if (PIIX_LEGAL_LINK(clink) == 0)
166 		return (1);
167 
168 	off = PIIX_CFG_PIRQ;
169 	if (clink > 3) {
170 		off += 8;
171 		clink -= 4;
172 	}
173 
174 	reg = pci_conf_read(ph->ph_pc, ph->ph_tag, off);
175 	shift = clink << 3;
176 	if ((reg >> shift) & PIIX_CFG_PIRQ_NONE)
177 		*irqp = I386_PCI_INTERRUPT_LINE_NO_CONNECTION;
178 	else
179 		*irqp = PIIX_PIRQ(reg, clink);
180 
181 	return (0);
182 }
183 
184 int
185 piix_set_intr(pciintr_icu_handle_t v, int clink, int irq)
186 {
187 	struct piix_handle *ph = v;
188 	int shift, off;
189 	pcireg_t reg;
190 
191 	if (PIIX_LEGAL_LINK(clink) == 0 || PIIX_LEGAL_IRQ(irq) == 0)
192 		return (1);
193 
194 	off = PIIX_CFG_PIRQ;
195 	if (clink > 3) {
196 		off += 8;
197 		clink -= 4;
198 	}
199 
200 	reg = pci_conf_read(ph->ph_pc, ph->ph_tag, off);
201 	shift = clink << 3;
202 	reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift);
203 	reg |= irq << shift;
204 	pci_conf_write(ph->ph_pc, ph->ph_tag, off, reg);
205 
206 	return (0);
207 }
208 
209 int
210 piix_get_trigger(pciintr_icu_handle_t v, int irq, int *triggerp)
211 {
212 	struct piix_handle *ph = v;
213 	int off, bit;
214 	u_int8_t elcr;
215 
216 	if (PIIX_LEGAL_IRQ(irq) == 0)
217 		return (1);
218 
219 	off = (irq > 7) ? 1 : 0;
220 	bit = irq & 7;
221 
222 	elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off);
223 	if (elcr & (1 << bit))
224 		*triggerp = IST_LEVEL;
225 	else
226 		*triggerp = IST_EDGE;
227 
228 	return (0);
229 }
230 
231 int
232 piix_set_trigger(pciintr_icu_handle_t v, int irq, int trigger)
233 {
234 	struct piix_handle *ph = v;
235 	int off, bit;
236 	u_int8_t elcr;
237 
238 	if (PIIX_LEGAL_IRQ(irq) == 0)
239 		return (1);
240 
241 	off = (irq > 7) ? 1 : 0;
242 	bit = irq & 7;
243 
244 	elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off);
245 	if (trigger == IST_LEVEL)
246 		elcr |= (1 << bit);
247 	else
248 		elcr &= ~(1 << bit);
249 	bus_space_write_1(ph->ph_iot, ph->ph_elcr_ioh, off, elcr);
250 
251 	return (0);
252 }
253 
254 #ifdef PIIX_DEBUG
255 void
256 piix_pir_dump(struct piix_handle *ph)
257 {
258 	int i, irq;
259 	pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ);
260 	u_int8_t elcr[2];
261 
262 	elcr[0] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 0);
263 	elcr[1] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 1);
264 
265 	for (i = 0; i < 8; i++) {
266 		if (i == 4)
267 			irqs = pci_conf_read(ph->ph_pc, ph->ph_tag,
268 			    PIIX_CFG_PIRQH);
269 
270 		irq = PIIX_PIRQ(irqs, i);
271 		if (irq & PIIX_CFG_PIRQ_NONE)
272 			printf("PIIX PIRQ %d: irq none (0x%x)\n", i, irq);
273 		else
274 			printf("PIIX PIRQ %d: irq %d\n", i, irq);
275 	}
276 
277 	printf("PIIX irq:");
278 	for (i = 0; i < 16; i++)
279 		printf(" %2d", i);
280 	printf("\n");
281 	printf(" trigger:");
282 	for (i = 0; i < 16; i++)
283 		printf("  %c", (elcr[(i & 8) ? 1 : 0] & (1 << (i & 7))) ?
284 		       'L' : 'E');
285 	printf("\n");
286 }
287 #endif /* PIIX_DEBUG */
288