xref: /openbsd/sys/arch/i386/pci/sis85c503.c (revision 4bdff4be)
1 /*	$OpenBSD: sis85c503.c,v 1.9 2023/01/30 10:49:05 jsg Exp $	*/
2 /*	$NetBSD: sis85c503.c,v 1.2 2000/07/18 11:24:09 soda Exp $	*/
3 
4 /*-
5  * Copyright (c) 1999 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to The NetBSD Foundation
9  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10  * NASA Ames Research Center.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 /*
35  * Copyright (c) 1999, by UCHIYAMA Yasushi
36  * All rights reserved.
37  *
38  * Redistribution and use in source and binary forms, with or without
39  * modification, are permitted provided that the following conditions
40  * are met:
41  * 1. Redistributions of source code must retain the above copyright
42  *    notice, this list of conditions and the following disclaimer.
43  * 2. The name of the developer may NOT be used to endorse or promote products
44  *    derived from this software without specific prior written permission.
45  *
46  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
47  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
48  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
49  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
50  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
51  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
52  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
53  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
54  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
55  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56  * SUCH DAMAGE.
57  */
58 
59 /*
60  * Support for the SiS 85c503 PCI-ISA bridge interrupt controller.
61  */
62 
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 
66 #include <machine/intr.h>
67 #include <machine/bus.h>
68 
69 #include <dev/pci/pcivar.h>
70 
71 #include <i386/pci/pcibiosvar.h>
72 #include <i386/pci/sis85c503reg.h>
73 #include <i386/pci/piixvar.h>
74 
75 int	sis85c503_getclink(pciintr_icu_handle_t, int, int *);
76 int	sis85c503_get_intr(pciintr_icu_handle_t, int, int *);
77 int	sis85c503_set_intr(pciintr_icu_handle_t, int, int);
78 
79 const struct pciintr_icu sis85c503_pci_icu = {
80 	sis85c503_getclink,
81 	sis85c503_get_intr,
82 	sis85c503_set_intr,
83 	piix_get_trigger,
84 	piix_set_trigger,
85 };
86 
87 int
88 sis85c503_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag,
89     pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp)
90 {
91 
92 	if (piix_init(pc, iot, tag, ptagp, phandp) == 0) {
93 		*ptagp = &sis85c503_pci_icu;
94 		return (0);
95 	}
96 
97 	return (1);
98 }
99 
100 int
101 sis85c503_getclink(pciintr_icu_handle_t v, int link, int *clinkp)
102 {
103 
104 	/* Pattern 1: simple. */
105 	if (link >= 1 && link <= 4) {
106 		*clinkp = SIS85C503_CFG_PIRQ_REGSTART + link - 1;
107 		return (0);
108 	}
109 
110 	/* Pattern 2: configuration register offset */
111 	if (link >= SIS85C503_CFG_PIRQ_REGSTART &&
112 	    link <= SIS85C503_CFG_PIRQ_REGEND) {
113 		*clinkp = link;
114 		return (0);
115 	}
116 
117 	return (1);
118 }
119 
120 int
121 sis85c503_get_intr(pciintr_icu_handle_t v, int clink, int *irqp)
122 {
123 	struct piix_handle *ph = v;
124 	pcireg_t reg;
125 
126 	if (SIS85C503_LEGAL_LINK(clink) == 0)
127 		return (1);
128 
129 	reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
130 	    SIS85C503_CFG_PIRQ_REGOFS(clink));
131 	reg = SIS85C503_CFG_PIRQ_REG(reg, clink);
132 
133 	if (reg & SIS85C503_CFG_PIRQ_ROUTE_DISABLE)
134 		*irqp = 0xff;
135 	else
136 		*irqp = reg & SIS85C503_CFG_PIRQ_INTR_MASK;
137 
138 	return (0);
139 }
140 
141 int
142 sis85c503_set_intr(pciintr_icu_handle_t v, int clink, int irq)
143 {
144 	struct piix_handle *ph = v;
145 	int shift;
146 	pcireg_t reg;
147 
148 	if (SIS85C503_LEGAL_LINK(clink) == 0 || SIS85C503_LEGAL_IRQ(irq) == 0)
149 		return (1);
150 
151 	reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
152 	    SIS85C503_CFG_PIRQ_REGOFS(clink));
153 	shift = SIS85C503_CFG_PIRQ_SHIFT(clink);
154 	reg &= ~((SIS85C503_CFG_PIRQ_ROUTE_DISABLE |
155 	    SIS85C503_CFG_PIRQ_INTR_MASK) << shift);
156 	reg |= (irq << shift);
157 	pci_conf_write(ph->ph_pc, ph->ph_tag, SIS85C503_CFG_PIRQ_REGOFS(clink),
158 	    reg);
159 
160 	return (0);
161 }
162