1 /* $OpenBSD: via82c586.c,v 1.11 2008/06/26 05:42:11 ray Exp $ */ 2 /* $NetBSD: via82c586.c,v 1.2 2000/07/18 11:24:09 soda Exp $ */ 3 4 /*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1999, by UCHIYAMA Yasushi 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. The name of the developer may NOT be used to endorse or promote products 44 * derived from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 */ 58 59 /* 60 * Support for the VIA 82c586 PCI-ISA bridge interrupt controller. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/device.h> 66 67 #include <machine/intr.h> 68 #include <machine/bus.h> 69 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcidevs.h> 73 74 #include <i386/pci/pcibiosvar.h> 75 #include <i386/pci/via82c586reg.h> 76 #include <i386/pci/piixvar.h> 77 78 int via82c586_getclink(pciintr_icu_handle_t, int, int *); 79 int via82c586_get_intr(pciintr_icu_handle_t, int, int *); 80 int via82c586_set_intr(pciintr_icu_handle_t, int, int); 81 int via82c586_get_trigger(pciintr_icu_handle_t, int, int *); 82 int via82c586_set_trigger(pciintr_icu_handle_t, int, int); 83 84 const struct pciintr_icu via82c586_pci_icu = { 85 via82c586_getclink, 86 via82c586_get_intr, 87 via82c586_set_intr, 88 via82c586_get_trigger, 89 via82c586_set_trigger, 90 }; 91 92 const int vp3_cfg_trigger_shift[] = { 93 VP3_CFG_TRIGGER_SHIFT_PIRQA, 94 VP3_CFG_TRIGGER_SHIFT_PIRQB, 95 VP3_CFG_TRIGGER_SHIFT_PIRQC, 96 VP3_CFG_TRIGGER_SHIFT_PIRQD, 97 }; 98 99 #define VP3_TRIGGER(reg, pirq) (((reg) >> vp3_cfg_trigger_shift[(pirq)]) & \ 100 VP3_CFG_TRIGGER_MASK) 101 102 const int vp3_cfg_intr_shift[] = { 103 VP3_CFG_INTR_SHIFT_PIRQA, 104 VP3_CFG_INTR_SHIFT_PIRQB, 105 VP3_CFG_INTR_SHIFT_PIRQC, 106 VP3_CFG_INTR_SHIFT_PIRQD, 107 VP3_CFG_INTR_SHIFT_PIRQ0, 108 VP3_CFG_INTR_SHIFT_PIRQ1, 109 VP3_CFG_INTR_SHIFT_PIRQ2, 110 }; 111 112 #define VP3_PIRQ(reg, pirq) (((reg) >> vp3_cfg_intr_shift[(pirq)]) & \ 113 VP3_CFG_INTR_MASK) 114 115 int 116 via82c586_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag, 117 pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp) 118 { 119 pcireg_t reg; 120 121 if (piix_init(pc, iot, tag, ptagp, phandp) == 0) { 122 *ptagp = &via82c586_pci_icu; 123 124 /* 125 * Enable EISA ELCR. 126 */ 127 reg = pci_conf_read(pc, tag, VP3_CFG_KBDMISCCTRL12_REG); 128 reg |= VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE << 129 VP3_CFG_MISCCTRL2_SHIFT; 130 pci_conf_write(pc, tag, VP3_CFG_KBDMISCCTRL12_REG, reg); 131 132 return (0); 133 } 134 135 return (1); 136 } 137 138 int 139 via82c586_getclink(pciintr_icu_handle_t v, int link, int *clinkp) 140 { 141 142 if (VP3_LEGAL_LINK(link - 1)) { 143 *clinkp = link - 1; 144 return (0); 145 } 146 147 return (1); 148 } 149 150 int 151 via82c586_get_intr(pciintr_icu_handle_t v, int clink, int *irqp) 152 { 153 struct piix_handle *ph = v; 154 pcireg_t reg; 155 int val; 156 157 if (VP3_LEGAL_LINK(clink) == 0) 158 return (1); 159 160 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG); 161 val = VP3_PIRQ(reg, clink); 162 *irqp = (val == VP3_PIRQ_NONE)? 163 I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val; 164 165 return (0); 166 } 167 168 int 169 via82c586_set_intr(pciintr_icu_handle_t v, int clink, int irq) 170 { 171 struct piix_handle *ph = v; 172 int shift, val; 173 pcireg_t reg; 174 175 if (VP3_LEGAL_LINK(clink) == 0 || VP3_LEGAL_IRQ(irq) == 0) 176 return (1); 177 178 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG); 179 via82c586_get_intr(v, clink, &val); 180 shift = vp3_cfg_intr_shift[clink]; 181 reg &= ~(VP3_CFG_INTR_MASK << shift); 182 reg |= (irq << shift); 183 pci_conf_write(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG, reg); 184 if (via82c586_get_intr(v, clink, &val) != 0 || 185 val != irq) 186 return (1); 187 188 return (0); 189 } 190 191 int 192 via82c586_get_trigger(pciintr_icu_handle_t v, int irq, int *triggerp) 193 { 194 struct piix_handle *ph = v; 195 int i, error, check_consistency, pciirq, pcitrigger = IST_NONE; 196 pcireg_t reg; 197 198 if (VP3_LEGAL_IRQ(irq) == 0) 199 return (1); 200 201 check_consistency = 0; 202 for (i = 0; i <= 3; i++) { 203 via82c586_get_intr(v, i, &pciirq); 204 if (pciirq == irq) { 205 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, 206 VP3_CFG_PIRQ_REG); 207 if (VP3_TRIGGER(reg, i) == VP3_CFG_TRIGGER_EDGE) 208 pcitrigger = IST_EDGE; 209 else 210 pcitrigger = IST_LEVEL; 211 check_consistency = 1; 212 break; 213 } 214 } 215 216 error = piix_get_trigger(v, irq, triggerp); 217 if (error == 0 && check_consistency && pcitrigger != *triggerp) 218 return (1); 219 return (error); 220 } 221 222 int 223 via82c586_set_trigger(pciintr_icu_handle_t v, int irq, int trigger) 224 { 225 struct piix_handle *ph = v; 226 int i, pciirq, shift, testtrig; 227 pcireg_t reg; 228 229 if (VP3_LEGAL_IRQ(irq) == 0) 230 return (1); 231 232 for (i = 0; i <= 3; i++) { 233 via82c586_get_intr(v, i, &pciirq); 234 if (pciirq == irq) { 235 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, 236 VP3_CFG_PIRQ_REG); 237 shift = vp3_cfg_trigger_shift[i]; 238 /* XXX we only upgrade the trigger here */ 239 if (trigger == IST_LEVEL) 240 reg &= ~(VP3_CFG_TRIGGER_MASK << shift); 241 pci_conf_write(ph->ph_pc, ph->ph_tag, 242 VP3_CFG_PIRQ_REG, reg); 243 break; 244 } 245 } 246 247 if (piix_set_trigger(v, irq, trigger) != 0 || 248 via82c586_get_trigger(v, irq, &testtrig) != 0 || 249 testtrig != trigger) 250 return (1); 251 252 return (0); 253 } 254