1*70641ad1Svisa /* $OpenBSD: cpu.h,v 1.8 2017/07/30 16:05:24 visa Exp $ */ 2cd5aee8bSmiod /*- 3cd5aee8bSmiod * Copyright (c) 1992, 1993 4cd5aee8bSmiod * The Regents of the University of California. All rights reserved. 5cd5aee8bSmiod * 6cd5aee8bSmiod * This code is derived from software contributed to Berkeley by 7cd5aee8bSmiod * Ralph Campbell and Rick Macklem. 8cd5aee8bSmiod * 9cd5aee8bSmiod * Redistribution and use in source and binary forms, with or without 10cd5aee8bSmiod * modification, are permitted provided that the following conditions 11cd5aee8bSmiod * are met: 12cd5aee8bSmiod * 1. Redistributions of source code must retain the above copyright 13cd5aee8bSmiod * notice, this list of conditions and the following disclaimer. 14cd5aee8bSmiod * 2. Redistributions in binary form must reproduce the above copyright 15cd5aee8bSmiod * notice, this list of conditions and the following disclaimer in the 16cd5aee8bSmiod * documentation and/or other materials provided with the distribution. 17cd5aee8bSmiod * 3. Neither the name of the University nor the names of its contributors 18cd5aee8bSmiod * may be used to endorse or promote products derived from this software 19cd5aee8bSmiod * without specific prior written permission. 20cd5aee8bSmiod * 21cd5aee8bSmiod * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22cd5aee8bSmiod * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23cd5aee8bSmiod * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24cd5aee8bSmiod * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25cd5aee8bSmiod * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26cd5aee8bSmiod * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27cd5aee8bSmiod * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28cd5aee8bSmiod * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29cd5aee8bSmiod * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30cd5aee8bSmiod * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31cd5aee8bSmiod * SUCH DAMAGE. 32cd5aee8bSmiod * 33cd5aee8bSmiod * Copyright (C) 1989 Digital Equipment Corporation. 34cd5aee8bSmiod * Permission to use, copy, modify, and distribute this software and 35cd5aee8bSmiod * its documentation for any purpose and without fee is hereby granted, 36cd5aee8bSmiod * provided that the above copyright notice appears in all copies. 37cd5aee8bSmiod * Digital Equipment Corporation makes no representations about the 38cd5aee8bSmiod * suitability of this software for any purpose. It is provided "as is" 39cd5aee8bSmiod * without express or implied warranty. 40cd5aee8bSmiod * 41cd5aee8bSmiod * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 42cd5aee8bSmiod */ 43cd5aee8bSmiod 44cd5aee8bSmiod #ifdef _KERNEL 45cd5aee8bSmiod 4639de0dfdSvisa #if defined(MULTIPROCESSOR) && !defined(_LOCORE) 47*70641ad1Svisa #define MAXCPUS 4 4839de0dfdSvisa struct cpu_info; 4939de0dfdSvisa struct cpu_info *hw_getcurcpu(void); 5039de0dfdSvisa void hw_setcurcpu(struct cpu_info *); 5139de0dfdSvisa void hw_cpu_boot_secondary(struct cpu_info *); 5239de0dfdSvisa void hw_cpu_hatch(struct cpu_info *); 5339de0dfdSvisa void hw_cpu_spinup_trampoline(struct cpu_info *); 5439de0dfdSvisa int hw_ipi_intr_establish(int (*)(void *), u_long); 5539de0dfdSvisa void hw_ipi_intr_set(u_long); 5639de0dfdSvisa void hw_ipi_intr_clear(u_long); 5739de0dfdSvisa #endif /* MULTIPROCESSOR && !_LOCORE */ 5839de0dfdSvisa 59f8fa4920Smiod #if defined(CPU_LOONGSON2) && !defined(CPU_LOONGSON3) 60c1805af1Smiod #define Mips_SyncCache(ci) \ 61c1805af1Smiod Loongson2_SyncCache((ci)) 62c1805af1Smiod #define Mips_InvalidateICache(ci, va, l) \ 63c1805af1Smiod Loongson2_InvalidateICache((ci), (va), (l)) 6480941abeSmiod #define Mips_InvalidateICachePage(ci, va) \ 6580941abeSmiod Loongson2_InvalidateICachePage((ci), (va)) 6680941abeSmiod #define Mips_SyncICache(ci) \ 6780941abeSmiod Loongson2_SyncICache((ci)) 68c1805af1Smiod #define Mips_SyncDCachePage(ci, va, pa) \ 69b94f5bc5Smiod Loongson2_SyncDCachePage((ci), (va), (pa)) 701a4be959Svisa #define Mips_HitSyncDCachePage(ci, va, pa) \ 711a4be959Svisa Loongson2_SyncDCachePage((ci), (va), (pa)) 72b94f5bc5Smiod #define Mips_HitSyncDCache(ci, va, l) \ 73b94f5bc5Smiod Loongson2_HitSyncDCache((ci), (va), (l)) 74b94f5bc5Smiod #define Mips_IOSyncDCache(ci, va, l, h) \ 75b94f5bc5Smiod Loongson2_IOSyncDCache((ci), (va), (l), (h)) 76b94f5bc5Smiod #define Mips_HitInvalidateDCache(ci, va, l) \ 77b94f5bc5Smiod Loongson2_HitInvalidateDCache((ci), (va), (l)) 78f8fa4920Smiod #endif 79f8fa4920Smiod 80f8fa4920Smiod #if defined(CPU_LOONGSON3) && !defined(CPU_LOONGSON2) 81f8fa4920Smiod #define Mips_SyncCache(ci) \ 82f8fa4920Smiod Loongson3_SyncCache((ci)) 83f8fa4920Smiod #define Mips_InvalidateICache(ci, va, l) \ 84f8fa4920Smiod Loongson3_InvalidateICache((ci), (va), (l)) 85f8fa4920Smiod #define Mips_InvalidateICachePage(ci, va) \ 86f8fa4920Smiod Loongson3_InvalidateICachePage((ci), (va)) 87f8fa4920Smiod #define Mips_SyncICache(ci) \ 88f8fa4920Smiod Loongson3_SyncICache((ci)) 89f8fa4920Smiod #define Mips_SyncDCachePage(ci, va, pa) \ 90f8fa4920Smiod Loongson3_SyncDCachePage((ci), (va), (pa)) 911a4be959Svisa #define Mips_HitSyncDCachePage(ci, va, pa) \ 921a4be959Svisa Loongson3_SyncDCachePage((ci), (va), (pa)) 93f8fa4920Smiod #define Mips_HitSyncDCache(ci, va, l) \ 94f8fa4920Smiod Loongson3_HitSyncDCache((ci), (va), (l)) 95f8fa4920Smiod #define Mips_IOSyncDCache(ci, va, l, h) \ 96f8fa4920Smiod Loongson3_IOSyncDCache((ci), (va), (l), (h)) 97f8fa4920Smiod #define Mips_HitInvalidateDCache(ci, va, l) \ 98f8fa4920Smiod Loongson3_HitInvalidateDCache((ci), (va), (l)) 99f8fa4920Smiod #endif 100cd5aee8bSmiod 101cd5aee8bSmiod #endif /* _KERNEL */ 102cd5aee8bSmiod 103cd5aee8bSmiod #include <mips64/cpu.h> 104