1 /* $OpenBSD: uni_n.c,v 1.17 2015/03/30 13:45:02 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Martin Pieuchot 5 * Copyright (c) 1998-2001 Dale Rahn. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/device.h> 31 #include <sys/systm.h> 32 33 #include <machine/bus.h> 34 #include <machine/autoconf.h> 35 36 #include <dev/ofw/openfirm.h> 37 38 #define UNINORTH_CLK_OFFSET 0x20 39 #define UNINORTH_POW_OFFSET 0x30 40 #define UNINORTH_STA_OFFSET 0x70 41 #define UNINORTH_MPIC_OFFSET 0xe0 42 43 #define UNINORTH_PCICLOCK_CTL 0x01 44 #define UNINORTH_ETHERNET_CTL 0x02 45 #define UNINORTH_FIREWIRE_CTL 0x04 46 47 #define UNINORTH_POW_NORMAL 0x00 48 #define UNINORTH_POW_IDLE 0x01 49 #define UNINORTH_POW_SLEEP 0x02 50 51 #define UNINORTH_MPIC_RESET 0x02 52 #define UNINORTH_MPIC_ENABLE 0x04 53 54 #define UNINORTH_SLEEPING 0x01 55 #define UNINORTH_RUNNING 0x02 56 57 58 struct memc_softc { 59 struct device sc_dev; 60 struct ppc_bus_space sc_membus_space; 61 62 uint8_t *sc_baseaddr; 63 }; 64 65 int memcmatch(struct device *, void *, void *); 66 void memcattach(struct device *, struct device *, void *); 67 void memc_attach_children(struct memc_softc *sc, int memc_node); 68 int memc_print(void *aux, const char *name); 69 70 struct cfdriver memc_cd = { 71 NULL, "memc", DV_DULL 72 }; 73 74 const struct cfattach memc_ca = { 75 sizeof(struct memc_softc), memcmatch, memcattach 76 }; 77 78 void memc_sleep(void); 79 void memc_resume(void); 80 uint32_t memc_read(struct memc_softc *sc, int); 81 void memc_write(struct memc_softc *sc, int, uint32_t); 82 void memc_enable(struct memc_softc *, int, uint32_t); 83 void memc_disable(struct memc_softc *, int, uint32_t); 84 85 int 86 memcmatch(struct device *parent, void *cf, void *aux) 87 { 88 struct confargs *ca = aux; 89 90 if (strcmp(ca->ca_name, "memc") != 0) 91 return (0); 92 93 return (1); 94 } 95 96 void 97 memcattach(struct device *parent, struct device *self, void *aux) 98 { 99 struct memc_softc *sc = (struct memc_softc *)self; 100 struct confargs *ca = aux; 101 uint32_t rev, reg[2]; 102 char name[32]; 103 int len; 104 105 OF_getprop(ca->ca_node, "reg", ®, sizeof(reg)); 106 107 len = OF_getprop(ca->ca_node, "name", name, sizeof(name)); 108 if (len > 0) 109 name[len] = 0; 110 111 /* Map the first page in order to access the registers */ 112 if (strcmp(name, "u3") == 0 || strcmp(name, "u4") == 0) 113 sc->sc_baseaddr = mapiodev(reg[1], PAGE_SIZE); 114 else 115 sc->sc_baseaddr = mapiodev(reg[0], PAGE_SIZE); 116 117 /* Enable the ethernet clock */ 118 memc_enable(sc, UNINORTH_CLK_OFFSET, UNINORTH_ETHERNET_CTL); 119 len = OF_getprop(ca->ca_node, "device-rev", &rev, sizeof(rev)); 120 if (len < 0) 121 rev = 0; 122 123 printf (": %s rev 0x%x\n", name, rev); 124 125 memc_attach_children(sc, ca->ca_node); 126 } 127 128 void 129 memc_attach_children(struct memc_softc *sc, int memc_node) 130 { 131 struct confargs ca; 132 int node, namelen; 133 u_int32_t reg[20]; 134 int32_t intr[8]; 135 char name[32]; 136 137 ca.ca_iot = &sc->sc_membus_space; 138 ca.ca_dmat = 0; /* XXX */ 139 ca.ca_baseaddr = 0; /* XXX */ 140 sc->sc_membus_space.bus_base = ca.ca_baseaddr; 141 142 for (node = OF_child(memc_node); node; node = OF_peer(node)) { 143 namelen = OF_getprop(node, "name", name, sizeof(name)); 144 if (namelen < 0) 145 continue; 146 if (namelen >= sizeof(name)) 147 continue; 148 name[namelen] = 0; 149 150 ca.ca_name = name; 151 ca.ca_node = node; 152 ca.ca_nreg = OF_getprop(node, "reg", reg, sizeof(reg)); 153 ca.ca_reg = reg; 154 ca.ca_nintr = OF_getprop(node, "AAPL,interrupts", intr, 155 sizeof(intr)); 156 if (ca.ca_nintr == -1) 157 ca.ca_nintr = OF_getprop(node, "interrupts", intr, 158 sizeof(intr)); 159 ca.ca_intr = intr; 160 161 if (strcmp(ca.ca_name, "mpic") == 0) 162 memc_enable(sc, UNINORTH_MPIC_OFFSET, 163 UNINORTH_MPIC_RESET|UNINORTH_MPIC_ENABLE); 164 165 config_found((struct device *)sc, &ca, memc_print); 166 } 167 } 168 169 int 170 memc_print(void *aux, const char *name) 171 { 172 struct confargs *ca = aux; 173 /* we dont want extra stuff printing */ 174 if (name) 175 printf("\"%s\" at %s", ca->ca_name, name); 176 if (ca->ca_nreg > 0) 177 printf(" offset 0x%x", ca->ca_reg[0]); 178 return UNCONF; 179 } 180 181 void 182 memc_sleep(void) 183 { 184 struct memc_softc *sc = memc_cd.cd_devs[0]; 185 186 memc_write(sc, UNINORTH_STA_OFFSET, UNINORTH_SLEEPING); 187 DELAY(10); 188 memc_write(sc, UNINORTH_POW_OFFSET, UNINORTH_POW_SLEEP); 189 DELAY(10); 190 } 191 192 void 193 memc_resume(void) 194 { 195 struct memc_softc *sc = memc_cd.cd_devs[0]; 196 197 memc_write(sc, UNINORTH_POW_OFFSET, UNINORTH_POW_NORMAL); 198 DELAY(10); 199 memc_write(sc, UNINORTH_STA_OFFSET, UNINORTH_RUNNING); 200 DELAY(100); /* XXX */ 201 } 202 203 uint32_t 204 memc_read(struct memc_softc *sc, int offset) 205 { 206 return in32(sc->sc_baseaddr + offset); 207 } 208 209 void 210 memc_write(struct memc_softc *sc, int offset, uint32_t value) 211 { 212 out32(sc->sc_baseaddr + offset, value); 213 } 214 215 void 216 memc_enable(struct memc_softc *sc, int offset, uint32_t bits) 217 { 218 bits |= memc_read(sc, offset); 219 memc_write(sc, offset, bits); 220 } 221 222 void 223 memc_disable(struct memc_softc *sc, int offset, uint32_t bits) 224 { 225 bits = memc_read(sc, offset) & ~bits; 226 memc_write(sc, offset, bits); 227 } 228