1 /* $OpenBSD: mips_cpu.h,v 1.8 2018/04/09 13:46:15 visa Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 */ 44 45 #ifndef _MIPS64_CPUREGS_H_ 46 #define _MIPS64_CPUREGS_H_ 47 48 #if defined(_KERNEL) || defined(_STANDALONE) 49 50 /* 51 * Status register. 52 */ 53 54 #define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */ 55 #define SR_COP_0_BIT 0x10000000 56 #define SR_COP_1_BIT 0x20000000 57 #define SR_COP_2_BIT 0x40000000 58 #define SR_RP 0x08000000 59 #define SR_FR_32 0x04000000 60 #define SR_RE 0x02000000 61 #define SR_DSD 0x01000000 /* Only on R12000 */ 62 #define SR_BOOT_EXC_VEC 0x00400000 63 #define SR_TLB_SHUTDOWN 0x00200000 64 #define SR_SOFT_RESET 0x00100000 65 #define SR_DIAG_CH 0x00040000 66 #define SR_DIAG_CE 0x00020000 67 #define SR_DIAG_DE 0x00010000 68 #define SR_KX 0x00000080 69 #define SR_SX 0x00000040 70 #define SR_UX 0x00000020 71 #define SR_ERL 0x00000004 72 #define SR_EXL 0x00000002 73 #define SR_INT_ENAB 0x00000001 74 75 #define SOFT_INT_MASK_0 0x00000100 76 #define SOFT_INT_MASK_1 0x00000200 77 #define SR_INT_MASK_0 0x00000400 78 #define SR_INT_MASK_1 0x00000800 79 #define SR_INT_MASK_2 0x00001000 80 #define SR_INT_MASK_3 0x00002000 81 #define SR_INT_MASK_4 0x00004000 82 #define SR_INT_MASK_5 0x00008000 83 84 /* R8000-specific bits */ 85 #define SR_SERIALIZE_FPU 0x0000010000000000 86 #define SR_KPGSZ_SHIFT 36 87 #define SR_UPGSZ_SHIFT 32 88 #define SR_PGSZ_4K 0 89 #define SR_PGSZ_8K 1 90 #define SR_PGSZ_16K 2 91 #define SR_PGSZ_64K 3 92 #define SR_PGSZ_1M 4 93 #define SR_PGSZ_4M 5 94 #define SR_PGSZ_16M 6 95 #define SR_PGSZ_MASK 0x0f 96 97 #define SR_INT_MASK_6 0x00010000 98 #define SR_INT_MASK_7 0x00020000 99 #define SR_INT_MASK_8 0x00040000 100 101 #ifdef CPU_R8000 102 #define SR_XX 0x00000040 103 #define SR_KSU_MASK 0x00000010 104 #define SR_KSU_KERNEL 0x00000000 105 #define SR_INT_MASK 0x0007ff00 106 #else 107 #define SR_XX 0x80000000 108 #define SR_KSU_MASK 0x00000018 109 #define SR_KSU_SUPER 0x00000008 110 #define SR_KSU_KERNEL 0x00000000 111 #define SR_INT_MASK 0x0000ff00 112 #endif 113 /* SR_KSU_USER is in <mips64/cpu.h> for CLKF_USERMODE() */ 114 #ifndef SR_KSU_USER 115 #define SR_KSU_USER 0x00000010 116 #endif 117 118 /* 119 * Interrupt control register in RM7000. Expansion of interrupts. 120 */ 121 122 #define IC_INT_MASK 0x00003f00 /* Two msb reserved */ 123 #define IC_INT_MASK_6 0x00000100 124 #define IC_INT_MASK_7 0x00000200 125 #define IC_INT_MASK_8 0x00000400 126 #define IC_INT_MASK_9 0x00000800 127 #define IC_INT_TIMR 0x00001000 /* 12 Timer */ 128 #define IC_INT_PERF 0x00002000 /* 13 Performance counter */ 129 #define IC_INT_TE 0x00000080 /* Timer on INT11 */ 130 131 #define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 132 133 /* 134 * Cause register. 135 */ 136 137 #ifdef CPU_R8000 138 #define CR_BR_DELAY 0x8000000000000000 139 #define CR_EXC_CODE 0x000000f8 140 #define CR_EXC_CODE_SHIFT 3 141 #define CR_COP_ERR 0x10000000 142 #else 143 #define CR_BR_DELAY 0x80000000 144 #define CR_EXC_CODE 0x0000007c 145 #define CR_EXC_CODE_SHIFT 2 146 #define CR_COP_ERR 0x30000000 147 #endif 148 #define CR_COP1_ERR 0x10000000 149 #define CR_COP2_ERR 0x20000000 150 #define CR_COP3_ERR 0x20000000 151 #define CR_INT_SOFT0 0x00000100 152 #define CR_INT_SOFT1 0x00000200 153 #define CR_INT_0 0x00000400 154 #define CR_INT_1 0x00000800 155 #define CR_INT_2 0x00001000 156 #define CR_INT_3 0x00002000 157 #define CR_INT_4 0x00004000 158 #define CR_INT_5 0x00008000 159 /* Following on RM7000 and R8000 */ 160 #define CR_INT_6 0x00010000 161 #define CR_INT_7 0x00020000 162 #define CR_INT_8 0x00040000 163 /* Following on RM7000 */ 164 #define CR_INT_9 0x00080000 165 #define CR_INT_HARD 0x000ffc00 166 #define CR_INT_TIMR 0x00100000 /* 12 Timer */ 167 #define CR_INT_PERF 0x00200000 /* 13 Performance counter */ 168 /* R8000 specific */ 169 #define CR_FPE 0x01000000 170 #define CR_VCE 0x02000000 171 #define CR_BERR 0x04000000 172 #define CR_NMI 0x08000000 173 174 #ifdef CPU_R8000 175 #define CR_INT_MASK 0x0007ff00 176 #else 177 #define CR_INT_MASK 0x003fff00 178 #endif 179 180 /* 181 * Config register. 182 */ 183 184 #define CFGR_CCA_MASK 0x00000007 185 #define CFGR_CU 0x00000008 186 #define CFGR_ICE 0x0000000200000000 187 #define CFGR_SMM 0x0000000400000000 188 189 /* 190 * Location of exception vectors. 191 */ 192 193 #ifdef CPU_R8000 194 #define RESET_EXC_VEC PHYS_TO_XKPHYS(0x1fc00000, CCA_NC) 195 /* all the others are relative to COP_0_TRAPBASE */ 196 /* #define UTLB_MISS_EXC_VEC 0x00000000 */ 197 /* #define KV1TLB_MISS_EXC_VEC 0x00000400 */ 198 /* #define KV0TLB_MISS_EXC_VEC 0x00000800 */ 199 /* #define GEN_EXC_VEC 0x00000c00 */ 200 #else 201 #define RESET_EXC_VEC (CKSEG1_BASE + 0x1fc00000) 202 #define TLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000000) 203 #define XTLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000080) 204 #define CACHE_ERR_EXC_VEC (CKSEG1_BASE + 0x00000100) 205 #define GEN_EXC_VEC (CKSEG1_BASE + 0x00000180) 206 #endif 207 208 /* 209 * Coprocessor 0 registers 210 */ 211 212 /* Common subset */ 213 #define COP_0_COUNT $9 214 #define COP_0_TLB_HI $10 215 #define COP_0_STATUS_REG $12 216 #define COP_0_CAUSE_REG $13 217 #define COP_0_EXC_PC $14 218 #define COP_0_PRID $15 219 #define COP_0_CONFIG $16 220 221 /* MIPS64 release 2 */ 222 #define COP_0_USERLOCAL $4, 2 223 #define COP_0_TLB_PG_GRAIN $5, 1 224 #define COP_0_EBASE $15, 1 225 226 /* R4000/5000/10000 */ 227 #define COP_0_TLB_INDEX $0 228 #define COP_0_TLB_RANDOM $1 229 #define COP_0_TLB_LO0 $2 230 #define COP_0_TLB_LO1 $3 231 #define COP_0_TLB_CONTEXT $4 232 #define COP_0_TLB_PG_MASK $5 233 #define COP_0_TLB_WIRED $6 234 #define COP_0_BAD_VADDR $8 235 #define COP_0_COMPARE $11 236 #define COP_0_LLADDR $17 237 #define COP_0_WATCH_LO $18 238 #define COP_0_WATCH_HI $19 239 #define COP_0_TLB_XCONTEXT $20 240 #define COP_0_ECC $26 241 #define COP_0_CACHE_ERR $27 242 #define COP_0_TAG_LO $28 243 #define COP_0_TAG_HI $29 244 #define COP_0_ERROR_PC $30 245 246 /* R8000 specific */ 247 #define COP_0_TLB_SET $0 248 #define COP_0_TLB_LO $2 249 #define COP_0_UBASE $4 250 #define COP_0_SHIFTAMT $5 251 #define COP_0_TRAPBASE $6 252 #define COP_0_BAD_PADDR $7 253 #define COP_0_VADDR $8 254 #define COP_0_WORK0 $18 255 #define COP_0_WORK1 $19 256 #define COP_0_PBASE $20 257 #define COP_0_GBASE $21 258 #define COP_0_TFP_TLB_WIRED $24 259 #define COP_0_DCACHE $28 260 #define COP_0_ICACHE $29 261 262 /* RM7000 specific */ 263 #define COP_0_WATCH_1 $18 264 #define COP_0_WATCH_2 $19 265 #define COP_0_WATCH_M $24 266 #define COP_0_PC_COUNT $25 267 #define COP_0_PC_CTRL $22 268 269 #define COP_0_ICR $20 /* Use cfc0/ctc0 to access */ 270 271 /* R10000 specific */ 272 #define COP_0_TLB_FR_MASK $21 273 274 /* Loongson-2 specific */ 275 #define COP_0_DIAG $22 276 277 /* Octeon specific */ 278 #define COP_0_CVMCTL $9, 7 279 #define COP_0_CVMMEMCTL $11, 7 280 281 /* 282 * COP_0_COUNT speed divider. 283 */ 284 #if defined(CPU_OCTEON) || defined(CPU_R8000) 285 #define CP0_CYCLE_DIVIDER 1 286 #else 287 #define CP0_CYCLE_DIVIDER 2 288 #endif 289 290 /* 291 * The floating point version and status registers. 292 */ 293 #define FPC_ID $0 294 #define FPC_CSR $31 295 296 /* 297 * Config1 register 298 */ 299 #define CONFIG1_M 0x80000000u 300 #define CONFIG1_MMUSize1 0x7e000000u 301 #define CONFIG1_MMUSize1_SHIFT 25 302 #define CONFIG1_IS 0x01c00000u 303 #define CONFIG1_IS_SHIFT 22 304 #define CONFIG1_IL 0x00380000u 305 #define CONFIG1_IL_SHIFT 19 306 #define CONFIG1_IA 0x00070000u 307 #define CONFIG1_IA_SHIFT 16 308 #define CONFIG1_DS 0x0000e000u 309 #define CONFIG1_DS_SHIFT 13 310 #define CONFIG1_DL 0x00001c00u 311 #define CONFIG1_DL_SHIFT 10 312 #define CONFIG1_DA 0x00000380u 313 #define CONFIG1_DA_SHIFT 7 314 #define CONFIG1_C2 0x00000040u 315 #define CONFIG1_MD 0x00000020u 316 #define CONFIG1_PC 0x00000010u 317 #define CONFIG1_WR 0x00000008u 318 #define CONFIG1_CA 0x00000004u 319 #define CONFIG1_EP 0x00000002u 320 #define CONFIG1_FP 0x00000001u 321 322 /* 323 * Config3 register 324 */ 325 #define CONFIG3_M 0x80000000 326 #define CONFIG3_BPG 0x40000000 327 #define CONFIG3_CMGCR 0x20000000 328 #define CONFIG3_IPLW 0x00600000 329 #define CONFIG3_MMAR 0x001c0000 330 #define CONFIG3_MCU 0x00020000 331 #define CONFIG3_ISAOnExc 0x00010000 332 #define CONFIG3_ISA 0x0000c000 333 #define CONFIG3_ULRI 0x00002000 334 #define CONFIG3_RXI 0x00001000 335 #define CONFIG3_DSP2P 0x00000800 336 #define CONFIG3_DSPP 0x00000400 337 #define CONFIG3_CTXTC 0x00000200 338 #define CONFIG3_ITL 0x00000100 339 #define CONFIG3_LPA 0x00000080 340 #define CONFIG3_VEIC 0x00000040 341 #define CONFIG3_VInt 0x00000020 342 #define CONFIG3_SP 0x00000010 343 #define CONFIG3_CDMM 0x00000008 344 #define CONFIG3_MT 0x00000004 345 #define CONFIG3_SM 0x00000002 346 #define CONFIG3_TL 0x00000001 347 348 /* 349 * Config4 register 350 */ 351 #define CONFIG4_M 0x80000000u 352 #define CONFIG4_IE 0x60000000u 353 #define CONFIG4_AE 0x10000000u 354 #define CONFIG4_VTLBSizeExt 0x0f000000u /* when MMUExtDef=3 */ 355 #define CONFIG4_KScrExist 0x00ff0000u 356 #define CONFIG4_MMUExtDef 0x0000c000u 357 #define CONFIG4_MMUExtDef_SHIFT 14 358 #define CONFIG4_FTLBPageSize 0x00001f00u /* when MMUExtDef=2 or 3 */ 359 #define CONFIG4_FTLBWays 0x000000f0u /* when MMUExtDef=2 or 3 */ 360 #define CONFIG4_FTLBSets 0x0000000fu /* when MMUExtDef=2 or 3 */ 361 #define CONFIG4_MMUSizeExt 0x000000ffu /* when MMUExtDef=1 */ 362 363 /* 364 * PageGrain register 365 */ 366 #define PGRAIN_RIE 0x80000000 367 #define PGRAIN_XIE 0x40000000 368 #define PGRAIN_ELPA 0x20000000 369 #define PGRAIN_ESP 0x10000000 370 #define PGRAIN_IEC 0x08000000 371 372 /* 373 * HWREna register 374 */ 375 #define HWRENA_ULR 0x20000000u 376 377 #endif /* _KERNEL || _STANDALONE */ 378 379 #endif /* !_MIPS64_CPUREGS_H_ */ 380