1 /* $OpenBSD: mips_cpu.h,v 1.4 2016/08/14 08:23:52 visa Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 */ 44 45 #ifndef _MIPS64_CPUREGS_H_ 46 #define _MIPS64_CPUREGS_H_ 47 48 #if defined(_KERNEL) || defined(_STANDALONE) 49 50 /* 51 * Status register. 52 */ 53 54 #define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */ 55 #define SR_COP_0_BIT 0x10000000 56 #define SR_COP_1_BIT 0x20000000 57 #define SR_RP 0x08000000 58 #define SR_FR_32 0x04000000 59 #define SR_RE 0x02000000 60 #define SR_DSD 0x01000000 /* Only on R12000 */ 61 #define SR_BOOT_EXC_VEC 0x00400000 62 #define SR_TLB_SHUTDOWN 0x00200000 63 #define SR_SOFT_RESET 0x00100000 64 #define SR_DIAG_CH 0x00040000 65 #define SR_DIAG_CE 0x00020000 66 #define SR_DIAG_DE 0x00010000 67 #define SR_KX 0x00000080 68 #define SR_SX 0x00000040 69 #define SR_UX 0x00000020 70 #define SR_ERL 0x00000004 71 #define SR_EXL 0x00000002 72 #define SR_INT_ENAB 0x00000001 73 74 #define SOFT_INT_MASK_0 0x00000100 75 #define SOFT_INT_MASK_1 0x00000200 76 #define SR_INT_MASK_0 0x00000400 77 #define SR_INT_MASK_1 0x00000800 78 #define SR_INT_MASK_2 0x00001000 79 #define SR_INT_MASK_3 0x00002000 80 #define SR_INT_MASK_4 0x00004000 81 #define SR_INT_MASK_5 0x00008000 82 83 /* R8000-specific bits */ 84 #define SR_SERIALIZE_FPU 0x0000010000000000 85 #define SR_KPGSZ_SHIFT 36 86 #define SR_UPGSZ_SHIFT 32 87 #define SR_PGSZ_4K 0 88 #define SR_PGSZ_8K 1 89 #define SR_PGSZ_16K 2 90 #define SR_PGSZ_64K 3 91 #define SR_PGSZ_1M 4 92 #define SR_PGSZ_4M 5 93 #define SR_PGSZ_16M 6 94 #define SR_PGSZ_MASK 0x0f 95 96 #define SR_INT_MASK_6 0x00010000 97 #define SR_INT_MASK_7 0x00020000 98 #define SR_INT_MASK_8 0x00040000 99 100 #ifdef CPU_R8000 101 #define SR_XX 0x00000040 102 #define SR_KSU_MASK 0x00000010 103 #define SR_KSU_KERNEL 0x00000000 104 #define SR_INT_MASK 0x0007ff00 105 #else 106 #define SR_XX 0x80000000 107 #define SR_KSU_MASK 0x00000018 108 #define SR_KSU_SUPER 0x00000008 109 #define SR_KSU_KERNEL 0x00000000 110 #define SR_INT_MASK 0x0000ff00 111 #endif 112 /* SR_KSU_USER is in <mips64/cpu.h> for CLKF_USERMODE() */ 113 #ifndef SR_KSU_USER 114 #define SR_KSU_USER 0x00000010 115 #endif 116 117 /* 118 * Interrupt control register in RM7000. Expansion of interrupts. 119 */ 120 121 #define IC_INT_MASK 0x00003f00 /* Two msb reserved */ 122 #define IC_INT_MASK_6 0x00000100 123 #define IC_INT_MASK_7 0x00000200 124 #define IC_INT_MASK_8 0x00000400 125 #define IC_INT_MASK_9 0x00000800 126 #define IC_INT_TIMR 0x00001000 /* 12 Timer */ 127 #define IC_INT_PERF 0x00002000 /* 13 Performance counter */ 128 #define IC_INT_TE 0x00000080 /* Timer on INT11 */ 129 130 #define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 131 132 /* 133 * Cause register. 134 */ 135 136 #ifdef CPU_R8000 137 #define CR_BR_DELAY 0x8000000000000000 138 #define CR_EXC_CODE 0x000000f8 139 #define CR_EXC_CODE_SHIFT 3 140 #define CR_COP_ERR 0x10000000 141 #else 142 #define CR_BR_DELAY 0x80000000 143 #define CR_EXC_CODE 0x0000007c 144 #define CR_EXC_CODE_SHIFT 2 145 #define CR_COP_ERR 0x30000000 146 #endif 147 #define CR_COP1_ERR 0x10000000 148 #define CR_COP2_ERR 0x20000000 149 #define CR_COP3_ERR 0x20000000 150 #define CR_INT_SOFT0 0x00000100 151 #define CR_INT_SOFT1 0x00000200 152 #define CR_INT_0 0x00000400 153 #define CR_INT_1 0x00000800 154 #define CR_INT_2 0x00001000 155 #define CR_INT_3 0x00002000 156 #define CR_INT_4 0x00004000 157 #define CR_INT_5 0x00008000 158 /* Following on RM7000 and R8000 */ 159 #define CR_INT_6 0x00010000 160 #define CR_INT_7 0x00020000 161 #define CR_INT_8 0x00040000 162 /* Following on RM7000 */ 163 #define CR_INT_9 0x00080000 164 #define CR_INT_HARD 0x000ffc00 165 #define CR_INT_TIMR 0x00100000 /* 12 Timer */ 166 #define CR_INT_PERF 0x00200000 /* 13 Performance counter */ 167 /* R8000 specific */ 168 #define CR_FPE 0x01000000 169 #define CR_VCE 0x02000000 170 #define CR_BERR 0x04000000 171 #define CR_NMI 0x08000000 172 173 #ifdef CPU_R8000 174 #define CR_INT_MASK 0x0007ff00 175 #else 176 #define CR_INT_MASK 0x003fff00 177 #endif 178 179 /* 180 * Config register. 181 */ 182 183 #define CFGR_CCA_MASK 0x00000007 184 #define CFGR_CU 0x00000008 185 #define CFGR_ICE 0x0000000200000000 186 #define CFGR_SMM 0x0000000400000000 187 188 /* 189 * Location of exception vectors. 190 */ 191 192 #ifdef CPU_R8000 193 #define RESET_EXC_VEC PHYS_TO_XKPHYS(0x1fc00000, CCA_NC) 194 /* all the others are relative to COP_0_TRAPBASE */ 195 /* #define UTLB_MISS_EXC_VEC 0x00000000 */ 196 /* #define KV1TLB_MISS_EXC_VEC 0x00000400 */ 197 /* #define KV0TLB_MISS_EXC_VEC 0x00000800 */ 198 /* #define GEN_EXC_VEC 0x00000c00 */ 199 #else 200 #define RESET_EXC_VEC (CKSEG1_BASE + 0x1fc00000) 201 #define TLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000000) 202 #define XTLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000080) 203 #define CACHE_ERR_EXC_VEC (CKSEG1_BASE + 0x00000100) 204 #define GEN_EXC_VEC (CKSEG1_BASE + 0x00000180) 205 #endif 206 207 /* 208 * Coprocessor 0 registers 209 */ 210 211 /* Common subset */ 212 #define COP_0_COUNT $9 213 #define COP_0_TLB_HI $10 214 #define COP_0_STATUS_REG $12 215 #define COP_0_CAUSE_REG $13 216 #define COP_0_EXC_PC $14 217 #define COP_0_PRID $15 218 #define COP_0_CONFIG $16 219 220 /* MIPS64 release 2 */ 221 #define COP_0_TLB_PG_GRAIN $5, 1 222 #define COP_0_EBASE $15, 1 223 224 /* R4000/5000/10000 */ 225 #define COP_0_TLB_INDEX $0 226 #define COP_0_TLB_RANDOM $1 227 #define COP_0_TLB_LO0 $2 228 #define COP_0_TLB_LO1 $3 229 #define COP_0_TLB_CONTEXT $4 230 #define COP_0_TLB_PG_MASK $5 231 #define COP_0_TLB_WIRED $6 232 #define COP_0_BAD_VADDR $8 233 #define COP_0_COMPARE $11 234 #define COP_0_LLADDR $17 235 #define COP_0_WATCH_LO $18 236 #define COP_0_WATCH_HI $19 237 #define COP_0_TLB_XCONTEXT $20 238 #define COP_0_ECC $26 239 #define COP_0_CACHE_ERR $27 240 #define COP_0_TAG_LO $28 241 #define COP_0_TAG_HI $29 242 #define COP_0_ERROR_PC $30 243 244 /* R8000 specific */ 245 #define COP_0_TLB_SET $0 246 #define COP_0_TLB_LO $2 247 #define COP_0_UBASE $4 248 #define COP_0_SHIFTAMT $5 249 #define COP_0_TRAPBASE $6 250 #define COP_0_BAD_PADDR $7 251 #define COP_0_VADDR $8 252 #define COP_0_WORK0 $18 253 #define COP_0_WORK1 $19 254 #define COP_0_PBASE $20 255 #define COP_0_GBASE $21 256 #define COP_0_TFP_TLB_WIRED $24 257 #define COP_0_DCACHE $28 258 #define COP_0_ICACHE $29 259 260 /* RM7000 specific */ 261 #define COP_0_WATCH_1 $18 262 #define COP_0_WATCH_2 $19 263 #define COP_0_WATCH_M $24 264 #define COP_0_PC_COUNT $25 265 #define COP_0_PC_CTRL $22 266 267 #define COP_0_ICR $20 /* Use cfc0/ctc0 to access */ 268 269 /* R10000 specific */ 270 #define COP_0_TLB_FR_MASK $21 271 272 /* Loongson-2 specific */ 273 #define COP_0_DIAG $22 274 275 /* Octeon specific */ 276 #define COP_0_CVMCTL $9, 7 277 #define COP_0_CVMMEMCTL $11, 7 278 279 /* 280 * COP_0_COUNT speed divider. 281 */ 282 #if defined(CPU_OCTEON) || defined(CPU_R8000) 283 #define CP0_CYCLE_DIVIDER 1 284 #else 285 #define CP0_CYCLE_DIVIDER 2 286 #endif 287 288 /* 289 * The floating point version and status registers. 290 */ 291 #define FPC_ID $0 292 #define FPC_CSR $31 293 294 /* 295 * Config3 register 296 */ 297 #define CONFIG3_M 0x80000000 298 #define CONFIG3_BPG 0x40000000 299 #define CONFIG3_CMGCR 0x20000000 300 #define CONFIG3_IPLW 0x00600000 301 #define CONFIG3_MMAR 0x001c0000 302 #define CONFIG3_MCU 0x00020000 303 #define CONFIG3_ISAOnExc 0x00010000 304 #define CONFIG3_ISA 0x0000c000 305 #define CONFIG3_ULRI 0x00002000 306 #define CONFIG3_RXI 0x00001000 307 #define CONFIG3_DSP2P 0x00000800 308 #define CONFIG3_DSPP 0x00000400 309 #define CONFIG3_CTXTC 0x00000200 310 #define CONFIG3_ITL 0x00000100 311 #define CONFIG3_LPA 0x00000080 312 #define CONFIG3_VEIC 0x00000040 313 #define CONFIG3_VInt 0x00000020 314 #define CONFIG3_SP 0x00000010 315 #define CONFIG3_CDMM 0x00000008 316 #define CONFIG3_MT 0x00000004 317 #define CONFIG3_SM 0x00000002 318 #define CONFIG3_TL 0x00000001 319 320 /* 321 * PageGrain register 322 */ 323 #define PGRAIN_RIE 0x80000000 324 #define PGRAIN_XIE 0x40000000 325 #define PGRAIN_ELPA 0x20000000 326 #define PGRAIN_ESP 0x10000000 327 #define PGRAIN_IEC 0x08000000 328 329 #endif /* _KERNEL || _STANDALONE */ 330 331 #endif /* !_MIPS64_CPUREGS_H_ */ 332