1 /* 2 * THIS FILE IS AUTOMATICALLY GENERATED 3 * DONT EDIT THIS FILE 4 */ 5 6 /* $OpenBSD: cn30xxbootbusreg.h,v 1.3 2022/12/28 01:39:21 yasuoka Exp $ */ 7 8 /* 9 * Copyright (c) 2007 Internet Initiative Japan, Inc. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Cavium Networks OCTEON CN30XX Hardware Reference Manual 36 * CN30XX-HM-1.0 37 * 12.8 Boot-Bus Registers 38 */ 39 40 #ifndef _CN30XXBOOTBUSREG_H_ 41 #define _CN30XXBOOTBUSREG_H_ 42 43 /* ---- register addresses */ 44 45 #define MIO_BOOT_REG_CFG0 0x0001180000000000ULL 46 #define MIO_BOOT_REG_CFG1 0x0001180000000008ULL 47 #define MIO_BOOT_REG_CFG2 0x0001180000000010ULL 48 #define MIO_BOOT_REG_CFG3 0x0001180000000018ULL 49 #define MIO_BOOT_REG_CFG4 0x0001180000000020ULL 50 #define MIO_BOOT_REG_CFG5 0x0001180000000028ULL 51 #define MIO_BOOT_REG_CFG6 0x0001180000000030ULL 52 #define MIO_BOOT_REG_CFG7 0x0001180000000038ULL 53 #define MIO_BOOT_REG_TIM0 0x0001180000000040ULL 54 #define MIO_BOOT_REG_TIM1 0x0001180000000048ULL 55 #define MIO_BOOT_REG_TIM2 0x0001180000000050ULL 56 #define MIO_BOOT_REG_TIM3 0x0001180000000058ULL 57 #define MIO_BOOT_REG_TIM4 0x0001180000000060ULL 58 #define MIO_BOOT_REG_TIM5 0x0001180000000068ULL 59 #define MIO_BOOT_REG_TIM6 0x0001180000000070ULL 60 #define MIO_BOOT_REG_TIM7 0x0001180000000078ULL 61 #define MIO_BOOT_LOC_CFG0 0x0001180000000080ULL 62 #define MIO_BOOT_LOC_CFG1 0x0001180000000088ULL 63 #define MIO_BOOT_LOC_ADR 0x0001180000000090ULL 64 #define MIO_BOOT_LOC_DAT 0x0001180000000098ULL 65 #define MIO_BOOT_ERR 0x00011800000000a0ULL 66 #define MIO_BOOT_INT 0x00011800000000a8ULL 67 #define MIO_BOOT_THR 0x00011800000000b0ULL 68 #define MIO_BOOT_BIST_STAT 0x00011800000000f8ULL 69 70 /* ---- register bits */ 71 72 #define MIO_BOOT_REG_CFGN_XXX_63_37 0xffffffe000000000ULL 73 #define MIO_BOOT_REG_CFGN_SAM 0x0000001000000000ULL 74 #define MIO_BOOT_REG_CFGN_WE_EXT 0x0000000c00000000ULL 75 #define MIO_BOOT_REG_CFGN_OE_EXT 0x0000000300000000ULL 76 #define MIO_BOOT_REG_CFGN_EN 0x0000000080000000ULL 77 #define MIO_BOOT_REG_CFGN_OR 0x0000000040000000ULL 78 #define MIO_BOOT_REG_CFGN_ALE 0x0000000020000000ULL 79 #define MIO_BOOT_REG_CFGN_WIDTH 0x0000000010000000ULL 80 #define MIO_BOOT_REG_CFGN_SIZE 0x000000000fff0000ULL 81 #define MIO_BOOT_REG_CFGN_BASE 0x000000000000ffffULL 82 83 #define MIO_BOOT_REG_TIMN_PAGEM 0x8000000000000000ULL 84 #define MIO_BOOT_REG_TIMN_WAITM 0x4000000000000000ULL 85 #define MIO_BOOT_REG_TIMN_PAGES 0x3000000000000000ULL 86 #define MIO_BOOT_REG_TIMN_ALE 0x0fc0000000000000ULL 87 #define MIO_BOOT_REG_TIMN_PAGE 0x003f000000000000ULL 88 #define MIO_BOOT_REG_TIMN_WAIT 0x0000fc0000000000ULL 89 #define MIO_BOOT_REG_TIMN_PAUSE 0x000003f000000000ULL 90 #define MIO_BOOT_REG_TIMN_WR_HLD 0x0000000fc0000000ULL 91 #define MIO_BOOT_REG_TIMN_RD_HLD 0x000000003f000000ULL 92 #define MIO_BOOT_REG_TIMN_WE 0x0000000000fc0000ULL 93 #define MIO_BOOT_REG_TIMN_OE 0x000000000003f000ULL 94 #define MIO_BOOT_REG_TIMN_CE 0x0000000000000fc0ULL 95 #define MIO_BOOT_REG_TIMN_ADR 0x000000000000003fULL 96 97 #define MIO_BOOT_LOC_CFGN_XXX_63_32 0xffffffff00000000ULL 98 #define MIO_BOOT_LOC_CFGN_EN 0x0000000080000000ULL 99 #define MIO_BOOT_LOC_CFGN_XXX_30_28 0x0000000070000000ULL 100 #define MIO_BOOT_LOC_CFGN_BASE 0x000000000ffffff8ULL 101 #define MIO_BOOT_LOC_CFGN_XXX_2_0 0x0000000000000007ULL 102 103 #define MIO_BOOT_LOC_ADR_XXX_63_8 0xffffffffffffff00ULL 104 #define MIO_BOOT_LOC_ADR_ADR 0x00000000000000f8ULL 105 #define MIO_BOOT_LOC_ADR_XXX_2_0 0x0000000000000007ULL 106 107 #define MIO_BOOT_ERR_XXX_63_2 0xfffffffffffffffcULL 108 #define MIO_BOOT_ERR_WAIT_ERR 0x0000000000000002ULL 109 #define MIO_BOOT_ERR_ADR_ERR 0x0000000000000001ULL 110 111 #define MIO_BOOT_INT_XXX_63_2 0xfffffffffffffffcULL 112 #define MIO_BOOT_INT_WAIT_INT 0x0000000000000002ULL 113 #define MIO_BOOT_INT_ADR_INT 0x0000000000000001ULL 114 115 #define MIO_BOOT_THR_XXX_63_14 0xffffffffffffc000ULL 116 #define MIO_BOOT_THR_FIF_CNT 0x0000000000003f00ULL 117 #define MIO_BOOT_THR_XXX_7_6 0x00000000000000c0ULL 118 #define MIO_BOOT_THR_FIF_THR 0x000000000000003fULL 119 120 #define MIO_BOOT_BIST_STAT_XXX_63_4 0xfffffffffffffff0ULL 121 #define MIO_BOOT_BIST_STAT_NCBO_1 0x0000000000000008ULL 122 #define MIO_BOOT_BIST_STAT_NCBO_0 0x0000000000000004ULL 123 #define MIO_BOOT_BIST_STAT_LOC 0x0000000000000002ULL 124 #define MIO_BOOT_BIST_STAT_NCBI 0x0000000000000001ULL 125 126 /* ---- bus_space */ 127 128 #define MIO_BOOT_REG_CFG0_OFFSET 0x0000 129 #define MIO_BOOT_REG_CFG1_OFFSET 0x0008 130 #define MIO_BOOT_REG_CFG2_OFFSET 0x0010 131 #define MIO_BOOT_REG_CFG3_OFFSET 0x0018 132 #define MIO_BOOT_REG_CFG4_OFFSET 0x0020 133 #define MIO_BOOT_REG_CFG5_OFFSET 0x0028 134 #define MIO_BOOT_REG_CFG6_OFFSET 0x0030 135 #define MIO_BOOT_REG_CFG7_OFFSET 0x0038 136 #define MIO_BOOT_REG_TIM0_OFFSET 0x0040 137 #define MIO_BOOT_REG_TIM1_OFFSET 0x0048 138 #define MIO_BOOT_REG_TIM2_OFFSET 0x0050 139 #define MIO_BOOT_REG_TIM3_OFFSET 0x0058 140 #define MIO_BOOT_REG_TIM4_OFFSET 0x0060 141 #define MIO_BOOT_REG_TIM5_OFFSET 0x0068 142 #define MIO_BOOT_REG_TIM6_OFFSET 0x0070 143 #define MIO_BOOT_REG_TIM7_OFFSET 0x0078 144 #define MIO_BOOT_LOC_CFG0_OFFSET 0x0080 145 #define MIO_BOOT_LOC_CFG1_OFFSET 0x0088 146 #define MIO_BOOT_LOC_ADR_OFFSET 0x0090 147 #define MIO_BOOT_LOC_DAT_OFFSET 0x0098 148 #define MIO_BOOT_ERR_OFFSET 0x00a0 149 #define MIO_BOOT_INT_OFFSET 0x00a8 150 #define MIO_BOOT_THR_OFFSET 0x00b0 151 #define MIO_BOOT_BIST_STAT_OFFSET 0x00f8 152 153 #endif /* _CN30XXBOOTBUSREG_H_ */ 154