1 /* 2 * THIS FILE IS AUTOMATICALLY GENERATED 3 * DONT EDIT THIS FILE 4 */ 5 6 /* $OpenBSD: cn30xxciureg.h,v 1.3 2022/12/28 01:39:21 yasuoka Exp $ */ 7 8 /* 9 * Copyright (c) 2007 Internet Initiative Japan, Inc. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Cavium Networks OCTEON CN30XX Hardware Reference Manual 36 * CN30XX-HM-1.0 37 * 11.10 CIU Registers 38 */ 39 40 #ifndef _CN30XXCIUREG_H_ 41 #define _CN30XXCIUREG_H_ 42 43 /* ---- register addresses */ 44 45 #define CIU_INT0_SUM0 0x0001070000000000ULL 46 #define CIU_INT1_SUM0 0x0001070000000008ULL 47 #define CIU_INT2_SUM0 0x0001070000000010ULL 48 #define CIU_INT3_SUM0 0x0001070000000018ULL 49 #define CIU_INT32_SUM0 0x0001070000000100ULL 50 #define CIU_INT_SUM1 0x0001070000000008ULL 51 #define CIU_INT0_EN0 0x0001070000000200ULL 52 #define CIU_INT1_EN0 0x0001070000000210ULL 53 #define CIU_INT2_EN0 0x0001070000000220ULL 54 #define CIU_INT3_EN0 0x0001070000000230ULL 55 #define CIU_INT32_EN0 0x0001070000000400ULL 56 #define CIU_INT0_EN1 0x0001070000000208ULL 57 #define CIU_INT1_EN1 0x0001070000000218ULL 58 #define CIU_INT2_EN1 0x0001070000000228ULL 59 #define CIU_INT3_EN1 0x0001070000000238ULL 60 #define CIU_INT32_EN1 0x0001070000000408ULL 61 #define CIU_TIM0 0x0001070000000480ULL 62 #define CIU_TIM1 0x0001070000000488ULL 63 #define CIU_TIM2 0x0001070000000490ULL 64 #define CIU_TIM3 0x0001070000000498ULL 65 #define CIU_WDOG0 0x0001070000000500ULL 66 #define CIU_WDOG1 0x0001070000000508ULL 67 #define CIU_PP_POKE0 0x0001070000000580ULL 68 #define CIU_PP_POKE1 0x0001070000000588ULL 69 #define CIU_MBOX_SET0 0x0001070000000600ULL 70 #define CIU_MBOX_SET1 0x0001070000000600ULL 71 #define CIU_MBOX_CLR0 0x0001070000000680ULL 72 #define CIU_MBOX_CLR1 0x0001070000000680ULL 73 #define CIU_PP_RST 0x0001070000000700ULL 74 #define CIU_PP_DBG 0x0001070000000708ULL 75 #define CIU_GSTOP 0x0001070000000710ULL 76 #define CIU_NMI 0x0001070000000718ULL 77 #define CIU_DINT 0x0001070000000720ULL 78 #define CIU_FUSE 0x0001070000000728ULL 79 #define CIU_BIST 0x0001070000000730ULL 80 #define CIU_SOFT_BIST 0x0001070000000738ULL 81 #define CIU_SOFT_RST 0x0001070000000740ULL 82 #define CIU_SOFT_PRST 0x0001070000000748ULL 83 #define CIU_PCI_INTA 0x0001070000000750ULL 84 85 #define CIU_INT0_SUM0_OFFSET 0x0000 86 #define CIU_INT1_SUM0_OFFSET 0x0008 87 #define CIU_INT2_SUM0_OFFSET 0x0010 88 #define CIU_INT3_SUM0_OFFSET 0x0018 89 #define CIU_INT32_SUM0_OFFSET 0x0100 90 #define CIU_INT_SUM1_OFFSET 0x0008 91 #define CIU_INT0_EN0_OFFSET 0x0200 92 #define CIU_INT1_EN0_OFFSET 0x0210 93 #define CIU_INT2_EN0_OFFSET 0x0220 94 #define CIU_INT3_EN0_OFFSET 0x0230 95 #define CIU_INT32_EN0_OFFSET 0x0400 96 #define CIU_INT0_EN1_OFFSET 0x0208 97 #define CIU_INT1_EN1_OFFSET 0x0218 98 #define CIU_INT2_EN1_OFFSET 0x0228 99 #define CIU_INT3_EN1_OFFSET 0x0238 100 #define CIU_INT32_EN1_OFFSET 0x0408 101 #define CIU_TIM0_OFFSET 0x0480 102 #define CIU_TIM1_OFFSET 0x0488 103 #define CIU_TIM2_OFFSET 0x0490 104 #define CIU_TIM3_OFFSET 0x0498 105 #define CIU_WDOG0_OFFSET 0x0500 106 #define CIU_WDOG1_OFFSET 0x0508 107 #define CIU_PP_POKE0_OFFSET 0x0580 108 #define CIU_PP_POKE1_OFFSET 0x0588 109 #define CIU_MBOX_SET0_OFFSET 0x0600 110 #define CIU_MBOX_SET1_OFFSET 0x0608 111 #define CIU_MBOX_CLR0_OFFSET 0x0680 112 #define CIU_MBOX_CLR1_OFFSET 0x0688 113 #define CIU_PP_RST_OFFSET 0x0700 114 #define CIU_PP_DBG_OFFSET 0x0708 115 #define CIU_GSTOP_OFFSET 0x0710 116 #define CIU_NMI_OFFSET 0x0718 117 #define CIU_DINT_OFFSET 0x0720 118 #define CIU_FUSE_OFFSET 0x0728 119 #define CIU_BIST_OFFSET 0x0730 120 #define CIU_SOFT_BIST_OFFSET 0x0738 121 #define CIU_SOFT_RST_OFFSET 0x0740 122 #define CIU_SOFT_PRST_OFFSET 0x0748 123 #define CIU_PCI_INTA_OFFSET 0x0750 124 125 /* ---- register bits */ 126 127 /* ``interrupt bits'' shift values */ 128 129 #define _CIU_INT_XXX_63_SHIFT 0x3f 130 #define _CIU_INT_XXX_62_SHIFT 0x3e 131 #define _CIU_INT_XXX_61_SHIFT 0x3d 132 #define _CIU_INT_XXX_60_SHIFT 0x3c 133 #define _CIU_INT_XXX_59_SHIFT 0x3b 134 #define _CIU_INT_MPI_SHIFT 0x3a 135 #define _CIU_INT_PCM_SHIFT 0x39 136 #define _CIU_INT_USB_SHIFT 0x38 137 #define _CIU_INT_TIMER_3_SHIFT 0x37 138 #define _CIU_INT_TIMER_2_SHIFT 0x36 139 #define _CIU_INT_TIMER_1_SHIFT 0x35 140 #define _CIU_INT_TIMER_0_SHIFT 0x34 141 #define _CIU_INT_XXX_51_SHIFT 0x33 142 #define _CIU_INT_IPD_DRP_SHIFT 0x32 143 #define _CIU_INT_GMX_DRP_SHIFT 0x30 144 #define _CIU_INT_TRACE_SHIFT 0x2f 145 #define _CIU_INT_RML_SHIFT 0x2e 146 #define _CIU_INT_TWSI_SHIFT 0x2d 147 #define _CIU_INT_WDOG_SUM_SHIFT 0x2c 148 #define _CIU_INT_PCI_MSI_63_48_SHIFT 0x2b 149 #define _CIU_INT_PCI_MSI_47_32_SHIFT 0x2a 150 #define _CIU_INT_PCI_MSI_31_16_SHIFT 0x29 151 #define _CIU_INT_PCI_MSI_15_0_SHIFT 0x28 152 #define _CIU_INT_PCI_INT_D_SHIFT 0x27 153 #define _CIU_INT_PCI_INT_C_SHIFT 0x26 154 #define _CIU_INT_PCI_INT_B_SHIFT 0x25 155 #define _CIU_INT_PCI_INT_A_SHIFT 0x24 156 #define _CIU_INT_UART_1_SHIFT 0x23 157 #define _CIU_INT_UART_0_SHIFT 0x22 158 #define _CIU_INT_MBOX_31_16_SHIFT 0x21 159 #define _CIU_INT_MBOX_15_0_SHIFT 0x20 160 #define _CIU_INT_GPIO_15_SHIFT 0x1f 161 #define _CIU_INT_GPIO_14_SHIFT 0x1e 162 #define _CIU_INT_GPIO_13_SHIFT 0x1d 163 #define _CIU_INT_GPIO_12_SHIFT 0x1c 164 #define _CIU_INT_GPIO_11_SHIFT 0x1b 165 #define _CIU_INT_GPIO_10_SHIFT 0x1a 166 #define _CIU_INT_GPIO_9_SHIFT 0x19 167 #define _CIU_INT_GPIO_8_SHIFT 0x18 168 #define _CIU_INT_GPIO_7_SHIFT 0x17 169 #define _CIU_INT_GPIO_6_SHIFT 0x16 170 #define _CIU_INT_GPIO_5_SHIFT 0x15 171 #define _CIU_INT_GPIO_4_SHIFT 0x14 172 #define _CIU_INT_GPIO_3_SHIFT 0x13 173 #define _CIU_INT_GPIO_2_SHIFT 0x12 174 #define _CIU_INT_GPIO_1_SHIFT 0x11 175 #define _CIU_INT_GPIO_0_SHIFT 0x10 176 #define _CIU_INT_WORKQ_15_SHIFT 0x0f 177 #define _CIU_INT_WORKQ_14_SHIFT 0x0e 178 #define _CIU_INT_WORKQ_13_SHIFT 0x0d 179 #define _CIU_INT_WORKQ_12_SHIFT 0x0c 180 #define _CIU_INT_WORKQ_11_SHIFT 0x0b 181 #define _CIU_INT_WORKQ_10_SHIFT 0x0a 182 #define _CIU_INT_WORKQ_9_SHIFT 0x09 183 #define _CIU_INT_WORKQ_8_SHIFT 0x08 184 #define _CIU_INT_WORKQ_7_SHIFT 0x07 185 #define _CIU_INT_WORKQ_6_SHIFT 0x06 186 #define _CIU_INT_WORKQ_5_SHIFT 0x05 187 #define _CIU_INT_WORKQ_4_SHIFT 0x04 188 #define _CIU_INT_WORKQ_3_SHIFT 0x03 189 #define _CIU_INT_WORKQ_2_SHIFT 0x02 190 #define _CIU_INT_WORKQ_1_SHIFT 0x01 191 192 #define CIU_INTX_SUM0_XXX_63_59 0xf800000000000000ULL 193 #define CIU_INTX_SUM0_MPI 0x0400000000000000ULL 194 #define CIU_INTX_SUM0_PCM 0x0200000000000000ULL 195 #define CIU_INTX_SUM0_USB 0x0100000000000000ULL 196 #define CIU_INTX_SUM0_TIMER 0x00f0000000000000ULL 197 #define CIU_INTX_SUM0_TIMER_3 0x0080000000000000ULL 198 #define CIU_INTX_SUM0_TIMER_2 0x0040000000000000ULL 199 #define CIU_INTX_SUM0_TIMER_1 0x0020000000000000ULL 200 #define CIU_INTX_SUM0_TIMER_0 0x0010000000000000ULL 201 #define CIU_INTX_SUM0_XXX_51 0x0008000000000000ULL 202 #define CIU_INTX_SUM0_IPD_DRP 0x0004000000000000ULL 203 #define CIU_INTX_SUM0_XXX_49 0x0002000000000000ULL 204 #define CIU_INTX_SUM0_GMX_DRP 0x0001000000000000ULL 205 #define CIU_INTX_SUM0_TRACE 0x0000800000000000ULL 206 #define CIU_INTX_SUM0_RML 0x0000400000000000ULL 207 #define CIU_INTX_SUM0_TWSI 0x0000200000000000ULL 208 #define CIU_INTX_SUM0_WDOG_SUM 0x0000100000000000ULL 209 #define CIU_INTX_SUM0_PCI_MSI 0x00000f0000000000ULL 210 #define CIU_INTX_SUM0_PCI_MSI_63_48 0x0000080000000000ULL 211 #define CIU_INTX_SUM0_PCI_MSI_47_32 0x0000040000000000ULL 212 #define CIU_INTX_SUM0_PCI_MSI_31_16 0x0000020000000000ULL 213 #define CIU_INTX_SUM0_PCI_MSI_15_0 0x0000010000000000ULL 214 #define CIU_INTX_SUM0_PCI_INT 0x000000f000000000ULL 215 #define CIU_INTX_SUM0_PCI_INT_D 0x0000008000000000ULL 216 #define CIU_INTX_SUM0_PCI_INT_C 0x0000004000000000ULL 217 #define CIU_INTX_SUM0_PCI_INT_B 0x0000002000000000ULL 218 #define CIU_INTX_SUM0_PCI_INT_A 0x0000001000000000ULL 219 #define CIU_INTX_SUM0_UART 0x0000000c00000000ULL 220 #define CIU_INTX_SUM0_UART_1 0x0000000800000000ULL 221 #define CIU_INTX_SUM0_UART_0 0x0000000400000000ULL 222 #define CIU_INTX_SUM0_MBOX 0x0000000300000000ULL 223 #define CIU_INTX_SUM0_MBOX_31_16 0x0000000200000000ULL 224 #define CIU_INTX_SUM0_MBOX_15_0 0x0000000100000000ULL 225 #define CIU_INTX_SUM0_GPIO 0x00000000ffff0000ULL 226 #define CIU_INTX_SUM0_GPIO_15 0x0000000080000000ULL 227 #define CIU_INTX_SUM0_GPIO_14 0x0000000040000000ULL 228 #define CIU_INTX_SUM0_GPIO_13 0x0000000020000000ULL 229 #define CIU_INTX_SUM0_GPIO_12 0x0000000010000000ULL 230 #define CIU_INTX_SUM0_GPIO_11 0x0000000008000000ULL 231 #define CIU_INTX_SUM0_GPIO_10 0x0000000004000000ULL 232 #define CIU_INTX_SUM0_GPIO_9 0x0000000002000000ULL 233 #define CIU_INTX_SUM0_GPIO_8 0x0000000001000000ULL 234 #define CIU_INTX_SUM0_GPIO_7 0x0000000000800000ULL 235 #define CIU_INTX_SUM0_GPIO_6 0x0000000000400000ULL 236 #define CIU_INTX_SUM0_GPIO_5 0x0000000000200000ULL 237 #define CIU_INTX_SUM0_GPIO_4 0x0000000000100000ULL 238 #define CIU_INTX_SUM0_GPIO_3 0x0000000000080000ULL 239 #define CIU_INTX_SUM0_GPIO_2 0x0000000000040000ULL 240 #define CIU_INTX_SUM0_GPIO_1 0x0000000000020000ULL 241 #define CIU_INTX_SUM0_GPIO_0 0x0000000000010000ULL 242 #define CIU_INTX_SUM0_WORKQ 0x000000000000ffffULL 243 #define CIU_INTX_SUM0_WORKQ_15 0x0000000000008000ULL 244 #define CIU_INTX_SUM0_WORKQ_14 0x0000000000004000ULL 245 #define CIU_INTX_SUM0_WORKQ_13 0x0000000000002000ULL 246 #define CIU_INTX_SUM0_WORKQ_12 0x0000000000001000ULL 247 #define CIU_INTX_SUM0_WORKQ_11 0x0000000000000800ULL 248 #define CIU_INTX_SUM0_WORKQ_10 0x0000000000000400ULL 249 #define CIU_INTX_SUM0_WORKQ_9 0x0000000000000200ULL 250 #define CIU_INTX_SUM0_WORKQ_8 0x0000000000000100ULL 251 #define CIU_INTX_SUM0_WORKQ_7 0x0000000000000080ULL 252 #define CIU_INTX_SUM0_WORKQ_6 0x0000000000000040ULL 253 #define CIU_INTX_SUM0_WORKQ_5 0x0000000000000020ULL 254 #define CIU_INTX_SUM0_WORKQ_4 0x0000000000000010ULL 255 #define CIU_INTX_SUM0_WORKQ_3 0x0000000000000008ULL 256 #define CIU_INTX_SUM0_WORKQ_2 0x0000000000000004ULL 257 #define CIU_INTX_SUM0_WORKQ_1 0x0000000000000002ULL 258 #define CIU_INTX_SUM0_WORKQ_0 0x0000000000000001ULL 259 260 #define CIU_INT_SUM1_XXX_63_1 0xfffffffffffffffeULL 261 #define CIU_INT_SUM1_WDOG 0x0000000000000001ULL 262 263 #define CIU_INTX_EN0_XXX_63_59 0xf800000000000000ULL 264 #define CIU_INTX_EN0_MPI 0x0400000000000000ULL 265 #define CIU_INTX_EN0_PCM 0x0200000000000000ULL 266 #define CIU_INTX_EN0_USB 0x0100000000000000ULL 267 #define CIU_INTX_EN0_TIMER 0x00f0000000000000ULL 268 #define CIU_INTX_EN0_TIMER_3 0x0080000000000000ULL 269 #define CIU_INTX_EN0_TIMER_2 0x0040000000000000ULL 270 #define CIU_INTX_EN0_TIMER_1 0x0020000000000000ULL 271 #define CIU_INTX_EN0_TIMER_0 0x0010000000000000ULL 272 #define CIU_INTX_EN0_XXX_51 0x0008000000000000ULL 273 #define CIU_INTX_EN0_IPD_DRP 0x0004000000000000ULL 274 #define CIU_INTX_EN0_XXX_49 0x0002000000000000ULL 275 #define CIU_INTX_EN0_GMX_DRP 0x0001000000000000ULL 276 #define CIU_INTX_EN0_TRACE 0x0000800000000000ULL 277 #define CIU_INTX_EN0_RML 0x0000400000000000ULL 278 #define CIU_INTX_EN0_TWSI 0x0000200000000000ULL 279 #define CIU_INTX_EN0_WDOG_SUM 0x0000100000000000ULL 280 #define CIU_INTX_EN0_PCI_MSI 0x00000f0000000000ULL 281 #define CIU_INTX_EN0_PCI_MSI_63_48 0x0000080000000000ULL 282 #define CIU_INTX_EN0_PCI_MSI_47_32 0x0000040000000000ULL 283 #define CIU_INTX_EN0_PCI_MSI_31_16 0x0000020000000000ULL 284 #define CIU_INTX_EN0_PCI_MSI_15_0 0x0000010000000000ULL 285 #define CIU_INTX_EN0_PCI_INT 0x000000f000000000ULL 286 #define CIU_INTX_EN0_PCI_INT_D 0x0000008000000000ULL 287 #define CIU_INTX_EN0_PCI_INT_C 0x0000004000000000ULL 288 #define CIU_INTX_EN0_PCI_INT_B 0x0000002000000000ULL 289 #define CIU_INTX_EN0_PCI_INT_A 0x0000001000000000ULL 290 #define CIU_INTX_EN0_UART 0x0000000c00000000ULL 291 #define CIU_INTX_EN0_UART_1 0x0000000800000000ULL 292 #define CIU_INTX_EN0_UART_0 0x0000000400000000ULL 293 #define CIU_INTX_EN0_MBOX 0x0000000300000000ULL 294 #define CIU_INTX_EN0_MBOX_31_16 0x0000000200000000ULL 295 #define CIU_INTX_EN0_MBOX_15_0 0x0000000100000000ULL 296 #define CIU_INTX_EN0_GPIO 0x00000000ffff0000ULL 297 #define CIU_INTX_EN0_GPIO_15 0x0000000080000000ULL 298 #define CIU_INTX_EN0_GPIO_14 0x0000000040000000ULL 299 #define CIU_INTX_EN0_GPIO_13 0x0000000020000000ULL 300 #define CIU_INTX_EN0_GPIO_12 0x0000000010000000ULL 301 #define CIU_INTX_EN0_GPIO_11 0x0000000008000000ULL 302 #define CIU_INTX_EN0_GPIO_10 0x0000000004000000ULL 303 #define CIU_INTX_EN0_GPIO_9 0x0000000002000000ULL 304 #define CIU_INTX_EN0_GPIO_8 0x0000000001000000ULL 305 #define CIU_INTX_EN0_GPIO_7 0x0000000000800000ULL 306 #define CIU_INTX_EN0_GPIO_6 0x0000000000400000ULL 307 #define CIU_INTX_EN0_GPIO_5 0x0000000000200000ULL 308 #define CIU_INTX_EN0_GPIO_4 0x0000000000100000ULL 309 #define CIU_INTX_EN0_GPIO_3 0x0000000000080000ULL 310 #define CIU_INTX_EN0_GPIO_2 0x0000000000040000ULL 311 #define CIU_INTX_EN0_GPIO_1 0x0000000000020000ULL 312 #define CIU_INTX_EN0_GPIO_0 0x0000000000010000ULL 313 #define CIU_INTX_EN0_WORKQ 0x000000000000ffffULL 314 #define CIU_INTX_EN0_WORKQ_15 0x0000000000008000ULL 315 #define CIU_INTX_EN0_WORKQ_14 0x0000000000004000ULL 316 #define CIU_INTX_EN0_WORKQ_13 0x0000000000002000ULL 317 #define CIU_INTX_EN0_WORKQ_12 0x0000000000001000ULL 318 #define CIU_INTX_EN0_WORKQ_11 0x0000000000000800ULL 319 #define CIU_INTX_EN0_WORKQ_10 0x0000000000000400ULL 320 #define CIU_INTX_EN0_WORKQ_9 0x0000000000000200ULL 321 #define CIU_INTX_EN0_WORKQ_8 0x0000000000000100ULL 322 #define CIU_INTX_EN0_WORKQ_7 0x0000000000000080ULL 323 #define CIU_INTX_EN0_WORKQ_6 0x0000000000000040ULL 324 #define CIU_INTX_EN0_WORKQ_5 0x0000000000000020ULL 325 #define CIU_INTX_EN0_WORKQ_4 0x0000000000000010ULL 326 #define CIU_INTX_EN0_WORKQ_3 0x0000000000000008ULL 327 #define CIU_INTX_EN0_WORKQ_2 0x0000000000000004ULL 328 #define CIU_INTX_EN0_WORKQ_1 0x0000000000000002ULL 329 #define CIU_INTX_EN0_WORKQ_0 0x0000000000000001ULL 330 331 #define CIU_INTX_EN1_XXX_63_1 0xfffffffffffffffeULL 332 #define CIU_INTX_EN1_WDOG 0x0000000000000001ULL 333 334 #define CIU_TIMX_XXX_63_37 0xffffffe000000000ULL 335 #define CIU_TIMX_ONE_SHOT 0x0000001000000000ULL 336 #define CIU_TIMX_LEN 0x0000000fffffffffULL 337 338 #define CIU_WDOGX_XXX_63_46 0xffffc00000000000ULL 339 #define CIU_WDOGX_GSTOPEN 0x0000200000000000ULL 340 #define CIU_WDOGX_DSTOP 0x0000100000000000ULL 341 #define CIU_WDOGX_CNT 0x00000ffffff00000ULL 342 #define CIU_WDOGX_LEN 0x00000000000ffff0ULL 343 #define CIU_WDOGX_STATE 0x000000000000000cULL 344 #define CIU_WDOGX_MODE 0x0000000000000003ULL 345 346 #define CIU_PP_POKEX_XXX_63_0 0xffffffffffffffffULL 347 348 #define CIU_MBOX_SETX_XXX_63_32 0xffffffff00000000ULL 349 #define CIU_MBOX_SETX_SET 0x00000000ffffffffULL 350 351 #define CIU_MBOX_CLRX_XXX_63_32 0xffffffff00000000ULL 352 #define CIU_MBOX_CLRX_CLR 0x00000000ffffffffULL 353 354 #define CIU_PP_RST_XXX_63_1 0xfffffffffffffffeULL 355 #define CIU_PP_RST_RST0 0x0000000000000001ULL 356 357 #define CIU_PP_DBG_XXX_63_1 0xfffffffffffffffeULL 358 #define CIU_PP_DBG_PPDBG 0x0000000000000001ULL 359 360 #define CIU_GSTOP_XXX_63_1 0xfffffffffffffffeULL 361 #define CIU_GSTOP_GSTOP 0x0000000000000001ULL 362 363 #define CIU_NMI_XXX_63_1 0xfffffffffffffffeULL 364 #define CIU_NMI_NMI 0x0000000000000001ULL 365 366 #define CIU_DINT_XXX_63_1 0xfffffffffffffffeULL 367 #define CIU_DINT_DINT 0x0000000000000001ULL 368 369 #define CIU_FUSE_XXX_63_1 0xfffffffffffffffeULL 370 #define CIU_FUSE_FUSE 0x0000000000000001ULL 371 372 #define CIU_BIST_XXX_63_4 0xfffffffffffffff0ULL 373 #define CIU_BIST_BIST 0x000000000000000fULL 374 375 #define CIU_SOFT_BIST_XXX_63_1 0xfffffffffffffffeULL 376 #define CIU_SOFT_BIST_SOFT_BIST 0x0000000000000001ULL 377 378 #define CIU_SOFT_RST_XXX_63_1 0xfffffffffffffffeULL 379 #define CIU_SOFT_RST_SOFT_RST 0x0000000000000001ULL 380 381 #define CIU_SOFT_PRST_XXX_63_1 0xfffffffffffffff8ULL 382 #define CIU_SOFT_PRST_HOST64 0x0000000000000004ULL 383 #define CIU_SOFT_PRST_NPI 0x0000000000000002ULL 384 #define CIU_SOFT_PRST_SOFT_PRST 0x0000000000000001ULL 385 386 #define CIU_PCI_INTA_XXX_63_2 0xfffffffffffffffcULL 387 #define CIU_PCI_INTA_INT 0x0000000000000003ULL 388 389 #endif /* _CN30XXCIUREG_H_ */ 390