1 /* 2 * THIS FILE IS AUTOMATICALLY GENERATED 3 * DONT EDIT THIS FILE 4 */ 5 6 /* $OpenBSD: cn30xxfpareg.h,v 1.1 2011/06/16 11:22:30 syuu Exp $ */ 7 8 /* 9 * Copyright (c) 2007 Internet Initiative Japan, Inc. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Cavium Networks OCTEON CN30XX Hardware Reference Manual 36 * CN30XX-HM-1.0 37 * 6.2 FPA Registers 38 */ 39 40 #ifndef _CN30XXFPAREG_H_ 41 #define _CN30XXFPAREG_H_ 42 43 /* ---- register offsets */ 44 45 #define FPA_INT_SUM 0x0001180028000040ULL 46 #define FPA_INT_ENB 0x0001180028000048ULL 47 #define FPA_CTL_STATUS 0x0001180028000050ULL 48 #define FPA_QUE0_AVAILABLE 0x0001180028000098ULL 49 #define FPA_QUE1_AVAILABLE 0x00011800280000a0ULL 50 #define FPA_QUE2_AVAILABLE 0x00011800280000a8ULL 51 #define FPA_QUE3_AVAILABLE 0x00011800280000b0ULL 52 #define FPA_QUE4_AVAILABLE 0x00011800280000b8ULL 53 #define FPA_QUE5_AVAILABLE 0x00011800280000c0ULL 54 #define FPA_QUE6_AVAILABLE 0x00011800280000c8ULL 55 #define FPA_QUE7_AVAILABLE 0x00011800280000d0ULL 56 #define FPA_WART_CTL 0x00011800280000d8ULL 57 #define FPA_WART_STATUS 0x00011800280000e0ULL 58 #define FPA_BIST_STATUS 0x00011800280000e8ULL 59 #define FPA_QUE0_PAGE_INDEX 0x00011800280000f0ULL 60 #define FPA_QUE1_PAGE_INDEX 0x00011800280000f8ULL 61 #define FPA_QUE2_PAGE_INDEX 0x0001180028000100ULL 62 #define FPA_QUE3_PAGE_INDEX 0x0001180028000108ULL 63 #define FPA_QUE4_PAGE_INDEX 0x0001180028000110ULL 64 #define FPA_QUE5_PAGE_INDEX 0x0001180028000118ULL 65 #define FPA_QUE6_PAGE_INDEX 0x0001180028000120ULL 66 #define FPA_QUE7_PAGE_INDEX 0x0001180028000128ULL 67 #define FPA_QUE_EXP 0x0001180028000130ULL 68 #define FPA_QUE_ACT 0x0001180028000138ULL 69 70 /* ---- register bit definitions */ 71 72 #define FPA_INT_SUM_XXX_63_28 0xfffffffff0000000ULL 73 #define FPA_INT_SUM_Q7_PERR 0x0000000008000000ULL 74 #define FPA_INT_SUM_Q7_COFF 0x0000000004000000ULL 75 #define FPA_INT_SUM_Q7_UND 0x0000000002000000ULL 76 #define FPA_INT_SUM_Q6_PERR 0x0000000001000000ULL 77 #define FPA_INT_SUM_Q6_COFF 0x0000000000800000ULL 78 #define FPA_INT_SUM_Q6_UND 0x0000000000400000ULL 79 #define FPA_INT_SUM_Q5_PERR 0x0000000000200000ULL 80 #define FPA_INT_SUM_Q5_COFF 0x0000000000100000ULL 81 #define FPA_INT_SUM_Q5_UND 0x0000000000080000ULL 82 #define FPA_INT_SUM_Q4_PERR 0x0000000000040000ULL 83 #define FPA_INT_SUM_Q4_COFF 0x0000000000020000ULL 84 #define FPA_INT_SUM_Q4_UND 0x0000000000010000ULL 85 #define FPA_INT_SUM_Q3_PERR 0x0000000000008000ULL 86 #define FPA_INT_SUM_Q3_COFF 0x0000000000004000ULL 87 #define FPA_INT_SUM_Q3_UND 0x0000000000002000ULL 88 #define FPA_INT_SUM_Q2_PERR 0x0000000000001000ULL 89 #define FPA_INT_SUM_Q2_COFF 0x0000000000000800ULL 90 #define FPA_INT_SUM_Q2_UND 0x0000000000000400ULL 91 #define FPA_INT_SUM_Q1_PERR 0x0000000000000200ULL 92 #define FPA_INT_SUM_Q1_COFF 0x0000000000000100ULL 93 #define FPA_INT_SUM_Q1_UND 0x0000000000000080ULL 94 #define FPA_INT_SUM_Q0_PERR 0x0000000000000040ULL 95 #define FPA_INT_SUM_Q0_COFF 0x0000000000000020ULL 96 #define FPA_INT_SUM_Q0_UND 0x0000000000000010ULL 97 #define FPA_INT_SUM_FED1_DBE 0x0000000000000008ULL 98 #define FPA_INT_SUM_FED1_SBE 0x0000000000000004ULL 99 #define FPA_INT_SUM_FED0_DBE 0x0000000000000002ULL 100 #define FPA_INT_SUM_FED0_SBE 0x0000000000000001ULL 101 102 #define FPA_INT_ENB_XXX_63_28 0xfffffffff0000000ULL 103 #define FPA_INT_ENB_Q7_PERR 0x0000000008000000ULL 104 #define FPA_INT_ENB_Q7_COFF 0x0000000004000000ULL 105 #define FPA_INT_ENB_Q7_UND 0x0000000002000000ULL 106 #define FPA_INT_ENB_Q6_PERR 0x0000000001000000ULL 107 #define FPA_INT_ENB_Q6_COFF 0x0000000000800000ULL 108 #define FPA_INT_ENB_Q6_UND 0x0000000000400000ULL 109 #define FPA_INT_ENB_Q5_PERR 0x0000000000200000ULL 110 #define FPA_INT_ENB_Q5_COFF 0x0000000000100000ULL 111 #define FPA_INT_ENB_Q5_UND 0x0000000000080000ULL 112 #define FPA_INT_ENB_Q4_PERR 0x0000000000040000ULL 113 #define FPA_INT_ENB_Q4_COFF 0x0000000000020000ULL 114 #define FPA_INT_ENB_Q4_UND 0x0000000000010000ULL 115 #define FPA_INT_ENB_Q3_PERR 0x0000000000008000ULL 116 #define FPA_INT_ENB_Q3_COFF 0x0000000000004000ULL 117 #define FPA_INT_ENB_Q3_UND 0x0000000000002000ULL 118 #define FPA_INT_ENB_Q2_PERR 0x0000000000001000ULL 119 #define FPA_INT_ENB_Q2_COFF 0x0000000000000800ULL 120 #define FPA_INT_ENB_Q2_UND 0x0000000000000400ULL 121 #define FPA_INT_ENB_Q1_PERR 0x0000000000000200ULL 122 #define FPA_INT_ENB_Q1_COFF 0x0000000000000100ULL 123 #define FPA_INT_ENB_Q1_UND 0x0000000000000080ULL 124 #define FPA_INT_ENB_Q0_PERR 0x0000000000000040ULL 125 #define FPA_INT_ENB_Q0_COFF 0x0000000000000020ULL 126 #define FPA_INT_ENB_Q0_UND 0x0000000000000010ULL 127 #define FPA_INT_ENB_FED1_DBE 0x0000000000000008ULL 128 #define FPA_INT_ENB_FED1_SBE 0x0000000000000004ULL 129 #define FPA_INT_ENB_FED0_DBE 0x0000000000000002ULL 130 #define FPA_INT_ENB_FED0_SBE 0x0000000000000001ULL 131 132 #define FPA_CTL_STATUS_XXX_63_18 0xfffffffffffc0000ULL 133 #define FPA_CTL_STATUS_RESET 0x0000000000020000ULL 134 #define FPA_CTL_STATUS_USE_LDT 0x0000000000010000ULL 135 #define FPA_CTL_STATUS_USE_STT 0x0000000000008000ULL 136 #define FPA_CTL_STATUS_ENB 0x0000000000004000ULL 137 #define FPA_CTL_STATUS_MEM1_ERR 0x0000000000003f80ULL 138 #define FPA_CTL_STATUS_MEM0_ERR 0x000000000000007fULL 139 140 #define FPA_QUEX_AVAILABLE_XXX_63_29 0xffffffffe0000000ULL 141 #define FPA_QUEX_AVAILABLE_QUE_SIZ 0x000000001fffffffULL 142 143 #define FPA_WART_CTL_XXX_63_16 0xffffffffffff0000ULL 144 #define FPA_WART_CTL_CTL 0x000000000000ffffULL 145 146 #define FPA_WART_STATUS_XXX_63_32 0xffffffff00000000ULL 147 #define FPA_WART_STATUS_STATUS 0x00000000ffffffffULL 148 149 #define FPA_BIST_STATUS_XXX_63_5 0xffffffffffffffe0ULL 150 #define FPA_BIST_STATUS_FRD 0x0000000000000010ULL 151 #define FPA_BIST_STATUS_FPF0 0x0000000000000008ULL 152 #define FPA_BIST_STATUS_FPF1 0x0000000000000004ULL 153 #define FPA_BIST_STATUS_FFR 0x0000000000000002ULL 154 #define FPA_BIST_STATUS_FDR 0x0000000000000001ULL 155 156 #define FPA_QUEX_PAGE_INDEX_XXX_63_25 0xfffffffffe000000ULL 157 #define FPA_QUEX_PAGE_INDEX_PG_NUM 0x0000000001ffffffULL 158 159 #define FPA_QUE_EXP_XXX_63_32 0xffffffff00000000ULL 160 #define FPA_QUE_EXP_XXX_31_29 0x00000000e0000000ULL 161 #define FPA_QUE_EXP_EXP_QUE 0x000000001c000000ULL 162 #define FPA_QUE_EXP_EXP_INDX 0x0000000003ffffffULL 163 164 #define FPA_QUE_ACT_XXX_63_32 0xffffffff00000000ULL 165 #define FPA_QUE_ACT_XXX_31_29 0x00000000e0000000ULL 166 #define FPA_QUE_ACT_ACT_QUE 0x000000001c000000ULL 167 #define FPA_QUE_ACT_ACT_INDX 0x0000000003ffffffULL 168 169 /* ---- bitmask_snprintf(9) */ 170 171 #define FPA_INT_SUM_BITS \ 172 "\177" /* new format */ \ 173 "\177" /* seil ext */ \ 174 "\020" /* hex display */ \ 175 "\020" /* %016x format */ \ 176 "b\x1b" "Q7_PERR\0" \ 177 "b\x1a" "Q7_COFF\0" \ 178 "b\x19" "Q7_UND\0" \ 179 "b\x18" "Q6_PERR\0" \ 180 "b\x17" "Q6_COFF\0" \ 181 "b\x16" "Q6_UND\0" \ 182 "b\x15" "Q5_PERR\0" \ 183 "b\x14" "Q5_COFF\0" \ 184 "b\x13" "Q5_UND\0" \ 185 "b\x12" "Q4_PERR\0" \ 186 "b\x11" "Q4_COFF\0" \ 187 "b\x10" "Q4_UND\0" \ 188 "b\x0f" "Q3_PERR\0" \ 189 "b\x0e" "Q3_COFF\0" \ 190 "b\x0d" "Q3_UND\0" \ 191 "b\x0c" "Q2_PERR\0" \ 192 "b\x0b" "Q2_COFF\0" \ 193 "b\x0a" "Q2_UND\0" \ 194 "b\x09" "Q1_PERR\0" \ 195 "b\x08" "Q1_COFF\0" \ 196 "b\x07" "Q1_UND\0" \ 197 "b\x06" "Q0_PERR\0" \ 198 "b\x05" "Q0_COFF\0" \ 199 "b\x04" "Q0_UND\0" \ 200 "b\x03" "FED1_DBE\0" \ 201 "b\x02" "FED1_SBE\0" \ 202 "b\x01" "FED0_DBE\0" \ 203 "b\x00" "FED0_SBE\0" 204 205 #define FPA_INT_ENB_BITS \ 206 "\177" /* new format */ \ 207 "\177" /* seil ext */ \ 208 "\020" /* hex display */ \ 209 "\020" /* %016x format */ \ 210 "b\x1b" "Q7_PERR\0" \ 211 "b\x1a" "Q7_COFF\0" \ 212 "b\x19" "Q7_UND\0" \ 213 "b\x18" "Q6_PERR\0" \ 214 "b\x17" "Q6_COFF\0" \ 215 "b\x16" "Q6_UND\0" \ 216 "b\x15" "Q5_PERR\0" \ 217 "b\x14" "Q5_COFF\0" \ 218 "b\x13" "Q5_UND\0" \ 219 "b\x12" "Q4_PERR\0" \ 220 "b\x11" "Q4_COFF\0" \ 221 "b\x10" "Q4_UND\0" \ 222 "b\x0f" "Q3_PERR\0" \ 223 "b\x0e" "Q3_COFF\0" \ 224 "b\x0d" "Q3_UND\0" \ 225 "b\x0c" "Q2_PERR\0" \ 226 "b\x0b" "Q2_COFF\0" \ 227 "b\x0a" "Q2_UND\0" \ 228 "b\x09" "Q1_PERR\0" \ 229 "b\x08" "Q1_COFF\0" \ 230 "b\x07" "Q1_UND\0" \ 231 "b\x06" "Q0_PERR\0" \ 232 "b\x05" "Q0_COFF\0" \ 233 "b\x04" "Q0_UND\0" \ 234 "b\x03" "FED1_DBE\0" \ 235 "b\x02" "FED1_SBE\0" \ 236 "b\x01" "FED0_DBE\0" \ 237 "b\x00" "FED0_SBE\0" 238 239 #define FPA_CTL_STATUS_BITS \ 240 "\177" /* new format */ \ 241 "\177" /* seil ext */ \ 242 "\020" /* hex display */ \ 243 "\020" /* %016x format */ \ 244 "b\x11" "RESET\0" \ 245 "b\x10" "USE_LDT\0" \ 246 "b\x0f" "USE_STT\0" \ 247 "b\x0e" "ENB\0" \ 248 "f\x07\x07" "MEM1_ERR\0" \ 249 "f\x00\x07" "MEM0_ERR\0" 250 251 #define FPA_QUEX_AVAILABLE_BITS \ 252 "\177" /* new format */ \ 253 "\177" /* seil ext */ \ 254 "\020" /* hex display */ \ 255 "\020" /* %016x format */ \ 256 "f\x00\x1d" "QUE_SIZ\0" 257 #define FPA_QUE0_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS 258 #define FPA_QUE1_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS 259 #define FPA_QUE2_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS 260 #define FPA_QUE3_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS 261 #define FPA_QUE4_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS 262 #define FPA_QUE5_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS 263 #define FPA_QUE6_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS 264 #define FPA_QUE7_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS 265 266 #define FPA_WART_CTL_BITS \ 267 "\177" /* new format */ \ 268 "\177" /* seil ext */ \ 269 "\020" /* hex display */ \ 270 "\020" /* %016x format */ \ 271 "f\x00\x10" "CTL\0" 272 273 #define FPA_WART_STATUS_BITS \ 274 "\177" /* new format */ \ 275 "\177" /* seil ext */ \ 276 "\020" /* hex display */ \ 277 "\020" /* %016x format */ \ 278 "f\x00\x20" "STATUS\0" 279 280 #define FPA_BIST_STATUS_BITS \ 281 "\177" /* new format */ \ 282 "\177" /* seil ext */ \ 283 "\020" /* hex display */ \ 284 "\020" /* %016x format */ \ 285 "b\x04" "FRD\0" \ 286 "b\x03" "FPF0\0" \ 287 "b\x02" "FPF1\0" \ 288 "b\x01" "FFR\0" \ 289 "b\x00" "FDR\0" 290 291 #define FPA_QUEX_PAGE_INDEX_BITS \ 292 "\177" /* new format */ \ 293 "\177" /* seil ext */ \ 294 "\020" /* hex display */ \ 295 "\020" /* %016x format */ \ 296 "f\x00\x19" "PG_NUM\0" 297 #define FPA_QUE0_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS 298 #define FPA_QUE1_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS 299 #define FPA_QUE2_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS 300 #define FPA_QUE3_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS 301 #define FPA_QUE4_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS 302 #define FPA_QUE5_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS 303 #define FPA_QUE6_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS 304 #define FPA_QUE7_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS 305 306 #define FPA_QUE_EXP_BITS \ 307 "\177" /* new format */ \ 308 "\177" /* seil ext */ \ 309 "\020" /* hex display */ \ 310 "\020" /* %016x format */ \ 311 "f\x1a\x03" "EXP_QUE\0" \ 312 "f\x00\x1a" "EXP_INDX\0" 313 314 #define FPA_QUE_ACT_BITS \ 315 "\177" /* new format */ \ 316 "\177" /* seil ext */ \ 317 "\020" /* hex display */ \ 318 "\020" /* %016x format */ \ 319 "f\x1a\x03" "ACT_QUE\0" \ 320 "f\x00\x1a" "ACT_INDX\0" 321 322 /* ---- operations */ 323 324 /* 325 * 6.1 Free Pool Unit Operations 326 */ 327 328 #define FPA_MAJORDID 0x5 /* 0b00101 */ 329 330 #define FPA_OPS_MAJORDID 0x0000f80000000000ULL 331 #define FPA_OPS_MAJORDID_SHIFT 43 332 #define FPA_OPS_SUBDID 0x0000070000000000ULL 333 #define FPA_OPS_SUBDID_SHIFT 40 334 #define FPA_OPS_XXX_39_0 0x000000ffffffffffULL 335 336 /* 6.1.1 Load Operations */ 337 338 #define FPA_OPS_LOAD_1 0x0001000000000000ULL 339 #define FPA_OPS_LOAD_MAJORDID 0x0000f80000000000ULL 340 #define FPA_OPS_LOAD_SUBDID 0x0000070000000000ULL 341 #define FPA_OPS_LOAD_XXX_39_0 0x000000ffffffffffULL 342 343 /* 6.1.2 IOBDMA Operations */ 344 345 #define FPA_OPS_IOBDMA_SRCADDR 0xff00000000000000ULL 346 #define FPA_OPS_IOBDMA_LEN 0x00ff000000000000ULL 347 #define FPA_OPS_IOBDMA_LEN_SHIFT 48 348 #define FPA_OPS_IOBDMA_MAJORDID 0x0000f80000000000ULL 349 #define FPA_OPS_IOBDMA_SUBDIR 0x0000070000000000ULL 350 #define FPA_OPS_IOBDMA_XXX_39_0 0x000000ffffffffffULL 351 352 /* 6.1.3 Store Operations */ 353 354 #define FPA_OPS_STORE_1 0x0001000000000000ULL 355 #define FPA_OPS_STORE_MAJORDID 0x0000f80000000000ULL 356 #define FPA_OPS_STORE_SUBDID 0x0000070000000000ULL 357 #define FPA_OPS_STORE_XXX_39_0 0x000000ffffffffffULL 358 359 #define FPA_OPS_STORE_DATA_XXX_63_9 0xfffffffffffffe00ULL 360 #define FPA_OPS_STORE_DATA_DWBCOUNT 0x00000000000001ffULL 361 362 /* ---- bus_space(9) */ 363 364 #define FPA_BASE 0x0001180028000000ULL 365 #define FPA_SIZE 0x0200 366 367 #define FPA_INT_SUM_OFFSET 0x0040 368 #define FPA_INT_ENB_OFFSET 0x0048 369 #define FPA_CTL_STATUS_OFFSET 0x0050 370 #define FPA_QUE0_AVAILABLE_OFFSET 0x0098 371 #define FPA_QUE1_AVAILABLE_OFFSET 0x00a0 372 #define FPA_QUE2_AVAILABLE_OFFSET 0x00a8 373 #define FPA_QUE3_AVAILABLE_OFFSET 0x00b0 374 #define FPA_QUE4_AVAILABLE_OFFSET 0x00b8 375 #define FPA_QUE5_AVAILABLE_OFFSET 0x00c0 376 #define FPA_QUE6_AVAILABLE_OFFSET 0x00c8 377 #define FPA_QUE7_AVAILABLE_OFFSET 0x00d0 378 #define FPA_WART_CTL_OFFSET 0x00d8 379 #define FPA_WART_STATUS_OFFSET 0x00e0 380 #define FPA_BIST_STATUS_OFFSET 0x00e8 381 #define FPA_QUE0_PAGE_INDEX_OFFSET 0x00f0 382 #define FPA_QUE1_PAGE_INDEX_OFFSET 0x00f8 383 #define FPA_QUE2_PAGE_INDEX_OFFSET 0x0100 384 #define FPA_QUE3_PAGE_INDEX_OFFSET 0x0108 385 #define FPA_QUE4_PAGE_INDEX_OFFSET 0x0110 386 #define FPA_QUE5_PAGE_INDEX_OFFSET 0x0118 387 #define FPA_QUE6_PAGE_INDEX_OFFSET 0x0120 388 #define FPA_QUE7_PAGE_INDEX_OFFSET 0x0128 389 #define FPA_QUE_EXP_OFFSET 0x0130 390 #define FPA_QUE_ACT_OFFSET 0x0138 391 392 /* XXXX not use bit field */ 393 /** 394 * cvmx_fpa_ctl_status 395 * 396 * FPA_CTL_STATUS = FPA's Control/Status Register 397 * 398 * The FPA's interrupt enable register. 399 */ 400 401 #if 0 402 403 #ifndef MIPS_SPACE 404 #define MIPS_SPACE 405 typedef enum { 406 MIPS_SPACE_XKSEG = 3LL, 407 MIPS_SPACE_XKPHYS = 2LL, 408 MIPS_SPACE_XSSEG = 1LL, 409 MIPS_SPACE_XUSEG = 0LL 410 } mips_space_t; 411 #endif 412 413 typedef enum { 414 MIPS_XKSEG_SPACE_KSEG0 = 0LL, 415 MIPS_XKSEG_SPACE_KSEG1 = 1LL, 416 MIPS_XKSEG_SPACE_SSEG = 2LL, 417 MIPS_XKSEG_SPACE_KSEG3 = 3LL 418 } mips_xkseg_space_t; 419 420 // decodes <14:13> of a kseg3 window address 421 typedef enum { 422 OCTEON_ADD_WIN_SCR = 0L, 423 OCTEON_ADD_WIN_DMA = 1L, // see cvmx_add_win_dma_dec_t for further decode 424 OCTEON_ADD_WIN_UNUSED = 2L, 425 OCTEON_ADD_WIN_UNUSED2 = 3L 426 } octeon_add_win_dec_t; 427 428 // decode within DMA space 429 typedef enum { 430 OCTEON_ADD_WIN_DMA_ADD = 0L, // add store data to the write buffer entry, allocating it if necessary 431 OCTEON_ADD_WIN_DMA_SENDMEM = 1L, // send out the write buffer entry to DRAM 432 // store data must be normal DRAM memory space address in this case 433 OCTEON_ADD_WIN_DMA_SENDDMA = 2L, // send out the write buffer entry as an IOBDMA command 434 // see CVMX_ADD_WIN_DMA_SEND_DEC for data contents 435 OCTEON_ADD_WIN_DMA_SENDIO = 3L, // send out the write buffer entry as an IO write 436 // store data must be normal IO space address in this case 437 OCTEON_ADD_WIN_DMA_SENDSINGLE = 4L, // send out a single-tick command on the NCB bus 438 // no write buffer data needed/used 439 } octeon_add_win_dma_dec_t; 440 441 442 typedef union { 443 444 uint64_t u64; 445 446 struct { 447 mips_space_t R : 2; 448 uint64_t offset :62; 449 } sva; // mapped or unmapped virtual address 450 451 struct { 452 uint64_t zeroes :33; 453 uint64_t offset :31; 454 } suseg; // mapped USEG virtual addresses (typically) 455 456 struct { 457 uint64_t ones :33; 458 mips_xkseg_space_t sp : 2; 459 uint64_t offset :29; 460 } sxkseg; // mapped or unmapped virtual address 461 462 struct { 463 mips_space_t R : 2; // CVMX_MIPS_SPACE_XKPHYS in this case 464 uint64_t cca : 3; // ignored by octeon 465 uint64_t mbz :10; 466 uint64_t pa :49; // physical address 467 } sxkphys; // physical address accessed through xkphys unmapped virtual address 468 469 struct { 470 uint64_t mbz :15; 471 uint64_t is_io : 1; // if set, the address is uncached and resides on MCB bus 472 uint64_t did : 8; // the hardware ignores this field when is_io==0, else device ID 473 uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I 474 uint64_t offset :36; 475 } sphys; // physical address 476 477 struct { 478 uint64_t zeroes :24; // techically, <47:40> are dont-cares 479 uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I 480 uint64_t offset :36; 481 } smem; // physical mem address 482 483 struct { 484 uint64_t mem_region :2; 485 uint64_t mbz :13; 486 uint64_t is_io : 1; // 1 in this case 487 uint64_t did : 8; // the hardware ignores this field when is_io==0, else device ID 488 uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I 489 uint64_t offset :36; 490 } sio; // physical IO address 491 492 struct { 493 uint64_t ones : 49; 494 octeon_add_win_dec_t csrdec : 2; // CVMX_ADD_WIN_SCR (0) in this case 495 uint64_t addr : 13; 496 } sscr; // scratchpad virtual address - accessed through a window at the end of kseg3 497 // there should only be stores to IOBDMA space, no loads 498 struct { 499 uint64_t ones : 49; 500 octeon_add_win_dec_t csrdec : 2; // CVMX_ADD_WIN_DMA (1) in this case 501 uint64_t unused2: 3; 502 octeon_add_win_dma_dec_t type : 3; 503 uint64_t addr : 7; 504 } sdma; // IOBDMA virtual address - accessed through a window at the end of kseg3 505 506 struct { 507 uint64_t didspace : 24; 508 uint64_t unused : 40; 509 } sfilldidspace; 510 511 } cn30xxfpa_addr_t; 512 513 #endif 514 515 #endif /* _CN30XXFPAREG_H_ */ 516