14a04f2fdSsyuu /* 24a04f2fdSsyuu * THIS FILE IS AUTOMATICALLY GENERATED 34a04f2fdSsyuu * DONT EDIT THIS FILE 44a04f2fdSsyuu */ 54a04f2fdSsyuu 6*52334306Syasuoka /* $OpenBSD: cn30xxgmxreg.h,v 1.10 2022/12/28 01:39:21 yasuoka Exp $ */ 74a04f2fdSsyuu 84a04f2fdSsyuu /* 94a04f2fdSsyuu * Copyright (c) 2007 Internet Initiative Japan, Inc. 104a04f2fdSsyuu * All rights reserved. 114a04f2fdSsyuu * 124a04f2fdSsyuu * Redistribution and use in source and binary forms, with or without 134a04f2fdSsyuu * modification, are permitted provided that the following conditions 144a04f2fdSsyuu * are met: 154a04f2fdSsyuu * 1. Redistributions of source code must retain the above copyright 164a04f2fdSsyuu * notice, this list of conditions and the following disclaimer. 174a04f2fdSsyuu * 2. Redistributions in binary form must reproduce the above copyright 184a04f2fdSsyuu * notice, this list of conditions and the following disclaimer in the 194a04f2fdSsyuu * documentation and/or other materials provided with the distribution. 204a04f2fdSsyuu * 21*52334306Syasuoka * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 224a04f2fdSsyuu * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 234a04f2fdSsyuu * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24*52334306Syasuoka * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 254a04f2fdSsyuu * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 264a04f2fdSsyuu * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 274a04f2fdSsyuu * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 284a04f2fdSsyuu * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 294a04f2fdSsyuu * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 304a04f2fdSsyuu * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 314a04f2fdSsyuu * SUCH DAMAGE. 324a04f2fdSsyuu */ 334a04f2fdSsyuu 344a04f2fdSsyuu /* 354a04f2fdSsyuu * Cavium Networks OCTEON CN30XX Hardware Reference Manual 364a04f2fdSsyuu * CN30XX-HM-1.0 374a04f2fdSsyuu * 13.8 GMX Registers 384a04f2fdSsyuu */ 394a04f2fdSsyuu 404a04f2fdSsyuu #ifndef _CN30XXGMXREG_H_ 414a04f2fdSsyuu #define _CN30XXGMXREG_H_ 424a04f2fdSsyuu 434a04f2fdSsyuu #define GMX0_RX0_INT_REG 0x000 444a04f2fdSsyuu #define GMX0_RX0_INT_EN 0x008 454a04f2fdSsyuu #define GMX0_PRT0_CFG 0x010 464a04f2fdSsyuu #define GMX0_RX0_FRM_CTL 0x018 474a04f2fdSsyuu #define GMX0_RX0_FRM_CHK 0x020 484a04f2fdSsyuu #define GMX0_RX0_FRM_MIN 0x028 494a04f2fdSsyuu #define GMX0_RX0_FRM_MAX 0x030 504a04f2fdSsyuu #define GMX0_RX0_JABBER 0x038 514a04f2fdSsyuu #define GMX0_RX0_DECISION 0x040 524a04f2fdSsyuu #define GMX0_RX0_UDD_SKP 0x048 534a04f2fdSsyuu #define GMX0_RX0_STATS_CTL 0x050 544a04f2fdSsyuu #define GMX0_RX0_IFG 0x058 554a04f2fdSsyuu #define GMX0_RX0_RX_INBND 0x060 564a04f2fdSsyuu #define GMX0_RX0_STATS_PKTS 0x080 574a04f2fdSsyuu #define GMX0_RX0_STATS_OCTS 0x088 584a04f2fdSsyuu #define GMX0_RX0_STATS_PKTS_CTL 0x090 594a04f2fdSsyuu #define GMX0_RX0_STATS_OCTS_CTL 0x098 604a04f2fdSsyuu #define GMX0_RX0_STATS_PKTS_DMAC 0x0a0 614a04f2fdSsyuu #define GMX0_RX0_STATS_OCTS_DMAC 0x0a8 624a04f2fdSsyuu #define GMX0_RX0_STATS_PKTS_DRP 0x0b0 634a04f2fdSsyuu #define GMX0_RX0_STATS_OCTS_DRP 0x0b8 644a04f2fdSsyuu #define GMX0_RX0_STATS_PKTS_BAD 0x0c0 654a04f2fdSsyuu #define GMX0_RX0_ADR_CTL 0x100 664a04f2fdSsyuu #define GMX0_RX0_ADR_CAM_EN 0x108 6781e9868dSvisa #define GMX0_RX0_ADR_CAM(i) (0x180 + (i) * 8) 684a04f2fdSsyuu #define GMX0_TX0_CLK 0x208 694a04f2fdSsyuu #define GMX0_TX0_THRESH 0x210 704a04f2fdSsyuu #define GMX0_TX0_APPEND 0x218 714a04f2fdSsyuu #define GMX0_TX0_SLOT 0x220 724a04f2fdSsyuu #define GMX0_TX0_BURST 0x228 734a04f2fdSsyuu #define GMX0_SMAC0 0x230 744a04f2fdSsyuu #define GMX0_TX0_PAUSE_PKT_TIME 0x238 754a04f2fdSsyuu #define GMX0_TX0_MIN_PKT 0x240 764a04f2fdSsyuu #define GMX0_TX0_PAUSE_PKT_INTERVAL 0x248 774a04f2fdSsyuu #define GMX0_TX0_SOFT_PAUSE 0x250 784a04f2fdSsyuu #define GMX0_TX0_PAUSE_TOGO 0x258 794a04f2fdSsyuu #define GMX0_TX0_PAUSE_ZERO 0x260 804a04f2fdSsyuu #define GMX0_TX0_STATS_CTL 0x268 814a04f2fdSsyuu #define GMX0_TX0_CTL 0x270 824a04f2fdSsyuu #define GMX0_TX0_STAT0 0x280 834a04f2fdSsyuu #define GMX0_TX0_STAT1 0x288 844a04f2fdSsyuu #define GMX0_TX0_STAT2 0x290 854a04f2fdSsyuu #define GMX0_TX0_STAT3 0x298 864a04f2fdSsyuu #define GMX0_TX0_STAT4 0x2a0 874a04f2fdSsyuu #define GMX0_TX0_STAT5 0x2a8 884a04f2fdSsyuu #define GMX0_TX0_STAT6 0x2b0 894a04f2fdSsyuu #define GMX0_TX0_STAT7 0x2b8 904a04f2fdSsyuu #define GMX0_TX0_STAT8 0x2c0 914a04f2fdSsyuu #define GMX0_TX0_STAT9 0x2c8 924a04f2fdSsyuu #define GMX0_BIST0 0x400 934a04f2fdSsyuu #define GMX0_RX_PRTS 0x410 944a04f2fdSsyuu #define GMX0_RX_BP_DROP0 0x420 954a04f2fdSsyuu #define GMX0_RX_BP_DROP1 0x428 964a04f2fdSsyuu #define GMX0_RX_BP_DROP2 0x430 974a04f2fdSsyuu #define GMX0_RX_BP_ON0 0x440 984a04f2fdSsyuu #define GMX0_RX_BP_ON1 0x448 994a04f2fdSsyuu #define GMX0_RX_BP_ON2 0x450 1004a04f2fdSsyuu #define GMX0_RX_BP_OFF0 0x460 1014a04f2fdSsyuu #define GMX0_RX_BP_OFF1 0x468 1024a04f2fdSsyuu #define GMX0_RX_BP_OFF2 0x470 1034a04f2fdSsyuu #define GMX0_TX_PRTS 0x480 1044a04f2fdSsyuu #define GMX0_TX_IFG 0x488 1054a04f2fdSsyuu #define GMX0_TX_JAM 0x490 1064a04f2fdSsyuu #define GMX0_TX_COL_ATTEMPT 0x498 1074a04f2fdSsyuu #define GMX0_TX_PAUSE_PKT_DMAC 0x4a0 1084a04f2fdSsyuu #define GMX0_TX_PAUSE_PKT_TYPE 0x4a8 1094a04f2fdSsyuu #define GMX0_TX_OVR_BP 0x4c8 1104a04f2fdSsyuu #define GMX0_TX_BP 0x4d0 1114a04f2fdSsyuu #define GMX0_TX_CORRUPT 0x4d8 1124a04f2fdSsyuu #define GMX0_RX_PRT_INFO 0x4e8 1134a04f2fdSsyuu #define GMX0_TX_LFSR 0x4f8 1144a04f2fdSsyuu #define GMX0_TX_INT_REG 0x500 1154a04f2fdSsyuu #define GMX0_TX_INT_EN 0x508 1164a04f2fdSsyuu #define GMX0_NXA_ADR 0x510 1174a04f2fdSsyuu #define GMX0_BAD_REG 0x518 1184a04f2fdSsyuu #define GMX0_STAT_BP 0x520 1194a04f2fdSsyuu #define GMX0_TX_CLK_MSK0 0x780 1204a04f2fdSsyuu #define GMX0_TX_CLK_MSK1 0x788 1214a04f2fdSsyuu #define GMX0_RX_TX_STATUS 0x7e8 1224a04f2fdSsyuu #define GMX0_INF_MODE 0x7f8 1234a04f2fdSsyuu 1244a04f2fdSsyuu /* -------------------------------------------------------------------------- */ 1254a04f2fdSsyuu 1264a04f2fdSsyuu /* GMX Interrupt Registers */ 1274a04f2fdSsyuu 1284a04f2fdSsyuu #define RXN_INT_REG_XXX_63_19 0xfffffffffff80000ULL 1294a04f2fdSsyuu #define RXN_INT_REG_PHY_DUPX 0x0000000000040000ULL 1304a04f2fdSsyuu #define RXN_INT_REG_PHY_SPD 0x0000000000020000ULL 1314a04f2fdSsyuu #define RXN_INT_REG_PHY_LINK 0x0000000000010000ULL 1324a04f2fdSsyuu #define RXN_INT_REG_IFGERR 0x0000000000008000ULL 1334a04f2fdSsyuu #define RXN_INT_REG_COLDET 0x0000000000004000ULL 1344a04f2fdSsyuu #define RXN_INT_REG_FALERR 0x0000000000002000ULL 1354a04f2fdSsyuu #define RXN_INT_REG_RSVERR 0x0000000000001000ULL 1364a04f2fdSsyuu #define RXN_INT_REG_PCTERR 0x0000000000000800ULL 1374a04f2fdSsyuu #define RXN_INT_REG_OVRERR 0x0000000000000400ULL 1384a04f2fdSsyuu #define RXN_INT_REG_NIBERR 0x0000000000000200ULL 1394a04f2fdSsyuu #define RXN_INT_REG_SKPERR 0x0000000000000100ULL 1404a04f2fdSsyuu #define RXN_INT_REG_RCVERR 0x0000000000000080ULL 1414a04f2fdSsyuu #define RXN_INT_REG_LENERR 0x0000000000000040ULL 1424a04f2fdSsyuu #define RXN_INT_REG_ALNERR 0x0000000000000020ULL 1434a04f2fdSsyuu #define RXN_INT_REG_FCSERR 0x0000000000000010ULL 1444a04f2fdSsyuu #define RXN_INT_REG_JABBER 0x0000000000000008ULL 1454a04f2fdSsyuu #define RXN_INT_REG_MAXERR 0x0000000000000004ULL 1464a04f2fdSsyuu #define RXN_INT_REG_CAREXT 0x0000000000000002ULL 1474a04f2fdSsyuu #define RXN_INT_REG_MINERR 0x0000000000000001ULL 1484a04f2fdSsyuu 1494a04f2fdSsyuu /* GMX Interrupt-Enable Registers */ 1504a04f2fdSsyuu 1514a04f2fdSsyuu #define RXN_INT_EN_XXX_63_19 0xfffffffffff80000ULL 1524a04f2fdSsyuu #define RXN_INT_EN_PHY_DUPX 0x0000000000040000ULL 1534a04f2fdSsyuu #define RXN_INT_EN_PHY_SPD 0x0000000000020000ULL 1544a04f2fdSsyuu #define RXN_INT_EN_PHY_LINK 0x0000000000010000ULL 1554a04f2fdSsyuu #define RXN_INT_EN_IFGERR 0x0000000000008000ULL 1564a04f2fdSsyuu #define RXN_INT_EN_COLDET 0x0000000000004000ULL 1574a04f2fdSsyuu #define RXN_INT_EN_FALERR 0x0000000000002000ULL 1584a04f2fdSsyuu #define RXN_INT_EN_RSVERR 0x0000000000001000ULL 1594a04f2fdSsyuu #define RXN_INT_EN_PCTERR 0x0000000000000800ULL 1604a04f2fdSsyuu #define RXN_INT_EN_OVRERR 0x0000000000000400ULL 1614a04f2fdSsyuu #define RXN_INT_EN_NIBERR 0x0000000000000200ULL 1624a04f2fdSsyuu #define RXN_INT_EN_SKPERR 0x0000000000000100ULL 1634a04f2fdSsyuu #define RXN_INT_EN_RCVERR 0x0000000000000080ULL 1644a04f2fdSsyuu #define RXN_INT_EN_LENERR 0x0000000000000040ULL 1654a04f2fdSsyuu #define RXN_INT_EN_ALNERR 0x0000000000000020ULL 1664a04f2fdSsyuu #define RXN_INT_EN_FCSERR 0x0000000000000010ULL 1674a04f2fdSsyuu #define RXN_INT_EN_JABBER 0x0000000000000008ULL 1684a04f2fdSsyuu #define RXN_INT_EN_MAXERR 0x0000000000000004ULL 1694a04f2fdSsyuu #define RXN_INT_EN_CAREXT 0x0000000000000002ULL 1704a04f2fdSsyuu #define RXN_INT_EN_MINERR 0x0000000000000001ULL 1714a04f2fdSsyuu 1724a04f2fdSsyuu /* GMX Port Configuration Registers */ 1734a04f2fdSsyuu 174e79b2291Svisa #define PRTN_CFG_XXX_63_9 0xfffffffffffffe00ULL 175e79b2291Svisa #define PRTN_CFG_SPEED_MSB 0x0000000000000100ULL 176e79b2291Svisa #define PRTN_CFG_XXX_7_4 0x00000000000000f0ULL 1774a04f2fdSsyuu #define PRTN_CFG_SLOTTIME 0x0000000000000008ULL 1784a04f2fdSsyuu #define PRTN_CFG_DUPLEX 0x0000000000000004ULL 1794a04f2fdSsyuu #define PRTN_CFG_SPEED 0x0000000000000002ULL 1804a04f2fdSsyuu #define PRTN_CFG_EN 0x0000000000000001ULL 1814a04f2fdSsyuu 1824a04f2fdSsyuu /* Frame Control Registers */ 1834a04f2fdSsyuu 1844a04f2fdSsyuu #define RXN_FRM_CTL_XXX_63_11 0xfffffffffffff800ULL 1854a04f2fdSsyuu #define RXN_FRM_CTL_NULL_DIS 0x0000000000000400ULL 1864a04f2fdSsyuu #define RXN_FRM_CTL_PRE_ALIGN 0x0000000000000200ULL 1874a04f2fdSsyuu #define RXN_FRM_CTL_PAD_LEN 0x0000000000000100ULL 1884a04f2fdSsyuu #define RXN_FRM_CTL_VLAN_LEN 0x0000000000000080ULL 1894a04f2fdSsyuu #define RXN_FRM_CTL_PRE_FREE 0x0000000000000040ULL 1904a04f2fdSsyuu #define RXN_FRM_CTL_CTL_SMAC 0x0000000000000020ULL 1914a04f2fdSsyuu #define RXN_FRM_CTL_CTL_MCST 0x0000000000000010ULL 1924a04f2fdSsyuu #define RXN_FRM_CTL_CTL_BCK 0x0000000000000008ULL 1934a04f2fdSsyuu #define RXN_FRM_CTL_CTL_DRP 0x0000000000000004ULL 1944a04f2fdSsyuu #define RXN_FRM_CTL_PRE_STRP 0x0000000000000002ULL 1954a04f2fdSsyuu #define RXN_FRM_CTL_PRE_CHK 0x0000000000000001ULL 1964a04f2fdSsyuu 1974a04f2fdSsyuu /* Frame Check Registers */ 1984a04f2fdSsyuu 1994a04f2fdSsyuu #define RXN_FRM_CKK_XXX_63_10 0xfffffffffffffc00ULL 2004a04f2fdSsyuu #define RXN_FRM_CHK_NIBERR 0x0000000000000200ULL 2014a04f2fdSsyuu #define RXN_FRM_CHK_SKPERR 0x0000000000000100ULL 2024a04f2fdSsyuu #define RXN_FRM_CHK_RCVERR 0x0000000000000080ULL 2034a04f2fdSsyuu #define RXN_FRM_CHK_LENERR 0x0000000000000040ULL 2044a04f2fdSsyuu #define RXN_FRM_CHK_ALNERR 0x0000000000000020ULL 2054a04f2fdSsyuu #define RXN_FRM_CHK_FCSERR 0x0000000000000010ULL 2064a04f2fdSsyuu #define RXN_FRM_CHK_JABBER 0x0000000000000008ULL 2074a04f2fdSsyuu #define RXN_FRM_CHK_MAXERR 0x0000000000000004ULL 2084a04f2fdSsyuu #define RXN_FRM_CHK_CAREXT 0x0000000000000002ULL 2094a04f2fdSsyuu #define RXN_FRM_CHK_MINERR 0x0000000000000001ULL 2104a04f2fdSsyuu 2114a04f2fdSsyuu /* Frame Minimum-Length Registers */ 2124a04f2fdSsyuu 2134a04f2fdSsyuu #define RXN_RRM_MIN_XXX_63_16 0xffffffffffff0000ULL 2144a04f2fdSsyuu #define RXN_RRM_MIN_LEN 0x000000000000ffffULL 2154a04f2fdSsyuu 2164a04f2fdSsyuu /* Frame Maximun-Length Registers */ 2174a04f2fdSsyuu 2184a04f2fdSsyuu #define RXN_RRM_MAX_XXX_63_16 0xffffffffffff0000ULL 2194a04f2fdSsyuu #define RXN_RRM_MAX_LEN 0x000000000000ffffULL 2204a04f2fdSsyuu 22136fd90dcSjsg /* GMX Maximum Packet-Size Registers */ 2224a04f2fdSsyuu 2234a04f2fdSsyuu #define RXN_JABBER_XXX_63_16 0xffffffffffff0000ULL 2244a04f2fdSsyuu #define RXN_JABBER_CNT 0x000000000000ffffULL 2254a04f2fdSsyuu 2264a04f2fdSsyuu /* GMX Packet Decision Registers */ 2274a04f2fdSsyuu 2284a04f2fdSsyuu #define RXN_DECISION_XXX_63_5 0xffffffffffffffe0ULL 2294a04f2fdSsyuu #define RXN_DECISION_CNT 0x000000000000001fULL 2304a04f2fdSsyuu 2314a04f2fdSsyuu /* GMX User-Defined Data Skip Registers */ 2324a04f2fdSsyuu 2334a04f2fdSsyuu #define RXN_UDD_SKP_XXX_63_9 0xfffffffffffffe00ULL 2344a04f2fdSsyuu #define RXN_UDD_SKP_FCSSEL 0x0000000000000100ULL 2354a04f2fdSsyuu #define RXN_UDD_SKP_XXX_7 0x0000000000000080ULL 2364a04f2fdSsyuu #define RXN_UDD_SKP_LEN 0x000000000000007fULL 2374a04f2fdSsyuu 2384a04f2fdSsyuu /* GMX RX Statistics Control Registers */ 2394a04f2fdSsyuu 2404a04f2fdSsyuu #define RXN_STATS_CTL_XXX_63_1 0xfffffffffffffffeULL 2414a04f2fdSsyuu #define RXN_STATS_CTL_RD_CLR 0x0000000000000001ULL 2424a04f2fdSsyuu 24336fd90dcSjsg /* GMX Minimum Interface-Gap Cycles Registers */ 2444a04f2fdSsyuu 2454a04f2fdSsyuu #define RXN_IFG_XXX_63_4 0xfffffffffffffff0ULL 2464a04f2fdSsyuu #define RXN_IFG_IFG 0x000000000000000fULL 2474a04f2fdSsyuu 2484a04f2fdSsyuu /* InBand Link Status Registers */ 2494a04f2fdSsyuu 2504a04f2fdSsyuu #define RXN_RX_INBND_XXX_63_4 0xfffffffffffffff0ULL 2514a04f2fdSsyuu #define RXN_RX_INBND_DUPLEX 0x0000000000000008ULL 2524a04f2fdSsyuu #define RXN_RX_INBND_DUPLEX_SHIFT 3 2534a04f2fdSsyuu #define RXN_RX_INBND_DUPLEX_HALF (0ULL << RXN_RX_INBND_DUPLEX_SHIFT) 2544a04f2fdSsyuu #define RXN_RX_INBND_DUPLEX_FULL (1ULL << RXN_RX_INBND_DUPLEX_SHIFT) 2554a04f2fdSsyuu #define RXN_RX_INBND_SPEED 0x0000000000000006ULL 2564a04f2fdSsyuu #define RXN_RX_INBND_SPEED_SHIFT 1 2574a04f2fdSsyuu #define RXN_RX_INBND_SPEED_2_5 (0ULL << RXN_RX_INBND_SPEED_SHIFT) 2584a04f2fdSsyuu #define RXN_RX_INBND_SPEED_25 (1ULL << RXN_RX_INBND_SPEED_SHIFT) 2594a04f2fdSsyuu #define RXN_RX_INBND_SPEED_125 (2ULL << RXN_RX_INBND_SPEED_SHIFT) 2604a04f2fdSsyuu #define RXN_RX_INBND_SPEED_XXX_3 (3ULL << RXN_RX_INBND_SPEED_SHIFT) 2614a04f2fdSsyuu #define RXN_RX_INBND_STATUS 0x0000000000000001ULL 2624a04f2fdSsyuu 2634a04f2fdSsyuu /* GMX RX Good Packets Registers */ 2644a04f2fdSsyuu 2654a04f2fdSsyuu #define RXN_STATS_PKTS_XXX_63_32 0xffffffff00000000ULL 2664a04f2fdSsyuu #define RXN_STATS_PKTS_CNT 0x00000000ffffffffULL 2674a04f2fdSsyuu 2684a04f2fdSsyuu /* GMX RX Good Packets Octet Registers */ 2694a04f2fdSsyuu 2704a04f2fdSsyuu #define RXN_STATS_OCTS_XXX_63_48 0xffff000000000000ULL 2714a04f2fdSsyuu #define RXN_STATS_OCTS_CNT 0x0000ffffffffffffULL 2724a04f2fdSsyuu 2734a04f2fdSsyuu /* GMX RX Pause Packets Registers */ 2744a04f2fdSsyuu 2754a04f2fdSsyuu #define RXN_STATS_PKTS_CTL_XXX_63_32 0xffffffff00000000ULL 2764a04f2fdSsyuu #define RXN_STATS_PKTS_CTL_CNT 0x00000000ffffffffULL 2774a04f2fdSsyuu 2784a04f2fdSsyuu /* GMX RX Pause Packets Octet Registers */ 2794a04f2fdSsyuu 2804a04f2fdSsyuu #define RXN_STATS_OCTS_CTL_XXX_63_48 0xffff000000000000ULL 2814a04f2fdSsyuu #define RXN_STATS_OCTS_CTL_CNT 0x0000ffffffffffffULL 2824a04f2fdSsyuu 2834a04f2fdSsyuu /* GMX RX DMAC Packets Registers */ 2844a04f2fdSsyuu 2854a04f2fdSsyuu #define RXN_STATS_PKTS_DMAC_XXX_63_32 0xffffffff00000000ULL 2864a04f2fdSsyuu #define RXN_STATS_PKTS_DMAC_CNT 0x00000000ffffffffULL 2874a04f2fdSsyuu 2884a04f2fdSsyuu /* GMX RX DMAC Packets Octet Registers */ 2894a04f2fdSsyuu 2904a04f2fdSsyuu #define RXN_STATS_OCTS_DMAC_XXX_63_48 0xffff000000000000ULL 2914a04f2fdSsyuu #define RXN_STATS_OCTS_DMAC_CNT 0x0000ffffffffffffULL 2924a04f2fdSsyuu 2934a04f2fdSsyuu /* GMX RX Overflow Packets Registers */ 2944a04f2fdSsyuu 2954a04f2fdSsyuu #define RXN_STATS_PKTS_DRP_XXX_63_48 0xffffffff00000000ULL 2964a04f2fdSsyuu #define RXN_STATS_PKTS_DRP_CNT 0x00000000ffffffffULL 2974a04f2fdSsyuu 2984a04f2fdSsyuu /* GMX RX Overflow Packets Octet Registers */ 2994a04f2fdSsyuu 3004a04f2fdSsyuu #define RXN_STATS_OCTS_DRP_XXX_63_48 0xffff000000000000ULL 3014a04f2fdSsyuu #define RXN_STATS_OCTS_DRP_CNT 0x0000ffffffffffffULL 3024a04f2fdSsyuu 3034a04f2fdSsyuu /* GMX RX Bad Packets Registers */ 3044a04f2fdSsyuu 3054a04f2fdSsyuu #define RXN_STATS_PKTS_BAD_XXX_63_48 0xffffffff00000000ULL 3064a04f2fdSsyuu #define RXN_STATS_PKTS_BAD_CNT 0x00000000ffffffffULL 3074a04f2fdSsyuu 3084a04f2fdSsyuu /* Address-Filtering Control Registers */ 3094a04f2fdSsyuu 3104a04f2fdSsyuu #define RXN_ADR_CTL_XXX_63_4 0xfffffffffffffff0ULL 3114a04f2fdSsyuu #define RXN_ADR_CTL_CAM_MODE 0x0000000000000008ULL 3124a04f2fdSsyuu #define RXN_ADR_CTL_CAM_MODE_SHIFT 3 3134a04f2fdSsyuu #define RXN_ADR_CTL_CAM_MODE_REJECT (0ULL << RXN_ADR_CTL_CAM_MODE_SHIFT) 3144a04f2fdSsyuu #define RXN_ADR_CTL_CAM_MODE_ACCEPT (1ULL << RXN_ADR_CTL_CAM_MODE_SHIFT) 3154a04f2fdSsyuu #define RXN_ADR_CTL_MCST 0x0000000000000006ULL 3164a04f2fdSsyuu #define RXN_ADR_CTL_MCST_SHIFT 1 3174a04f2fdSsyuu #define RXN_ADR_CTL_MCST_AFCAM (0ULL << RXN_ADR_CTL_MCST_SHIFT) 3184a04f2fdSsyuu #define RXN_ADR_CTL_MCST_REJECT (1ULL << RXN_ADR_CTL_MCST_SHIFT) 3194a04f2fdSsyuu #define RXN_ADR_CTL_MCST_ACCEPT (2ULL << RXN_ADR_CTL_MCST_SHIFT) 3204a04f2fdSsyuu #define RXN_ADR_CTL_MCST_XXX_3 (3ULL << RXN_ADR_CTL_MCST_SHIFT) 3214a04f2fdSsyuu #define RXN_ADR_CTL_BCST 0x0000000000000001ULL 3224a04f2fdSsyuu 3234a04f2fdSsyuu /* Address-Filtering Control Enable Registers */ 3244a04f2fdSsyuu 3254a04f2fdSsyuu #define RXN_ADR_CAM_EN_XXX_63_8 0xffffffffffffff00ULL 3264a04f2fdSsyuu #define RXN_ADR_CAM_EN_EN 0x00000000000000ffULL 3274a04f2fdSsyuu 3284a04f2fdSsyuu /* Address-Filtering CAM Control Registers */ 3294a04f2fdSsyuu #define RXN_ADR_CAMN_ADR 0xffffffffffffffffULL 3304a04f2fdSsyuu 3314a04f2fdSsyuu /* GMX TX Clock Generation Registers */ 3324a04f2fdSsyuu 3334a04f2fdSsyuu #define TXN_CLK_XXX_63_6 0xffffffffffffffc0ULL 3344a04f2fdSsyuu #define TXN_CLK_CLK_CNT 0x000000000000003fULL 3354a04f2fdSsyuu 3364a04f2fdSsyuu /* TX Threshold Registers */ 3374a04f2fdSsyuu 3384a04f2fdSsyuu #define TXN_THRESH_XXX_63_6 0xffffffffffffffc0ULL 3394a04f2fdSsyuu #define TXN_THRESH_CNT 0x000000000000003fULL 3404a04f2fdSsyuu 3414a04f2fdSsyuu /* TX Append Control Registers */ 3424a04f2fdSsyuu 3434a04f2fdSsyuu #define TXN_APPEND_XXX_63_4 0xfffffffffffffff0ULL 3444a04f2fdSsyuu #define TXN_APPEND_FORCE_FCS 0x0000000000000008ULL 3454a04f2fdSsyuu #define TXN_APPEND_FCS 0x0000000000000004ULL 3464a04f2fdSsyuu #define TXN_APPEND_PAD 0x0000000000000002ULL 3474a04f2fdSsyuu #define TXN_APPEND_PREAMBLE 0x0000000000000001ULL 3484a04f2fdSsyuu 3494a04f2fdSsyuu /* TX Slottime Counter Registers */ 3504a04f2fdSsyuu 3514a04f2fdSsyuu #define TXN_SLOT_XXX_63_10 0xfffffffffffffc00ULL 3524a04f2fdSsyuu #define TXN_SLOT_SLOT 0x00000000000003ffULL 3534a04f2fdSsyuu 3544a04f2fdSsyuu /* TX Burst-Counter Registers */ 3554a04f2fdSsyuu 3564a04f2fdSsyuu #define TXN_BURST_XXX_63_16 0xffffffffffff0000ULL 3574a04f2fdSsyuu #define TXN_BURST_BURST 0x000000000000ffffULL 3584a04f2fdSsyuu 3594a04f2fdSsyuu /* RGMII SMAC Registers */ 3604a04f2fdSsyuu 3614a04f2fdSsyuu #define SMACN_XXX_63_48 0xffff000000000000ULL 3624a04f2fdSsyuu #define SMACN_SMAC 0x0000ffffffffffffULL 3634a04f2fdSsyuu 3644a04f2fdSsyuu /* TX Pause Packet Pause-Time Registers */ 3654a04f2fdSsyuu 3664a04f2fdSsyuu #define TXN_PAUSE_PKT_TIME_XXX_63_16 0xffffffffffff0000ULL 3674a04f2fdSsyuu #define TXN_PAUSE_PKT_TIME_TIME 0x000000000000ffffULL 3684a04f2fdSsyuu 3694a04f2fdSsyuu /* RGMII TX Minimum-Size-Packet Registers */ 3704a04f2fdSsyuu 3714a04f2fdSsyuu #define TXN_MIN_PKT_XXX_63_8 0xffffffffffffff00ULL 3724a04f2fdSsyuu #define TXN_MIN_PKT_MIN_SIZE 0x00000000000000ffULL 3734a04f2fdSsyuu 3744a04f2fdSsyuu /* TX Pause-Packet Transmission-Interval Registers */ 3754a04f2fdSsyuu 3764a04f2fdSsyuu #define TXN_PAUSE_PKT_INTERVAL_XXX_63_16 0xffffffffffff0000ULL 3774a04f2fdSsyuu #define TXN_PAUSE_PKT_INTERVAL_INTERVAL 0x000000000000ffffULL 3784a04f2fdSsyuu 3794a04f2fdSsyuu /* TX Software-Pause Registers */ 3804a04f2fdSsyuu 3814a04f2fdSsyuu #define TXN_SOFT_PAUSE_XXX_63_16 0xffffffffffff0000ULL 3824a04f2fdSsyuu #define TXN_SOFT_PAUSE_TIME 0x000000000000ffffULL 3834a04f2fdSsyuu 3844a04f2fdSsyuu /* TX Time-to-Backpressure Registers */ 3854a04f2fdSsyuu 3864a04f2fdSsyuu #define TXN_PAUSE_TOGO_XXX_63_16 0xffffffffffff0000ULL 3874a04f2fdSsyuu #define TXN_PAUSE_TOGO_TIME 0x000000000000ffffULL 3884a04f2fdSsyuu 3894a04f2fdSsyuu /* TX Pause-Zero-Enable Registers */ 3904a04f2fdSsyuu 3914a04f2fdSsyuu #define TXN_PAUSE_ZERO_XXX_63_1 0xfffffffffffffffeULL 3924a04f2fdSsyuu #define TXN_PAUSE_ZERO_SEND 0x0000000000000001ULL 3934a04f2fdSsyuu 3944a04f2fdSsyuu /* GMX TX Statistics Control Registers */ 3954a04f2fdSsyuu 3964a04f2fdSsyuu #define TXN_STATS_CTL_XXX_63_1 0xfffffffffffffffeULL 3974a04f2fdSsyuu #define TXN_STATS_CTL_RD_CLR 0x0000000000000001ULL 3984a04f2fdSsyuu 3994a04f2fdSsyuu /* GMX TX Transmit Control Registers */ 4004a04f2fdSsyuu 4014a04f2fdSsyuu #define TXN_CTL_XXX_63_2 0xfffffffffffffffcULL 4024a04f2fdSsyuu #define TXN_CTL_XSDEF_EN 0x0000000000000002ULL 4034a04f2fdSsyuu #define TXN_CTL_XSCOL_EN 0x0000000000000001ULL 4044a04f2fdSsyuu 4054a04f2fdSsyuu /* Transmit Statistics Registers 0 */ 4064a04f2fdSsyuu 4074a04f2fdSsyuu #define TXN_STAT0_XSDEF 0xffffffff00000000ULL 4084a04f2fdSsyuu #define TXN_STAT0_XSCOL 0x00000000ffffffffULL 4094a04f2fdSsyuu 4104a04f2fdSsyuu /* Transmit Statistics Registers 1 */ 4114a04f2fdSsyuu 4124a04f2fdSsyuu #define TXN_STAT1_SCOL 0xffffffff00000000ULL 4134a04f2fdSsyuu #define TXN_STAT1_MSCOL 0x00000000ffffffffULL 4144a04f2fdSsyuu 4154a04f2fdSsyuu /* Transmit Statistics Registers 2 */ 4164a04f2fdSsyuu 4174a04f2fdSsyuu #define TXN_STAT2_XXX_63_48 0xffff000000000000ULL 4184a04f2fdSsyuu #define TXN_STAT2_OCTS 0x0000ffffffffffffULL 4194a04f2fdSsyuu 4204a04f2fdSsyuu /* Transmit Statistics Registers 3 */ 4214a04f2fdSsyuu 4224a04f2fdSsyuu #define TXN_STAT3_XXX_63_48 0xffffffff00000000ULL 4234a04f2fdSsyuu #define TXN_STAT3_PKTS 0x00000000ffffffffULL 4244a04f2fdSsyuu 4254a04f2fdSsyuu /* Transmit Statistics Registers 4 */ 4264a04f2fdSsyuu 4274a04f2fdSsyuu #define TXN_STAT4_HIST1 0xffffffff00000000ULL 4284a04f2fdSsyuu #define TXN_STAT4_HIST0 0x00000000ffffffffULL 4294a04f2fdSsyuu 4304a04f2fdSsyuu /* Transmit Statistics Registers 5 */ 4314a04f2fdSsyuu 4324a04f2fdSsyuu #define TXN_STAT5_HIST3 0xffffffff00000000ULL 4334a04f2fdSsyuu #define TXN_STAT5_HIST2 0x00000000ffffffffULL 4344a04f2fdSsyuu 4354a04f2fdSsyuu /* Transmit Statistics Registers 6 */ 4364a04f2fdSsyuu 4374a04f2fdSsyuu #define TXN_STAT6_HIST5 0xffffffff00000000ULL 4384a04f2fdSsyuu #define TXN_STAT6_HIST4 0x00000000ffffffffULL 4394a04f2fdSsyuu 4404a04f2fdSsyuu /* Transmit Statistics Registers 7 */ 4414a04f2fdSsyuu 4424a04f2fdSsyuu #define TXN_STAT7_HIST7 0xffffffff00000000ULL 4434a04f2fdSsyuu #define TXN_STAT7_HIST6 0x00000000ffffffffULL 4444a04f2fdSsyuu 4454a04f2fdSsyuu /* Transmit Statistics Registers 8 */ 4464a04f2fdSsyuu 4474a04f2fdSsyuu #define TXN_STAT8_MCST 0xffffffff00000000ULL 4484a04f2fdSsyuu #define TXN_STAT8_BCST 0x00000000ffffffffULL 4494a04f2fdSsyuu 4504a04f2fdSsyuu /* Transmit Statistics Register 9 */ 4514a04f2fdSsyuu 4524a04f2fdSsyuu #define TXN_STAT9_UNDFLW 0xffffffff00000000ULL 4534a04f2fdSsyuu #define TXN_STAT9_CTL 0x00000000ffffffffULL 4544a04f2fdSsyuu 4554a04f2fdSsyuu /* BMX BIST Results Register */ 4564a04f2fdSsyuu 4574a04f2fdSsyuu #define BIST_XXX_63_10 0xfffffffffffffc00ULL 4584a04f2fdSsyuu #define BIST_STATUS 0x00000000000003ffULL 4594a04f2fdSsyuu 4604a04f2fdSsyuu /* RX Ports Register */ 4614a04f2fdSsyuu 4624a04f2fdSsyuu #define RX_PRTS_XXX_63_3 0xfffffffffffffff8ULL 4634a04f2fdSsyuu #define RX_PRTS_PRTS 0x0000000000000007ULL 4644a04f2fdSsyuu 4654a04f2fdSsyuu /* RX FIFO Packet-Drop Registers */ 4664a04f2fdSsyuu 4674a04f2fdSsyuu #define RX_BP_DROPN_XXX_63_6 0xffffffffffffffc0ULL 4684a04f2fdSsyuu #define RX_BP_DROPN_MARK 0x000000000000003fULL 4694a04f2fdSsyuu 4704a04f2fdSsyuu /* RX Backpressure On Registers */ 4714a04f2fdSsyuu 4724a04f2fdSsyuu #define RX_BP_ONN_XXX_63_9 0xfffffffffffffe00ULL 4734a04f2fdSsyuu #define RX_BP_ONN_MARK 0x00000000000001ffULL 4744a04f2fdSsyuu 4754a04f2fdSsyuu /* RX Backpressure Off Registers */ 4764a04f2fdSsyuu 4774a04f2fdSsyuu #define RX_BP_OFFN_XXX_63_6 0xffffffffffffffc0ULL 4784a04f2fdSsyuu #define RX_BP_OFFN_MARK 0x000000000000003fULL 4794a04f2fdSsyuu 4804a04f2fdSsyuu /* TX Ports Register */ 4814a04f2fdSsyuu 4824a04f2fdSsyuu #define TX_PRTS_XXX_63_5 0xffffffffffffffe0ULL 4834a04f2fdSsyuu #define TX_PRTS_PRTS 0x000000000000001fULL 4844a04f2fdSsyuu 4854a04f2fdSsyuu /* TX Interframe Gap Register */ 4864a04f2fdSsyuu 4874a04f2fdSsyuu #define TX_IFG_XXX_63_8 0xffffffffffffff00ULL 4884a04f2fdSsyuu #define TX_IFG_IFG2 0x00000000000000f0ULL 4894a04f2fdSsyuu #define TX_IFG_IFG1 0x000000000000000fULL 4904a04f2fdSsyuu 4914a04f2fdSsyuu /* TX Jam Pattern Register */ 4924a04f2fdSsyuu 4934a04f2fdSsyuu #define TX_JAM_XXX_63_8 0xffffffffffffff00ULL 4944a04f2fdSsyuu #define TX_JAM_JAM 0x00000000000000ffULL 4954a04f2fdSsyuu 4964a04f2fdSsyuu /* TX Collision Attempts Before Dropping Frame Register */ 4974a04f2fdSsyuu 4984a04f2fdSsyuu #define TX_COL_ATTEMPT_XXX_63_5 0xffffffffffffffe0ULL 4994a04f2fdSsyuu #define TX_COL_ATTEMPT_LIMIT 0x000000000000001fULL 5004a04f2fdSsyuu 5014a04f2fdSsyuu /* TX Pause-Packet DMAC-Field Register */ 5024a04f2fdSsyuu 5034a04f2fdSsyuu #define TX_PAUSE_PKT_DMAC_XXX_63_48 0xffff000000000000ULL 5044a04f2fdSsyuu #define TX_PAUSE_PKT_DMAC_DMAC 0x0000ffffffffffffULL 5054a04f2fdSsyuu 5064a04f2fdSsyuu /* TX Pause Packet Type Field Register */ 5074a04f2fdSsyuu 5084a04f2fdSsyuu #define TX_PAUSE_PKT_TYPE_XXX_63_16 0xffffffffffff0000ULL 5094a04f2fdSsyuu #define TX_PAUSE_PKT_TYPE_TYPE 0x000000000000ffffULL 5104a04f2fdSsyuu 5114a04f2fdSsyuu /* TX Override Backpressure Register */ 5124a04f2fdSsyuu 5134a04f2fdSsyuu #define TX_OVR_BP_XXX_63_12 0xfffffffffffff000ULL 5144a04f2fdSsyuu #define TX_OVR_BP_XXX_11 0x0000000000000800ULL 5154a04f2fdSsyuu #define TX_OVR_BP_EN 0x0000000000000700ULL 5164a04f2fdSsyuu #define TX_OVR_BP_EN_SHIFT 8 5174a04f2fdSsyuu #define TX_OVR_BP_XXX_7 0x0000000000000080ULL 5184a04f2fdSsyuu #define TX_OVR_BP_BP 0x0000000000000070ULL 5194a04f2fdSsyuu #define TX_OVR_BP_BP_SHIFT 4 5204a04f2fdSsyuu #define TX_OVR_BP_XXX_3 0x0000000000000008ULL 5214a04f2fdSsyuu #define TX_OVR_BP_IGN_FULL 0x0000000000000007ULL 5224a04f2fdSsyuu #define TX_OVR_BP_IGN_FULL_SHIFT 0 5234a04f2fdSsyuu 5244a04f2fdSsyuu /* TX Override Backpressure Register */ 5254a04f2fdSsyuu 5264a04f2fdSsyuu #define TX_OVR_BP_XXX_63_12 0xfffffffffffff000ULL 5274a04f2fdSsyuu #define TX_OVR_BP_XXX_11 0x0000000000000800ULL 5284a04f2fdSsyuu #define TX_OVR_BP_EN 0x0000000000000700ULL 5294a04f2fdSsyuu #define TX_OVR_BP_XXX_7 0x0000000000000080ULL 5304a04f2fdSsyuu #define TX_OVR_BP_BP 0x0000000000000070ULL 5314a04f2fdSsyuu #define TX_OVR_BP_XXX_3 0x0000000000000008ULL 5324a04f2fdSsyuu #define TX_OVR_BP_IGN_FULL 0x0000000000000007ULL 5334a04f2fdSsyuu 5344a04f2fdSsyuu /* TX Backpressure Status Register */ 5354a04f2fdSsyuu 5364a04f2fdSsyuu #define TX_BP_SR_XXX_63_3 0xfffffffffffffff8ULL 5374a04f2fdSsyuu #define TX_BP_SR_BP 0x0000000000000007ULL 5384a04f2fdSsyuu 5394a04f2fdSsyuu /* TX Corrupt Packets Register */ 5404a04f2fdSsyuu 5414a04f2fdSsyuu #define TX_CORRUPT_XXX_63_3 0xfffffffffffffff8ULL 5424a04f2fdSsyuu #define TX_CORRUPT_CORRUPT 0x0000000000000007ULL 5434a04f2fdSsyuu 5444a04f2fdSsyuu /* RX Port State Information Register */ 5454a04f2fdSsyuu 5464a04f2fdSsyuu #define RX_PRT_INFO_XXX_63_19 0xfffffffffff80000ULL 5474a04f2fdSsyuu #define RX_PRT_INFO_DROP 0x0000000000070000ULL 5484a04f2fdSsyuu #define RX_PRT_INFO_XXX_15_3 0x000000000000fff8ULL 5494a04f2fdSsyuu #define RX_PRT_INFO_COMMIT 0x0000000000000007ULL 5504a04f2fdSsyuu 5514a04f2fdSsyuu /* TX LFSR Register */ 5524a04f2fdSsyuu 5534a04f2fdSsyuu #define TX_LFSR_XXX_63_16 0xffffffffffff0000ULL 5544a04f2fdSsyuu #define TX_LFSR_LFSR 0x000000000000ffffULL 5554a04f2fdSsyuu 5564a04f2fdSsyuu /* TX Interrupt Register */ 5574a04f2fdSsyuu 5584a04f2fdSsyuu #define TX_INT_REG_XXX_63_20 0xfffffffffff00000ULL 5594a04f2fdSsyuu #define TX_INT_REG_XXX_19 0x0000000000080000ULL 5604a04f2fdSsyuu #define TX_INT_REG_LATE_COL 0x0000000000070000ULL 5614a04f2fdSsyuu #define TX_INT_REG_XXX_15 0x0000000000008000ULL 5624a04f2fdSsyuu #define TX_INT_REG_XSDEF 0x0000000000007000ULL 5634a04f2fdSsyuu #define TX_INT_REG_XXX_11 0x0000000000000800ULL 5644a04f2fdSsyuu #define TX_INT_REG_XSCOL 0x0000000000000700ULL 5654a04f2fdSsyuu #define TX_INT_REG_XXX_7_5 0x00000000000000e0ULL 5664a04f2fdSsyuu #define TX_INT_REG_UNDFLW 0x000000000000001cULL 5674a04f2fdSsyuu #define TX_INT_REG_XXX_1 0x0000000000000002ULL 5684a04f2fdSsyuu #define TX_INT_REG_PKO_NXA 0x0000000000000001ULL 5694a04f2fdSsyuu 5704a04f2fdSsyuu /* TX Interrupt Register */ 5714a04f2fdSsyuu 5724a04f2fdSsyuu #define TX_INT_EN_XXX_63_20 0xfffffffffff00000ULL 5734a04f2fdSsyuu #define TX_INT_EN_XXX_19 0x0000000000080000ULL 5744a04f2fdSsyuu #define TX_INT_EN_LATE_COL 0x0000000000070000ULL 5754a04f2fdSsyuu #define TX_INT_EN_XXX_15 0x0000000000008000ULL 5764a04f2fdSsyuu #define TX_INT_EN_XSDEF 0x0000000000007000ULL 5774a04f2fdSsyuu #define TX_INT_EN_XXX_11 0x0000000000000800ULL 5784a04f2fdSsyuu #define TX_INT_EN_XSCOL 0x0000000000000700ULL 5794a04f2fdSsyuu #define TX_INT_EN_XXX_7_5 0x00000000000000e0ULL 5804a04f2fdSsyuu #define TX_INT_EN_UNDFLW 0x000000000000001cULL 5814a04f2fdSsyuu #define TX_INT_EN_XXX_1 0x0000000000000002ULL 5824a04f2fdSsyuu #define TX_INT_EN_PKO_NXA 0x0000000000000001ULL 5834a04f2fdSsyuu 5844a04f2fdSsyuu /* Address-out-of-Range Error Register */ 5854a04f2fdSsyuu 5864a04f2fdSsyuu #define NXA_ADR_XXX_63_6 0xffffffffffffffc0ULL 5874a04f2fdSsyuu #define NXA_ADR_PRT 0x000000000000003fULL 5884a04f2fdSsyuu 5894a04f2fdSsyuu /* GMX Miscellaneous Error Register */ 5904a04f2fdSsyuu 5914a04f2fdSsyuu #define BAD_REG_XXX_63_31 0xffffffff80000000ULL 5924a04f2fdSsyuu #define BAD_REG_INB_NXA 0x0000000078000000ULL 5934a04f2fdSsyuu #define BAD_REG_STATOVR 0x0000000004000000ULL 5944a04f2fdSsyuu #define BAD_REG_XXX_25 0x0000000002000000ULL 5954a04f2fdSsyuu #define BAD_REG_LOSTSTAT 0x0000000001c00000ULL 5964a04f2fdSsyuu #define BAD_REG_XXX_21_18 0x00000000003c0000ULL 5974a04f2fdSsyuu #define BAD_REG_XXX_17_5 0x000000000003ffe0ULL 5984a04f2fdSsyuu #define BAD_REG_OUT_OVR 0x000000000000001cULL 5994a04f2fdSsyuu #define BAD_REG_XXX_1_0 0x0000000000000003ULL 6004a04f2fdSsyuu 6014a04f2fdSsyuu /* GMX Backpressure Statistics Register */ 6024a04f2fdSsyuu 6034a04f2fdSsyuu #define STAT_BP_XXX_63_17 0xfffffffffffe0000ULL 6044a04f2fdSsyuu #define STAT_BP_BP 0x0000000000010000ULL 6054a04f2fdSsyuu #define STAT_BP_CNT 0x000000000000ffffULL 6064a04f2fdSsyuu 6074a04f2fdSsyuu /* Mode Change Mask Registers */ 6084a04f2fdSsyuu 6094a04f2fdSsyuu #define TX_CLK_MSKN_XXX_63_1 0xfffffffffffffffeULL 6104a04f2fdSsyuu #define TX_CLK_MSKN_MSK 0x0000000000000001ULL 6114a04f2fdSsyuu 6124a04f2fdSsyuu /* GMX RX/TX Status Register */ 6134a04f2fdSsyuu 6144a04f2fdSsyuu #define RX_TX_STATUS_XXX_63_7 0xffffffffffffff80ULL 6154a04f2fdSsyuu #define RX_TX_STATUS_TX 0x0000000000000070ULL 6164a04f2fdSsyuu #define RX_TX_STATUS_XXX_3 0x0000000000000008ULL 6174a04f2fdSsyuu #define RX_TX_STATUS_RX 0x0000000000000007ULL 6184a04f2fdSsyuu 6194a04f2fdSsyuu /* Interface Mode Register */ 6204a04f2fdSsyuu 6214a04f2fdSsyuu #define INF_MODE_XXX_63_3 0xfffffffffffffff8ULL 6224a04f2fdSsyuu #define INF_MODE_P0MII 0x0000000000000004ULL 6234a04f2fdSsyuu #define INF_MODE_EN 0x0000000000000002ULL 6244a04f2fdSsyuu #define INF_MODE_TYPE 0x0000000000000001ULL 6254a04f2fdSsyuu 626204304b2Svisa /* Interface mode, applicable on CN68xx and CN7xxx (?) */ 627204304b2Svisa #define INF_MODE_MODE 0x0000000000000070ULL 628204304b2Svisa #define INF_MODE_MODE_SGMII 0x0000000000000020ULL 629204304b2Svisa #define INF_MODE_MODE_XAUI 0x0000000000000030ULL 630204304b2Svisa 631e79b2291Svisa #define MIO_QLM_CFG(x) (0x0001180000001590ULL + (x)*8) 632e79b2291Svisa 633e79b2291Svisa #define MIO_QLM_CFG_CFG 0x000000000000000fULL 634e79b2291Svisa 6354a04f2fdSsyuu /* -------------------------------------------------------------------------- */ 6364a04f2fdSsyuu 6374a04f2fdSsyuu /* for bus_space(9) */ 6384a04f2fdSsyuu 639959570ccSvisa #define GMX_PORT_NUNITS (3 * 16) 640959570ccSvisa #define GMX_PORT_NUM(g, i) ((g) * 16 + (i)) 641959570ccSvisa #define GMX_PORT_IFACE(port) ((port) / 16) 642959570ccSvisa #define GMX_PORT_INDEX(port) ((port) % 16) 643959570ccSvisa 644959570ccSvisa #define GMX_BLOCK_SIZE 0x8000000 6454a04f2fdSsyuu 6464a04f2fdSsyuu #define GMX0_BASE_PORT0 0x0001180008000000ULL 6474a04f2fdSsyuu #define GMX0_BASE_PORT1 0x0001180008000800ULL 6484a04f2fdSsyuu #define GMX0_BASE_PORT2 0x0001180008001000ULL 6494a04f2fdSsyuu #define GMX0_BASE_PORT_SIZE 0x00800 6504a04f2fdSsyuu #define GMX0_BASE_IF0 0x0001180008000000ULL 651e79b2291Svisa #define GMX0_BASE_IF_SIZE(n) (GMX0_BASE_PORT_SIZE * (n)) 652e79b2291Svisa 653ef1f2cdcSvisa #define AGL_BASE 0x00011800e0000000ULL 654ef1f2cdcSvisa #define AGL_SIZE 0x4000 655ef1f2cdcSvisa 656ef1f2cdcSvisa #define AGL_GMX_PRT_CFG 0x0010 657ef1f2cdcSvisa #define AGL_GMX_PRT_CFG_TX_IDLE 0x0000000000002000ULL 658ef1f2cdcSvisa #define AGL_GMX_PRT_CFG_RX_IDLE 0x0000000000001000ULL 659ef1f2cdcSvisa #define AGL_GMX_PRT_CFG_SPEED_MSB 0x0000000000000100ULL 660ef1f2cdcSvisa #define AGL_GMX_PRT_CFG_BURST 0x0000000000000040ULL 661ef1f2cdcSvisa #define AGL_GMX_PRT_CFG_TX_EN 0x0000000000000020ULL 662ef1f2cdcSvisa #define AGL_GMX_PRT_CFG_RX_EN 0x0000000000000010ULL 663ef1f2cdcSvisa #define AGL_GMX_PRT_CFG_SLOTTIME 0x0000000000000008ULL 664ef1f2cdcSvisa #define AGL_GMX_PRT_CFG_DUPLEX 0x0000000000000004ULL 665ef1f2cdcSvisa #define AGL_GMX_PRT_CFG_SPEED 0x0000000000000002ULL 666ef1f2cdcSvisa #define AGL_GMX_PRT_CFG_EN 0x0000000000000001ULL 667ef1f2cdcSvisa 668ef1f2cdcSvisa #define AGL_GMX_RX_FRM_CTL 0x0018 669ef1f2cdcSvisa #define AGL_GMX_RX_FRM_CTL_PRE_ALIGN 0x0000000000000200ULL 670ef1f2cdcSvisa #define AGL_GMX_RX_FRM_CTL_PAD_LEN 0x0000000000000100ULL 671ef1f2cdcSvisa #define AGL_GMX_RX_FRM_CTL_VLAN_LEN 0x0000000000000080ULL 672ef1f2cdcSvisa #define AGL_GMX_RX_FRM_CTL_PRE_FREE 0x0000000000000040ULL 673ef1f2cdcSvisa #define AGL_GMX_RX_FRM_CTL_SMAC 0x0000000000000020ULL 674ef1f2cdcSvisa #define AGL_GMX_RX_FRM_CTL_MCST 0x0000000000000010ULL 675ef1f2cdcSvisa #define AGL_GMX_RX_FRM_CTL_BCK 0x0000000000000008ULL 676ef1f2cdcSvisa #define AGL_GMX_RX_FRM_CTL_DRP 0x0000000000000004ULL 677ef1f2cdcSvisa #define AGL_GMX_RX_FRM_CTL_PRE_STRP 0x0000000000000002ULL 678ef1f2cdcSvisa #define AGL_GMX_RX_FRM_CTL_PRE_CHK 0x0000000000000001ULL 679ef1f2cdcSvisa 680ef1f2cdcSvisa #define AGL_GMX_RX_FRM_MAX 0x0030 681ef1f2cdcSvisa #define AGL_GMX_RX_JABBER 0x0038 682ef1f2cdcSvisa 683ef1f2cdcSvisa #define AGL_GMX_TX_CLK 0x0208 684ef1f2cdcSvisa #define AGL_GMX_TX_CLK_CLK_CNT_M 0x000000000000003fULL 685ef1f2cdcSvisa #define AGL_GMX_TX_CLK_CLK_CNT_S 0 686ef1f2cdcSvisa 687ef1f2cdcSvisa #define AGL_PRT_CTL(i) (0x2000 + (i) * 8) 688ef1f2cdcSvisa #define AGL_PRT_CTL_DRV_BYP 0x8000000000000000ULL 689ef1f2cdcSvisa #define AGL_PRT_CTL_CLK_SET_M 0x000000007f000000ULL 690ef1f2cdcSvisa #define AGL_PRT_CTL_CLKRX_BYP 0x0000000000800000ULL 691ef1f2cdcSvisa #define AGL_PRT_CTL_CLKRX_SET_M 0x00000000007f0000ULL 692ef1f2cdcSvisa #define AGL_PRT_CTL_CLKTX_BYP 0x0000000000008000ULL 693ef1f2cdcSvisa #define AGL_PRT_CTL_CLKTX_SET_M 0x0000000000007f00ULL 694ef1f2cdcSvisa #define AGL_PRT_CTL_REFCLK_SEL_M 0x00000000000000c0ULL 695ef1f2cdcSvisa #define AGL_PRT_CTL_DLLRST 0x0000000000000010ULL 696ef1f2cdcSvisa #define AGL_PRT_CTL_COMP 0x0000000000000008ULL 697ef1f2cdcSvisa #define AGL_PRT_CTL_ENABLE 0x0000000000000004ULL 698ef1f2cdcSvisa #define AGL_PRT_CTL_CLKRST 0x0000000000000002ULL 699ef1f2cdcSvisa #define AGL_PRT_CTL_MODE_M 0x0000000000000001ULL 700ef1f2cdcSvisa #define AGL_PRT_CTL_MODE_RGMII 0x0000000000000000ULL 701ef1f2cdcSvisa 702e79b2291Svisa /* -------------------------------------------------------------------------- */ 703e79b2291Svisa 704e79b2291Svisa /* Low-level SGMII link control */ 705e79b2291Svisa 7066a26a470Svisa #define PCS_BASE(g, i) (0x00011800b0001000ULL + 0x8000000 * (g) + 0x400 * (i)) 707e79b2291Svisa #define PCS_SIZE 0x98 708e79b2291Svisa 709e79b2291Svisa #define PCS_MR_CONTROL 0x00 710e79b2291Svisa #define PCS_MR_STATUS 0x08 711e79b2291Svisa #define PCS_LINK_TIMER_COUNT 0x40 712e79b2291Svisa #define PCS_MISC_CTL 0x78 713e79b2291Svisa 714e79b2291Svisa #define PCS_MR_CONTROL_RES_16_63 0xffffffffffff0000ULL 715e79b2291Svisa #define PCS_MR_CONTROL_RESET 0x0000000000008000ULL 716e79b2291Svisa #define PCS_MR_CONTROL_LOOPBCK1 0x0000000000004000ULL 717e79b2291Svisa #define PCS_MR_CONTROL_SPDLSB 0x0000000000002000ULL 718e79b2291Svisa #define PCS_MR_CONTROL_AN_EN 0x0000000000001000ULL 719e79b2291Svisa #define PCS_MR_CONTROL_PWR_DN 0x0000000000000800ULL 720e79b2291Svisa #define PCS_MR_CONTROL_RES_10_10 0x0000000000000400ULL 721e79b2291Svisa #define PCS_MR_CONTROL_RST_AN 0x0000000000000200ULL 722e79b2291Svisa #define PCS_MR_CONTROL_DUPLEX 0x0000000000000100ULL 723e79b2291Svisa #define PCS_MR_CONTROL_COLTST 0x0000000000000080ULL 724e79b2291Svisa #define PCS_MR_CONTROL_SPDMSB 0x0000000000000040ULL 725e79b2291Svisa #define PCS_MR_CONTROL_UNI 0x0000000000000020ULL 726e79b2291Svisa #define PCS_MR_CONTROL_RES_0_4 0x000000000000001fULL 727e79b2291Svisa 728e79b2291Svisa #define PCS_MR_STATUS_RES_16_63 0xffffffffffff0000ULL 729e79b2291Svisa #define PCS_MR_STATUS_HUN_T4 0x0000000000008000ULL 730e79b2291Svisa #define PCS_MR_STATUS_HUN_XFD 0x0000000000004000ULL 731e79b2291Svisa #define PCS_MR_STATUS_HUN_XHD 0x0000000000002000ULL 732e79b2291Svisa #define PCS_MR_STATUS_TEN_FD 0x0000000000001000ULL 733e79b2291Svisa #define PCS_MR_STATUS_TEN_HD 0x0000000000000800ULL 734e79b2291Svisa #define PCS_MR_STATUS_HUN_T2FD 0x0000000000000400ULL 735e79b2291Svisa #define PCS_MR_STATUS_HUN_T2HD 0x0000000000000200ULL 736e79b2291Svisa #define PCS_MR_STATUS_EXT_ST 0x0000000000000100ULL 737e79b2291Svisa #define PCS_MR_STATUS_RES_7_7 0x0000000000000080ULL 738e79b2291Svisa #define PCS_MR_STATUS_PRB_SUP 0x0000000000000040ULL 739e79b2291Svisa #define PCS_MR_STATUS_AN_CPT 0x0000000000000020ULL 740e79b2291Svisa #define PCS_MR_STATUS_RM_FLT 0x0000000000000010ULL 741e79b2291Svisa #define PCS_MR_STATUS_AN_ABIL 0x0000000000000008ULL 742e79b2291Svisa #define PCS_MR_STATUS_LNK_ST 0x0000000000000004ULL 743e79b2291Svisa #define PCS_MR_STATUS_RES_1_1 0x0000000000000002ULL 744e79b2291Svisa #define PCS_MR_STATUS_EXTND 0x0000000000000001ULL 745e79b2291Svisa 746e79b2291Svisa #define PCS_LINK_TIMER_COUNT_MASK 0x000000000000ffffULL 747e79b2291Svisa 748e79b2291Svisa #define PCS_MISC_CTL_SGMII 0x0000000000001000ULL 749e79b2291Svisa #define PCS_MISC_CTL_GMXENO 0x0000000000000800ULL 750e79b2291Svisa #define PCS_MISC_CTL_LOOPBCK2 0x0000000000000400ULL 751e79b2291Svisa #define PCS_MISC_CTL_MAC_PHY 0x0000000000000200ULL 752e79b2291Svisa #define PCS_MISC_CTL_MODE 0x0000000000000100ULL 753e79b2291Svisa #define PCS_MISC_CTL_AN_OVRD 0x0000000000000080ULL 754e79b2291Svisa #define PCS_MISC_CTL_SAMP_PT 0x000000000000007fULL 7554a04f2fdSsyuu 7564a04f2fdSsyuu #endif /* _CN30XXGMXREG_H_ */ 757