1 /* $OpenBSD: ogxreg.h,v 1.1 2019/11/04 14:58:40 visa Exp $ */ 2 3 /* 4 * Copyright (c) 2019 Visa Hankala 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _OGXREG_H_ 20 #define _OGXREG_H_ 21 22 #define BGX_CMR_CONFIG 0x00000 23 #define BGX_CMR_CONFIG_ENABLE 0x0000000000008000ULL 24 #define BGX_CMR_CONFIG_DATA_PKT_RX_EN 0x0000000000004000ULL 25 #define BGX_CMR_CONFIG_DATA_PKT_TX_EN 0x0000000000002000ULL 26 #define BGX_CMR_CONFIG_INT_BEAT_GEN 0x0000000000001000ULL 27 #define BGX_CMR_CONFIG_MIX_EN 0x0000000000000800ULL 28 #define BGX_CMR_CONFIG_LMAC_TYPE_M 0x0000000000000700ULL 29 #define BGX_CMR_CONFIG_LMAC_TYPE_S 8 30 #define BGX_CMR_CONFIG_LANE_TO_SDS 0x00000000000000ffULL 31 32 #define BGX_CMR_RX_ID_MAP 0x00028 33 #define BGX_CMR_RX_ID_MAP_RID_M 0x0000000000007f00ULL 34 #define BGX_CMR_RX_ID_MAP_RID_S 8 35 #define BGX_CMR_RX_ID_MAP_PKND_M 0x00000000000000ffULL 36 #define BGX_CMR_RX_ID_MAP_PKND_S 0 37 38 #define BGX_CMR_RX_ADR_CTL 0x000a0 39 #define BGX_CMR_RX_ADR_CTL_CAM_ACCEPT 0x0000000000000008ULL 40 #define BGX_CMR_RX_ADR_CTL_MCST_MODE 0x0000000000000006ULL 41 #define BGX_CMR_RX_ADR_CTL_MCST_MODE_ALL 0x0000000000000002ULL 42 #define BGX_CMR_RX_ADR_CTL_MCST_MODE_CAM 0x0000000000000004ULL 43 #define BGX_CMR_RX_ADR_CTL_BCST_ACCEPT 0x0000000000000001ULL 44 45 #define BGX_CMR_RX_FIFO_LEN 0x000c0 46 47 #define BGX_CMR_RX_ADR_CAM(i) (0x00100 + (i) * 8) 48 #define BGX_CMR_RX_ADR_CAM_ID 0x0030000000000000ULL 49 #define BGX_CMR_RX_ADR_CAM_ID_S 52 50 #define BGX_CMR_RX_ADR_CAM_EN 0x0001000000000000ULL 51 #define BGX_CMR_RX_ADR_CAM_ADR 0x0000ffffffffffffULL 52 53 #define BGX_CMR_CHAN_MSK_AND 0x00200 54 #define BGX_CMR_CHAN_MSK_OR 0x00208 55 56 #define BGX_CMR_RX_LMACS 0x00308 57 58 #define BGX_CMR_TX_FIFO_LEN 0x00418 59 60 #define BGX_CMR_TX_LMACS 0x01000 61 #define BGX_CMR_TX_LMACS_NUM_M 0x0000000000000007ULL 62 #define BGX_CMR_TX_LMACS_NUM_S 0 63 64 #define BGX_GMP_PCS_MR_CONTROL 0x30000 65 #define BGX_GMP_PCS_MR_CONTROL_RESET 0x0000000000008000ULL 66 #define BGX_GMP_PCS_MR_CONTROL_LOOPBCK1 0x0000000000004000ULL 67 #define BGX_GMP_PCS_MR_CONTROL_SPDLSB 0x0000000000002000ULL 68 #define BGX_GMP_PCS_MR_CONTROL_AN_EN 0x0000000000001000ULL 69 #define BGX_GMP_PCS_MR_CONTROL_PWR_DN 0x0000000000000800ULL 70 #define BGX_GMP_PCS_MR_CONTROL_RST_AN 0x0000000000000200ULL 71 #define BGX_GMP_PCS_MR_CONTROL_DUP 0x0000000000000100ULL 72 #define BGX_GMP_PCS_MR_CONTROL_COLTST 0x0000000000000080ULL 73 #define BGX_GMP_PCS_MR_CONTROL_SPDMSB 0x0000000000000040ULL 74 #define BGX_GMP_PCS_MR_CONTROL_UNI 0x0000000000000020ULL 75 76 #define BGX_GMP_PCS_MR_STATUS 0x30008 77 #define BGX_GMP_PCS_MR_STATUS_AN_CPT 0x0000000000000020ULL 78 79 #define BGX_GMP_PCS_LINK_TIMER 0x30040 80 #define BGX_GMP_PCS_LINK_TIMER_COUNT_M 0x000000000000ffffULL 81 82 #define BGX_GMP_PCS_RX_SYNC 0x30050 83 84 #define BGX_GMP_SGM_LP_ADV 0x30070 85 86 #define BGX_GMP_PCS_MISC_CTL 0x30078 87 #define BGX_GMP_PCS_MISC_CTL_SGMII 0x0000000000001000ULL 88 #define BGX_GMP_PCS_MISC_CTL_GMXENO 0x0000000000000800ULL 89 #define BGX_GMP_PCS_MISC_CTL_LOOPBCK2 0x0000000000000400ULL 90 #define BGX_GMP_PCS_MISC_CTL_MAC_PHY 0x0000000000000200ULL 91 #define BGX_GMP_PCS_MISC_CTL_MODE 0x0000000000000100ULL 92 #define BGX_GMP_PCS_MISC_CTL_AN_OVRD 0x0000000000000080ULL 93 #define BGX_GMP_PCS_MISC_CTL_SAMP_PT_M 0x000000000000007fULL 94 #define BGX_GMP_PCS_MISC_CTL_SAMP_PT_S 0 95 96 #define BGX_GMP_PCS_INT 0x30080 97 98 #define BGX_GMP_GMI_PRT_CFG 0x38010 99 #define BGX_GMP_GMI_PRT_CFG_TX_IDLE 0x0000000000002000ULL 100 #define BGX_GMP_GMI_PRT_CFG_RX_IDLE 0x0000000000001000ULL 101 #define BGX_GMP_GMI_PRT_CFG_SPEED_MSB 0x0000000000000100ULL 102 #define BGX_GMP_GMI_PRT_CFG_SLOTTIME 0x0000000000000008ULL 103 #define BGX_GMP_GMI_PRT_CFG_DUPLEX 0x0000000000000004ULL 104 #define BGX_GMP_GMI_PRT_CFG_SPEED 0x0000000000000002ULL 105 106 #define BGX_GMP_GMI_TX_THRESH 0x38210 107 #define BGX_GMP_GMI_TX_THRESH_M 0x00000000000007ffULL 108 109 #define BGX_GMP_GMI_TX_APPEND 0x38218 110 #define BGX_GMP_GMI_TX_APPEND_FORCE_FCS 0x0000000000000008ULL 111 #define BGX_GMP_GMI_TX_APPEND_FCS 0x0000000000000004ULL 112 #define BGX_GMP_GMI_TX_APPEND_PAD 0x0000000000000002ULL 113 #define BGX_GMP_GMI_TX_APPEND_PREAMBLE 0x0000000000000001ULL 114 115 #define BGX_GMP_GMI_TX_SLOT 0x38220 116 #define BGX_GMP_GMI_TX_SLOT_M 0x000000000000ffffULL 117 118 #define BGX_GMP_GMI_TX_BURST 0x38228 119 #define BGX_GMP_GMI_TX_BURST_M 0x000000000000ffffULL 120 121 #define BGX_GMP_GMI_TX_MIN_PKT 0x38240 122 #define BGX_GMP_GMI_TX_MIN_PKT_M 0x00000000000000ffULL 123 124 #define BGX_GMP_GMI_TX_SGMII_CTL 0x38300 125 #define BGX_GMP_GMI_TX_SGMII_CTL_ALIGN 0x0000000000000001ULL 126 127 #define FPA3_BASE 0x0001280000000000ULL 128 #define FPA3_SIZE 0x0000000100000000ULL 129 130 #define FPA3_LD_IO 0x0001000000000000ULL 131 #define FPA3_LD_DID 0x0000290000000000ULL 132 #define FPA3_LD_NODE_M 0x000000f000000000ULL 133 #define FPA3_LD_NODE_S 36 134 #define FPA3_LD_RED 0x0000000800000000ULL 135 #define FPA3_LD_AURA_M 0x0000000003ff0000ULL 136 #define FPA3_LD_AURA_S 16 137 138 #define FPA3_ST_IO 0x0001000000000000ULL 139 #define FPA3_ST_DID_FPA 0x0000290000000000ULL 140 #define FPA3_ST_DID_M 0x0000ff0000000000ULL 141 #define FPA3_ST_NODE_M 0x000000f000000000ULL 142 #define FPA3_ST_NODE_S 36 143 #define FPA3_ST_AURA_M 0x0000000003ff0000ULL 144 #define FPA3_ST_AURA_S 16 145 #define FPA3_ST_FABS 0x0000000000008000ULL 146 #define FPA3_ST_DWB_COUNT_M 0x0000000000000ff8ULL 147 #define FPA3_ST_DWB_COUNT_S 3 148 149 #define FPA3_POOL_CFG(i) (0x10000000ULL + (i) * 8) 150 #define FPA3_POOL_CFG_ENA 0x0000000000000001ULL 151 #define FPA3_POOL_START_ADDR(i) (0x10500000ULL + (i) * 8) 152 #define FPA3_POOL_END_ADDR(i) (0x10600000ULL + (i) * 8) 153 #define FPA3_POOL_STACK_BASE(i) (0x10700000ULL + (i) * 8) 154 #define FPA3_POOL_STACK_END(i) (0x10800000ULL + (i) * 8) 155 #define FPA3_POOL_STACK_ADDR(i) (0x10900000ULL + (i) * 8) 156 157 #define FPA3_AURA_POOL(i) (0x20000000ULL + (i) * 8) 158 #define FPA3_AURA_CFG(i) (0x20100000ULL + (i) * 8) 159 #define FPA3_AURA_CNT(i) (0x20200000ULL + (i) * 8) 160 #define FPA3_AURA_CNT_LIMIT(i) (0x20400000ULL + (i) * 8) 161 #define FPA3_AURA_CNT_THRESHOLD(i) (0x20500000ULL + (i) * 8) 162 #define FPA3_AURA_CNT_INT(i) (0x20600000ULL + (i) * 8) 163 #define FPA3_AURA_POOL_LEVELS(i) (0x20700000ULL + (i) * 8) 164 #define FPA3_AURA_CNT_LEVELS(i) (0x20800000ULL + (i) * 8) 165 166 /* 167 * PKO3 registers 168 */ 169 170 #define PKO3_BASE 0x0001540000000000ULL 171 #define PKO3_SIZE 0x0000000001000000ULL 172 173 #define PKO3_LD_IO 0x0001000000000000ULL 174 #define PKO3_LD_DID 0x0000510000000000ULL 175 #define PKO3_LD_NODE_M 0x000000f000000000ULL 176 #define PKO3_LD_NODE_S 36 177 #define PKO3_LD_OP_M 0x0000000300000000ULL 178 #define PKO3_LD_OP_S 32 179 #define PKO3_LD_DQ_M 0x0000000003ff0000ULL 180 #define PKO3_LD_DQ_S 16 181 182 #define PKO3_CHANNEL_LEVEL (0x000800f0ULL) 183 184 #define PKO3_L1_SQ_SHAPE(i) (0x00000010ULL + (i) * 512) 185 #define PKO3_L1_SQ_SHAPE_LINK_M 0x000000000003e000ULL 186 #define PKO3_L1_SQ_SHAPE_LINK_S 13 187 188 #define PKO3_L2_SQ_SHAPE(i) (0x00080010ULL + (i) * 512) 189 #define PKO3_L3_SQ_SHAPE(i) (0x00100010ULL + (i) * 512) 190 191 #define PKO3_L1_SQ_LINK(i) (0x00000038ULL + (i) * 512) 192 #define PKO3_L1_SQ_LINK_LINK_M 0x0001f00000000000ULL 193 #define PKO3_L1_SQ_LINK_LINK_S 44 194 #define PKO3_L1_SQ_LINK_CC_WORD_CNT_M 0x00000000fffff000ULL 195 #define PKO3_L1_SQ_LINK_CC_WORD_CNT_S 12 196 #define PKO3_L1_SQ_LINK_CC_PACKET_CNT_M 0x0000000000000ffcULL 197 #define PKO3_L1_SQ_LINK_CC_PACKET_CNT_S 2 198 #define PKO3_L1_SQ_LINK_CC_ENABLE 0x0000000000000002ULL 199 200 #define PKO3_DQ_WM_CTL(i) (0x00000040ULL + (i) * 512) 201 #define PKO3_DQ_WM_CTL_KIND 0x0002000000000000ULL 202 203 #define PKO3_L1_SQ_SW_XOFF(i) (0x000000e0ULL + (i) * 512) 204 #define PKO3_DQ_SW_XOFF(i) (0x002800e0ULL + (i) * 512) 205 #define PKO3_LX_SQ_SW_XOFF_DRAIN_NULL_LINK 0x0000000000000004ULL 206 #define PKO3_LX_SQ_SW_XOFF_DRAIN 0x0000000000000002ULL 207 208 #define PKO3_L1_SQ_SCHEDULE(i) (0x00000008ULL + (i) * 512) 209 #define PKO3_L2_SQ_SCHEDULE(i) (0x00080008ULL + (i) * 512) 210 #define PKO3_L3_SQ_SCHEDULE(i) (0x00100008ULL + (i) * 512) 211 #define PKO3_L4_SQ_SCHEDULE(i) (0x00180008ULL + (i) * 512) 212 #define PKO3_L5_SQ_SCHEDULE(i) (0x00200008ULL + (i) * 512) 213 #define PKO3_DQ_SCHEDULE(i) (0x00280008ULL + (i) * 512) 214 #define PKO3_LX_SQ_SCHEDULE_PRIO_M 0x000000000f000000ULL 215 #define PKO3_LX_SQ_SCHEDULE_PRIO_S 24 216 #define PKO3_LX_SQ_SCHEDULE_RR_QUANTUM_M 0x0000000000ffffffULL 217 #define PKO3_LX_SQ_SCHEDULE_RR_QUANTUM_S 0 218 219 #define PKO3_L1_SQ_TOPOLOGY(i) (0x00080000ULL + (i) * 512) 220 #define PKO3_L1_SQ_TOPOLOGY_PRIO_ANCHOR_M 0x000001ff00000000ULL 221 #define PKO3_L1_SQ_TOPOLOGY_PRIO_ANCHOR_S 32 222 #define PKO3_L1_SQ_TOPOLOGY_LINK_M 0x00000000001f0000ULL 223 #define PKO3_L1_SQ_TOPOLOGY_LINK_S 16 224 #define PKO3_L1_SQ_TOPOLOGY_RR_PRIO_M 0x000000000000001eULL 225 #define PKO3_L1_SQ_TOPOLOGY_RR_PRIO_S 1 226 227 #define PKO3_L3_L2_SQ_CHANNEL(i) (0x00080038ULL + (i) * 512) 228 #define PKO3_L3_L2_SQ_CHANNEL_M 0x00000fff00000000ULL 229 #define PKO3_L3_L2_SQ_CHANNEL_S 32 230 #define PKO3_L3_L2_SQ_CHANNEL_CC_ENABLE 0x0000000000000002ULL 231 232 #define PKO3_L2_SQ_TOPOLOGY(i) (0x00100000ULL + (i) * 512) 233 #define PKO3_L2_SQ_TOPOLOGY_PRIO_ANCHOR_M 0x000001ff00000000ULL 234 #define PKO3_L2_SQ_TOPOLOGY_PRIO_ANCHOR_S 32 235 #define PKO3_L2_SQ_TOPOLOGY_PARENT_M 0x00000000001f0000ULL 236 #define PKO3_L2_SQ_TOPOLOGY_PARENT_S 16 237 #define PKO3_L2_SQ_TOPOLOGY_RR_PRIO_M 0x000000000000001eULL 238 #define PKO3_L2_SQ_TOPOLOGY_RR_PRIO_S 1 239 240 #define PKO3_L3_SQ_TOPOLOGY(i) (0x00180000ULL + (i) * 512) 241 #define PKO3_L3_SQ_TOPOLOGY_PRIO_ANCHOR_M 0x000003ff00000000ULL 242 #define PKO3_L3_SQ_TOPOLOGY_PRIO_ANCHOR_S 32 243 #define PKO3_L3_SQ_TOPOLOGY_PARENT_M 0x0000000001ff0000ULL 244 #define PKO3_L3_SQ_TOPOLOGY_PARENT_S 16 245 #define PKO3_L3_SQ_TOPOLOGY_RR_PRIO_M 0x000000000000001eULL 246 #define PKO3_L3_SQ_TOPOLOGY_RR_PRIO_S 1 247 248 #define PKO3_L4_SQ_TOPOLOGY(i) (0x00200000ULL + (i) * 512) 249 #define PKO3_L4_SQ_TOPOLOGY_PRIO_ANCHOR_M 0x000003ff00000000ULL 250 #define PKO3_L4_SQ_TOPOLOGY_PRIO_ANCHOR_S 32 251 #define PKO3_L4_SQ_TOPOLOGY_PARENT_M 0x0000000001ff0000ULL 252 #define PKO3_L4_SQ_TOPOLOGY_PARENT_S 16 253 #define PKO3_L4_SQ_TOPOLOGY_RR_PRIO_M 0x000000000000001eULL 254 #define PKO3_L4_SQ_TOPOLOGY_RR_PRIO_S 1 255 256 #define PKO3_L5_SQ_TOPOLOGY(i) (0x00280000ULL + (i) * 512) 257 #define PKO3_L5_SQ_TOPOLOGY_PRIO_ANCHOR_M 0x000003ff00000000ULL 258 #define PKO3_L5_SQ_TOPOLOGY_PRIO_ANCHOR_S 32 259 #define PKO3_L5_SQ_TOPOLOGY_PARENT_M 0x0000000003ff0000ULL 260 #define PKO3_L5_SQ_TOPOLOGY_PARENT_S 16 261 #define PKO3_L5_SQ_TOPOLOGY_RR_PRIO_M 0x000000000000001eULL 262 #define PKO3_L5_SQ_TOPOLOGY_RR_PRIO_S 1 263 264 #define PKO3_DQ_TOPOLOGY(i) (0x00300000ULL + (i) * 512) 265 #define PKO3_DQ_TOPOLOGY_PARENT_M 0x0000000003ff0000ULL 266 #define PKO3_DQ_TOPOLOGY_PARENT_S 16 267 268 #define PKO3_PDM_CFG 0x00800000ULL 269 #define PKO3_PDM_CFG_DIS_LPD_W2R_FILL 0x0000000000001000ULL 270 #define PKO3_PDM_CFG_EN_FR_W2R_PTR_SWP 0x0000000000000800ULL 271 #define PKO3_PDM_CFG_DIS_FLSH_CACHE 0x0000000000000400ULL 272 #define PKO3_PDM_CFG_MIN_PAD_LEN_M 0x00000000000002f8ULL 273 #define PKO3_PDM_CFG_MIN_PAD_LEN_S 3 274 #define PKO3_PDM_CFG_DIAG_MODE 0x0000000000000004ULL 275 #define PKO3_PDM_CFG_ALLOC_LDS 0x0000000000000002ULL 276 #define PKO3_PDM_CFG_ALLOC_STS 0x0000000000000001ULL 277 278 #define PKO3_PDM_DQ_MINPAD(dq) (0x008f0000ULL + (dq) * 8) 279 #define PKO3_PDM_DQ_MINPAD_MINPAD 0x0000000000000001ULL 280 281 #define PKO3_MAC_CFG(mac) (0x00900000ULL + (mac) * 8) 282 #define PKO3_MAC_CFG_MIN_PAD_ENA 0x0000000000010000ULL 283 #define PKO3_MAC_CFG_FCS_ENA 0x0000000000008000ULL 284 #define PKO3_MAC_CFG_FCS_SOP_OFF_M 0x0000000000007f80ULL 285 #define PKO3_MAC_CFG_FCS_SOP_OFF_S 7 286 #define PKO3_MAC_CFG_SKID_MAX_CNT_M 0x0000000000000060ULL 287 #define PKO3_MAC_CFG_SKID_MAX_CNT_S 5 288 #define PKO3_MAC_CFG_FIFO_NUM_M 0x000000000000001fULL 289 #define PKO3_MAC_CFG_FIFO_NUM_S 0 290 291 #define PKO3_PTGF_CFG(i) (0x00900200ULL + (i) * 8) 292 #define PKO3_PTGF_CFG_RESET 0x0000000000000040ULL 293 #define PKO3_PTGF_CFG_RATE_M 0x0000000000000038ULL 294 #define PKO3_PTGF_CFG_RATE_S 3 295 #define PKO3_PTGF_CFG_SIZE_M 0x0000000000000007ULL 296 #define PKO3_PTGF_CFG_SIZE_S 0 297 298 #define PKO3_PTF_IOBP_CFG 0x00900300ULL 299 #define PKO3_PTF_IOBP_CFG_MAX_RD_SZ_M 0x000000000000007fULL 300 #define PKO3_PTF_IOBP_CFG_MAX_RD_SZ_S 0 301 302 #define PKO3_MCI0_MAX_CRED(mac) (0x00a00000ULL + (mac) * 8) 303 #define PKO3_MCI0_MAC_CRED_LIMIT 0x0000000000000fffULL 304 305 #define PKO3_MCI1_MAX_CRED(mac) (0x00a80000ULL + (mac) * 8) 306 #define PKO3_MCI1_CRED_CNT(mac) (0x00a80100ULL + (mac) * 8) 307 308 #define PKO3_LUT(i) (0x00b00000ULL + (i) * 8) 309 #define PKO3_LUT_VALID 0x0000000000008000ULL 310 #define PKO3_LUT_PQ_IDX_M 0x0000000000003e00ULL 311 #define PKO3_LUT_PQ_IDX_S 9 312 #define PKO3_LUT_QUEUE_NUM_M 0x00000000000001ffULL 313 #define PKO3_LUT_QUEUE_NUM_S 0 314 315 #define PKO3_DPFI_FLUSH 0x00c00008ULL 316 317 #define PKO3_DPFI_FPA_AURA 0x00c00010ULL 318 #define PKO3_DPFI_FPA_AURA_NODE_S 10 319 #define PKO3_DPFI_FPA_AURA_AURA_S 0 320 321 #define PKO3_DPFI_FPA_ENA 0x00c00018ULL 322 #define PKO3_DPFI_FPA_ENA_ENABLE 0x0000000000000001ULL 323 324 #define PKO3_STATUS 0x00d00000ULL 325 #define PKO3_STATUS_PKO_RDY 0x8000000000000000ULL 326 327 #define PKO3_ENABLE 0x00d00008ULL 328 #define PKO3_ENABLE_ENABLE 0x0000000000000001ULL 329 330 /* 331 * PKO commands 332 */ 333 334 #define PKO3_SEND_HDR_AURA 0x0fff000000000000ULL 335 #define PKO3_SEND_HDR_CKL4 0x0000c00000000000ULL 336 #define PKO3_SEND_HDR_CKL3 0x0000200000000000ULL 337 #define PKO3_SEND_HDR_DS 0x0000100000000000ULL 338 #define PKO3_SEND_HDR_LE 0x0000080000000000ULL 339 #define PKO3_SEND_HDR_N2 0x0000040000000000ULL 340 #define PKO3_SEND_HDR_II 0x0000020000000000ULL 341 #define PKO3_SEND_HDR_DF 0x0000010000000000ULL 342 #define PKO3_SEND_HDR_FORMAT 0x0000007f00000000ULL 343 #define PKO3_SEND_HDR_L4PTR 0x00000000ff000000ULL 344 #define PKO3_SEND_HDR_L3PTR 0x0000000000ff0000ULL 345 #define PKO3_SEND_HDR_TOTAL_M 0x000000000000ffffULL 346 #define PKO3_SEND_HDR_TOTAL_S 0 347 348 #define PKO3_LMTDMA_SCRADDR_M 0xff00000000000000ULL 349 #define PKO3_LMTDMA_SCRADDR_S 56 350 #define PKO3_LMTDMA_RTNLEN_M 0x00ff000000000000ULL 351 #define PKO3_LMTDMA_RTNLEN_S 48 352 #define PKO3_LMTDMA_DID 0x0000510000000000ULL 353 #define PKO3_LMTDMA_DID_M 0x0000ff0000000000ULL 354 #define PKO3_LMTDMA_NODE 0x000000f000000000ULL 355 #define PKO3_LMTDMA_DQOP 0x0000000300000000ULL 356 #define PKO3_LMTDMA_DQ_M 0x0000000003ff0000ULL 357 #define PKO3_LMTDMA_DQ_S 16 358 359 #define PKO3_DQOP_SEND 0x0ULL 360 #define PKO3_DQOP_OPEN 0x1ULL 361 #define PKO3_DQOP_CLOSE 0x2ULL 362 363 #define PKO3_SUBDC3_SEND_GATHER 0x1ULL 364 365 #define PKO3_SEND_SUBDC4_CODE_S 44 366 #define PKO3_SEND_SUBDC4_WORK 0xaULL 367 368 #define PKO3_SEND_WORK_CODE 0xaULL 369 370 #define PKO3_SEND_WORK_GRP_S 52 371 #define PKO3_SEND_WORK_TT_S 50 372 #define PKO3_SEND_WORK_ADDR_S 0 373 374 #define PKO3_SEND_ADDR_M 0x000003ffffffffffULL 375 #define PKO3_SEND_ADDR_S 0 376 377 #define PKO3_SUBC_BUF_PTR_SIZE_M 0xffff000000000000ULL 378 #define PKO3_SUBC_BUF_PTR_SIZE_S 48 379 #define PKO3_SUBC_BUF_PTR_SUBDC3_M 0x0000e00000000000ULL 380 #define PKO3_SUBC_BUF_PTR_SUBDC3_S 45 381 #define PKO3_SUBC_BUF_PTR_ADDR_M 0x000003ffffffffffULL 382 #define PKO3_SUBC_BUF_PTR_ADDR_S 0 383 384 /* 385 * PKI registers 386 */ 387 388 #define PKI_BASE 0x0001180044000000ULL 389 #define PKI_SIZE 0x0000000001000000ULL 390 391 #define PKI_ICG_CFG(i) (0x0000a000ULL + (i) * 8) 392 #define PKI_ICG_CFG_PENA 0x0000000001000000ULL 393 394 #define PKI_SFT_RST 0x00000010ULL 395 #define PKI_SFT_RST_BUSY 0x8000000000000000ULL 396 397 #define PKI_BUF_CTL 0x00000100ULL 398 #define PKI_BUF_CTL_PBP_EN 0x0000000000000001ULL 399 #define PKI_BUF_CTL_PKI_EN 0x0000000000000001ULL 400 401 #define PKI_STAT_CTL 0x00000110ULL 402 403 #define PKI_GBL_PEN 0x00000200ULL 404 #define PKI_GBL_PEN_M 0x00000000000003ffULL 405 #define PKI_GBL_PEN_VIRT 0x0000000000000200ULL 406 #define PKI_GBL_PEN_CLG 0x0000000000000100ULL 407 #define PKI_GBL_PEN_CL2 0x0000000000000080ULL 408 #define PKI_GBL_PEN_L4 0x0000000000000040ULL 409 #define PKI_GBL_PEN_IL3 0x0000000000000020ULL 410 #define PKI_GBL_PEN_L3 0x0000000000000010ULL 411 #define PKI_GBL_PEN_MPLS 0x0000000000000008ULL 412 #define PKI_GBL_PEN_FULC 0x0000000000000004ULL 413 #define PKI_GBL_PEN_DSA 0x0000000000000002ULL 414 #define PKI_GBL_PEN_HG 0x0000000000000001ULL 415 416 #define PKI_FRM_LEN_CHK(i) (0x00004000ULL + (i) * 8) 417 #define PKI_FRM_LEN_CHK_MAXLEN_M 0x00000000ffff0000ULL 418 #define PKI_FRM_LEN_CHK_MAXLEN_S 16 419 #define PKI_FRM_LEN_CHK_MINLEN_M 0x000000000000ffffULL 420 #define PKI_FRM_LEN_CHK_MINLEN_S 0 421 422 #define PKI_LTYPE_MAP(i) (0x00005000ULL + (i) * 8) 423 424 #define PKI_IMEM(i) (0x00100000ULL + (i) * 8) 425 426 #define PKI_QPG_TBL(i) (0x00800000ULL + (i) * 8) 427 #define PKI_QPG_TBL_PADD 0x0fff000000000000ULL 428 #define PKI_QPG_TBL_GRPTAG_OK 0x0000c00000000000ULL 429 #define PKI_QPG_TBL_GRP_OK_M 0x000003ff00000000ULL 430 #define PKI_QPG_TBL_GRP_OK_S 32 431 #define PKI_QPG_TBL_GRPTAG_BAD 0x00000000c0000000ULL 432 #define PKI_QPG_TBL_GRP_BAD_M 0x0000000003ff0000ULL 433 #define PKI_QPG_TBL_GRP_BAD_S 16 434 #define PKI_QPG_TBL_AURA_NODE_M 0x0000000000000c00ULL 435 #define PKI_QPG_TBL_AURA_NODE_S 10 436 #define PKI_QPG_TBL_LAURA_M 0x00000000000003ffULL 437 #define PKI_QPG_TBL_LAURA_S 0 438 439 #define PKI_STAT_STAT0(i) (0x00e00038ULL + (i) * 256) 440 #define PKI_STAT_STAT0_PKTS_M 0x0000ffffffffffffULL 441 #define PKI_STAT_STAT1(i) (0x00e00040ULL + (i) * 256) 442 #define PKI_STAT_STAT0_PKTS_M 0x0000ffffffffffffULL 443 #define PKI_STAT_STAT3(i) (0x00e00050ULL + (i) * 256) 444 #define PKI_STAT_STAT3_PKTS 0x0000ffffffffffffULL 445 446 #define PKI_STYLE_BUF(style) (0x0024000ULL + (style) * 8) 447 #define PKI_STYLE_BUF_PKT_LEND 0x0000000100000000ULL 448 #define PKI_STYLE_BUF_WQE_HSZ_M 0x00000000c0000000ULL 449 #define PKI_STYLE_BUF_WQE_HSZ_S 30 450 #define PKI_STYLE_BUF_WQE_SKIP_M 0x0000000030000000ULL 451 #define PKI_STYLE_BUF_WQE_SKIP_S 28 452 #define PKI_STYLE_BUF_FIRST_SKIP_M 0x000000000fc00000ULL 453 #define PKI_STYLE_BUF_FIRST_SKIP_S 22 454 #define PKI_STYLE_BUF_LATER_SKIP_M 0x00000000003f0000ULL 455 #define PKI_STYLE_BUF_LATER_SKIP_S 16 456 #define PKI_STYLE_BUF_OPC_MODE_M 0x000000000000c000ULL 457 #define PKI_STYLE_BUF_OPC_MODE_S 14 458 #define PKI_STYLE_BUF_DIS_WQ_DAT 0x0000000000002000ULL 459 #define PKI_STYLE_BUF_MB_SIZE_M 0x0000000000001fffULL 460 #define PKI_STYLE_BUF_MB_SIZE_S 0 461 462 #define PKI_CL_STYLE_CFG(cl, style) (0x00500000ULL + (cl) * 0x10000 + \ 463 (style) * 8) 464 #define PKI_CL_STYLE_CFG_IP6_UDP_OPT 0x0000000100000000ULL 465 #define PKI_CL_STYLE_CFG_LENERR_EN 0x0000000080000000ULL 466 #define PKI_CL_STYLE_CFG_LENERR_EQPAD 0x0000000040000000ULL 467 #define PKI_CL_STYLE_CFG_MINMAX_SEL 0x0000000020000000ULL 468 #define PKI_CL_STYLE_CFG_MAXERR_EN 0x0000000010000000ULL 469 #define PKI_CL_STYLE_CFG_MINERR_EN 0x0000000008000000ULL 470 #define PKI_CL_STYLE_CFG_QPG_DIS_GRPTAG 0x0000000004000000ULL 471 #define PKI_CL_STYLE_CFG_FCS_STRIP 0x0000000002000000ULL 472 #define PKI_CL_STYLE_CFG_FCS_CHK 0x0000000001000000ULL 473 #define PKI_CL_STYLE_CFG_RAWDRP 0x0000000000800000ULL 474 #define PKI_CL_STYLE_CFG_DROP 0x0000000000400000ULL 475 #define PKI_CL_STYLE_CFG_NODROP 0x0000000000200000ULL 476 #define PKI_CL_STYLE_CFG_QPG_DIS_PADD 0x0000000000100000ULL 477 #define PKI_CL_STYLE_CFG_QPG_DIS_GRP 0x0000000000080000ULL 478 #define PKI_CL_STYLE_CFG_QPG_DIS_AURA 0x0000000000040000ULL 479 #define PKI_CL_STYLE_CFG_QPG_BASE_M 0x00000000000007ffULL 480 #define PKI_CL_STYLE_CFG_QPG_BASE_S 0 481 482 #define PKI_CL_PKIND_STYLE(cl, pkind) (0x00300048ULL + (cl) * 0x10000 + \ 483 (pkind) * 0x100) 484 #define PKI_CL_PKIND_STYLE_PM_M 0x0000000000007f00ULL 485 #define PKI_CL_PKIND_STYLE_PM_S 8 486 #define PKI_CL_PKIND_STYLE_STYLE_M 0x00000000000000ffULL 487 #define PKI_CL_PKIND_STYLE_STYLE_S 0 488 489 #define PKI_CL_STYLE_CFG2(cl, style) (0x00500800ULL + (cl) * 0x10000 + \ 490 (style) * 8) 491 #define PKI_CL_STYLE_ALG(cl, style) (0x00501000ULL + (cl) * 0x10000 + \ 492 (style) * 8) 493 494 #define PKI_CL_PCAM_TERM(cl, bank, i) (0x00700000ULL + (cl) * 0x10000 + \ 495 (bank) * 0x100 + (i) * 8) 496 497 /* 498 * SSO registers 499 */ 500 501 #define SSO_BASE 0x0001670000000000ULL 502 #define SSO_SIZE 0x0000000100000000ULL 503 504 #define SSO_LD_IO 0x0001000000000000ULL 505 #define SSO_LD_DID 0x0000600000000000ULL 506 #define SSO_LD_NODE_M 0x000000f000000000ULL 507 #define SSO_LD_NODE_S 36 508 #define SSO_LD_INDEXED 0x0000000080000000ULL 509 #define SSO_LD_GROUPED 0x0000000040000000ULL 510 #define SSO_LD_RTNGRP 0x0000000020000000ULL 511 #define SSO_LD_INDEX_M 0x000000000000fff0ULL 512 #define SSO_LD_INDEX_S 4 513 #define SSO_LD_WAIT 0x0000000000000008ULL 514 515 /* SSO LD response */ 516 #define SSO_LD_RTN_NO_WORK 0x8000000000000000ULL 517 #define SSO_LD_RTN_ADDR_M 0x000003ffffffffffULL 518 519 #define SSO_WQ_INT 0x00001000ULL 520 521 #define SSO_ERR0 0x00001240ULL 522 #define SSO_ERR1 0x00001248ULL 523 524 #define SSO_AW_CFG 0x000010f0ULL 525 #define SSO_AW_CFG_STT 0x0000000000000008ULL 526 #define SSO_AW_CFG_LDT 0x0000000000000004ULL 527 #define SSO_AW_CFG_LDWB 0x0000000000000002ULL 528 #define SSO_AW_CFG_RWEN 0x0000000000000001ULL 529 530 #define SSO_XAQ_AURA 0x00002100ULL 531 #define SSO_XAQ_AURA_NODE_M 0x0000000000000c00ULL 532 #define SSO_XAQ_AURA_NODE_S 10 533 #define SSO_XAQ_AURA_LAURA_M 0x00000000000003ffULL 534 #define SSO_XAQ_AURA_LAURA_S 0 535 536 #define SSO_XAQ_HEAD_PTR(i) (0x00080000ULL + (i) * 8) 537 #define SSO_XAQ_TAIL_PTR(i) (0x00090000ULL + (i) * 8) 538 #define SSO_XAQ_HEAD_NEXT(i) (0x000a0000ULL + (i) * 8) 539 #define SSO_XAQ_TAIL_NEXT(i) (0x000b0000ULL + (i) * 8) 540 541 #define SSO_GRP_PRI(group) (0x20000200ULL + (group) * 0x10000) 542 #define SSO_GRP_PRI_WEIGHT_M 0x00000000003f0000ULL 543 #define SSO_GRP_PRI_WEIGHT_S 16 544 545 #define SSO_GRP_INT(group) (0x20000400ULL + (group) * 0x10000) 546 #define SSO_GRP_INT_EXE_DIS 0x8000000000000000ULL 547 #define SSO_GRP_INT_EXE_INT 0x0000000000000002ULL 548 549 #define SSO_GRP_INT_THR(group) (0x20000500ULL + (group) * 0x10000) 550 #define SSO_GRP_INT_THR_IAQ_THR_M 0x0000000000001fffULL 551 552 #define SSO_GRP_AQ_CNT(group) (0x20000700ULL + (group) * 0x10000) 553 554 #define SSO_PP_GRPMSK(core, set, i) (0x40001000ULL + (core) * 0x10000 + \ 555 (set) * 0x20 + (i) * 8) 556 557 #define PKI_WORD0_BUFS_M 0x00000000ff000000ULL 558 #define PKI_WORD0_BUFS_S 24 559 #define PKI_WORD0_PKIND_M 0x000000000000003fULL 560 #define PKI_WORD0_PKIND_S 0 561 562 #define PKI_WORD1_LEN_M 0xffff000000000000ULL 563 #define PKI_WORD1_LEN_S 48 564 #define PKI_WORD1_TAG_M 0x00000000ffffffffULL 565 #define PKI_WORD1_TAG_S 0 566 567 #define PKI_WORD2_SW_FLAG 0x8000000000000000ULL 568 #define PKI_WORD2_LG_HDR_TYPE 0x7c00000000000000ULL 569 #define PKI_WORD2_LF_HDR_TYPE 0x03e0000000000000ULL 570 #define PKI_WORD2_LE_HDR_TYPE 0x001f000000000000ULL 571 #define PKI_WORD2_LD_HDR_TYPE 0x0000f80000000000ULL 572 #define PKI_WORD2_LC_HDR_TYPE 0x000007c000000000ULL 573 #define PKI_WORD2_LB_HDR_TYPE 0x0000003e00000000ULL 574 #define PKI_WORD2_IS_LA_ETHER 0x0000000100000000ULL 575 #define PKI_WORD2_VLAN_VALID 0x0000000000800000ULL 576 #define PKI_WORD2_VLAN_STACKED 0x0000000000400000ULL 577 #define PKI_WORD2_STAT_INC 0x0000000000200000ULL 578 #define PKI_WORD2_PCAM_FLAG_M 0x00000000001e0000ULL 579 #define PKI_WORD2_IS_FRAG 0x0000000000010000ULL 580 #define PKI_WORD2_IS_L3_BCAST 0x0000000000008000ULL 581 #define PKI_WORD2_IS_L3_MCAST 0x0000000000004000ULL 582 #define PKI_WORD2_IS_L2_BCAST 0x0000000000002000ULL 583 #define PKI_WORD2_IS_L2_MCAST 0x0000000000001000ULL 584 #define PKI_WORD2_IS_RAW 0x0000000000000800ULL 585 #define PKI_WORD2_ERR_LEVEL_M 0x0000000000000700ULL 586 #define PKI_WORD2_ERR_LEVEL_S 8 587 #define PKI_WORD2_ERR_CODE_M 0x00000000000000ffULL 588 #define PKI_WORD2_ERR_CODE_S 0 589 590 #define PKI_WORD3_SIZE_M 0xffff000000000000ULL 591 #define PKI_WORD3_SIZE_S 48 592 #define PKI_WORD3_ADDR_M 0x000003ffffffffffULL 593 #define PKI_WORD3_ADDR_S 0 594 595 #define PKO3_L1_SQ_SHAPE_STATE(i) (0x00000030ULL + (i) * 512) 596 #define PKO3_L2_SQ_SHAPE_STATE(i) (0x00080030ULL + (i) * 512) 597 #define PKO3_L3_SQ_SHAPE_STATE(i) (0x00100030ULL + (i) * 512) 598 #define PKO3_DQ_SHAPE_STATE(i) (0x00280030ULL + (i) * 512) 599 600 #define PKO3_PTF_STATUS(i) (0x00900100ULL + (i) * 8) 601 602 #endif /* !_OGXREG_H_ */ 603