1 /* $OpenBSD: octeonreg.h,v 1.4 2014/06/17 01:33:04 jmatthew Exp $ */ 2 3 /* 4 * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.com). 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _MACHINE_OCTEONREG_H_ 30 #define _MACHINE_OCTEONREG_H_ 31 32 #define OCTEON_CF_BASE 0x1D000800ULL 33 #define OCTEON_CIU_BASE 0x1070000000000ULL 34 #define OCTEON_CIU_SIZE 0xC10 35 #define OCTEON_MIO_BOOT_BASE 0x1180000000000ULL 36 #define OCTEON_UART0_BASE 0x1180000000800ULL 37 #define OCTEON_UART1_BASE 0x1180000000C00ULL 38 #define OCTEON_RNG_BASE 0x1400000000000ULL 39 40 #define MIO_BOOT_REG_CFG0 0x0 41 #define MIO_BOOT_REG_CFG(x) (MIO_BOOT_REG_CFG0+((x)*8)) 42 #define BOOT_CFG_BASE_MASK 0xFFFF 43 #define BOOT_CFG_BASE_SHIFT 16 44 #define BOOT_CFG_WIDTH_MASK 0x10000000 45 #define BOOT_CFG_WIDTH_SHIFT 28 46 47 #define CIU_INT_WORKQ0 0 48 #define CIU_INT_WORKQ1 1 49 #define CIU_INT_WORKQ2 2 50 #define CIU_INT_WORKQ3 3 51 #define CIU_INT_WORKQ4 4 52 #define CIU_INT_WORKQ5 5 53 #define CIU_INT_WORKQ6 6 54 #define CIU_INT_WORKQ7 7 55 #define CIU_INT_WORKQ8 8 56 #define CIU_INT_WORKQ9 9 57 #define CIU_INT_WORKQ10 10 58 #define CIU_INT_WORKQ11 11 59 #define CIU_INT_WORKQ12 12 60 #define CIU_INT_WORKQ13 13 61 #define CIU_INT_WORKQ14 14 62 #define CIU_INT_WORKQ15 15 63 #define CIU_INT_GPIO0 16 64 #define CIU_INT_GPIO1 17 65 #define CIU_INT_GPIO2 18 66 #define CIU_INT_GPIO3 19 67 #define CIU_INT_GPIO4 20 68 #define CIU_INT_GPIO5 21 69 #define CIU_INT_GPIO6 22 70 #define CIU_INT_GPIO7 23 71 #define CIU_INT_GPIO8 24 72 #define CIU_INT_GPIO9 25 73 #define CIU_INT_GPIO10 26 74 #define CIU_INT_GPIO11 27 75 #define CIU_INT_GPIO12 28 76 #define CIU_INT_GPIO13 29 77 #define CIU_INT_GPIO14 30 78 #define CIU_INT_GPIO15 31 79 #define CIU_INT_MBOX0 32 80 #define CIU_INT_MBOX1 33 81 #define CIU_INT_MBOX(x) (CIU_INT_MBOX0+(x)) 82 #define CIU_INT_UART0 34 83 #define CIU_INT_UART1 35 84 #define CIU_INT_PCI_INTA 36 85 #define CIU_INT_PCI_INTB 37 86 #define CIU_INT_PCI_INTC 38 87 #define CIU_INT_PCI_INTD 39 88 #define CIU_INT_PCI_MSIA 40 89 #define CIU_INT_PCI_MSIB 41 90 #define CIU_INT_PCI_MSIC 42 91 #define CIU_INT_PCI_MSID 43 92 #define CIU_INT_44 44 93 #define CIU_INT_TWSI 45 94 #define CIU_INT_RML 46 95 #define CIU_INT_TRACE 47 96 #define CIU_INT_GMX_DRP0 48 97 #define CIU_INT_GMX_DRP1 49 98 #define CIU_INT_IPD_DRP 50 99 #define CIU_INT_KEY_ZERO 51 100 #define CIU_INT_TIMER0 52 101 #define CIU_INT_TIMER1 53 102 #define CIU_INT_TIMER2 54 103 #define CIU_INT_TIMER3 55 104 #define CIU_INT_USB 56 105 #define CIU_INT_PCM 57 106 #define CIU_INT_MPI 58 107 #define CIU_INT_TWSI2 59 108 #define CIU_INT_POWIQ 60 109 #define CIU_INT_IPDPPTHR 61 110 #define CIU_INT_MII0 62 111 #define CIU_INT_BOOTDMA 63 112 113 #define CIU_INT0_SUM0 0x00000000 114 #define CIU_INT1_SUM0 0x00000008 115 #define CIU_INT2_SUM0 0x00000010 116 #define CIU_INT3_SUM0 0x00000018 117 #define CIU_IP2_SUM0(x) (CIU_INT0_SUM0+(0x10 * (x))) 118 #define CIU_IP3_SUM0(x) (CIU_INT1_SUM0+(0x10 * (x))) 119 #define CIU_INT32_SUM0 0x00000100 120 #define CIU_INT32_SUM1 0x00000108 121 #define CIU_INT0_EN0 0x00000200 122 #define CIU_INT1_EN0 0x00000210 123 #define CIU_INT2_EN0 0x00000220 124 #define CIU_INT3_EN0 0x00000230 125 #define CIU_IP2_EN0(x) (CIU_INT0_EN0+(0x20 * (x))) 126 #define CIU_IP3_EN0(x) (CIU_INT1_EN0+(0x20 * (x))) 127 #define CIU_INT32_EN0 0x00000400 128 #define CIU_INT0_EN1 0x00000208 129 #define CIU_INT1_EN1 0x00000218 130 #define CIU_INT2_EN1 0x00000228 131 #define CIU_INT3_EN1 0x00000238 132 #define CIU_INT32_EN1 0x00000408 133 #define CIU_IP2_EN1(x) (CIU_INT0_EN1+(0x20 * (x))) 134 #define CIU_IP3_EN1(x) (CIU_INT1_EN1+(0x20 * (x))) 135 #define CIU_TIM0 0x00000480 136 #define CIU_TIM1 0x00000488 137 #define CIU_TIM2 0x00000490 138 #define CIU_TIM3 0x00000498 139 #define CIU_WDOG0 0x00000500 140 #define CIU_WDOG1 0x00000508 141 #define CIU_PP_POKE0 0x00000580 142 #define CIU_PP_POKE1 0x00000588 143 #define CIU_MBOX_SET0 0x00000600 144 #define CIU_MBOX_SET1 0x00000608 145 #define CIU_MBOX_SET(x) (CIU_MBOX_SET0+(0x08 * (x))) 146 #define CIU_MBOX_CLR0 0x00000680 147 #define CIU_MBOX_CLR1 0x00000688 148 #define CIU_MBOX_CLR(x) (CIU_MBOX_CLR0+(0x08 * (x))) 149 #define CIU_PP_RST 0x00000700 150 #define CIU_PP_DBG 0x00000708 151 #define CIU_GSTOP 0x00000710 152 #define CIU_NMI 0x00000718 153 #define CIU_DINT 0x00000720 154 #define CIU_FUSE 0x00000728 155 #define CIU_BIST 0x00000730 156 #define CIU_SOFT_BIST 0x00000738 157 #define CIU_SOFT_RST 0x00000740 158 #define CIU_SOFT_PRST 0x00000748 159 #define CIU_PCI_INTA 0x00000750 160 #define CIU_INT0_SUM4 0x00000C00 161 #define CIU_INT1_SUM4 0x00000C08 162 #define CIU_INT0_EN4_0 0x00000C80 163 #define CIU_INT1_EN4_0 0x00000C90 164 #define CIU_INT0_EN4_1 0x00000C88 165 #define CIU_INT1_EN4_1 0x00000C98 166 167 #define MIO_RST_BOOT 0x1180000001600ULL 168 #define MIO_RST_BOOT_PNR_MUL_SHIFT 24 169 #define MIO_RST_BOOT_PNR_MUL_MASK 0x3f 170 #define OCTEON_IO_REF_CLOCK 50000000 /* 50MHz */ 171 172 #endif /* !_MACHINE_OCTEONREG_H_ */ 173