1 /* $OpenBSD: cpu.h,v 1.69 2021/06/02 00:39:26 cheloha Exp $ */ 2 /* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */ 3 4 /* 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 #ifndef _POWERPC_CPU_H_ 35 #define _POWERPC_CPU_H_ 36 37 #include <machine/frame.h> 38 39 #include <sys/device.h> 40 #include <sys/sched.h> 41 #include <sys/srp.h> 42 43 struct cpu_info { 44 struct device *ci_dev; /* our device */ 45 struct schedstate_percpu ci_schedstate; /* scheduler state */ 46 47 struct proc *ci_curproc; 48 49 struct pcb *ci_curpcb; 50 struct pmap *ci_curpm; 51 struct proc *ci_fpuproc; 52 struct proc *ci_vecproc; 53 int ci_cpuid; 54 55 volatile int ci_want_resched; 56 volatile int ci_cpl; 57 volatile int ci_ipending; 58 59 volatile int ci_flags; 60 #define CI_FLAGS_SLEEPING 2 61 62 #if defined(MULTIPROCESSOR) 63 struct srp_hazard ci_srp_hazards[SRP_HAZARD_NUM]; 64 #endif 65 66 int ci_intrdepth; 67 char *ci_intstk; 68 #define CPUSAVE_LEN 8 69 register_t ci_tempsave[CPUSAVE_LEN]; 70 register_t ci_ddbsave[CPUSAVE_LEN]; 71 #define DISISAVE_LEN 4 72 register_t ci_disisave[DISISAVE_LEN]; 73 74 volatile u_int64_t ci_nexttimerevent; 75 volatile u_int64_t ci_prevtb; 76 volatile u_int64_t ci_lasttb; 77 volatile u_int64_t ci_nextstatevent; 78 int ci_statspending; 79 80 volatile int ci_ddb_paused; 81 #define CI_DDB_RUNNING 0 82 #define CI_DDB_SHOULDSTOP 1 83 #define CI_DDB_STOPPED 2 84 #define CI_DDB_ENTERDDB 3 85 #define CI_DDB_INDDB 4 86 87 u_int32_t ci_randseed; 88 89 #ifdef DIAGNOSTIC 90 int ci_mutex_level; 91 #endif 92 #ifdef GPROF 93 struct gmonparam *ci_gmon; 94 #endif 95 char ci_panicbuf[512]; 96 }; 97 98 static __inline struct cpu_info * 99 curcpu(void) 100 { 101 struct cpu_info *ci; 102 103 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 104 return ci; 105 } 106 107 #define curpcb (curcpu()->ci_curpcb) 108 #define curpm (curcpu()->ci_curpm) 109 110 #define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0) 111 112 #ifdef MULTIPROCESSOR 113 114 #define PPC_MAXPROCS 4 115 116 static __inline int 117 cpu_number(void) 118 { 119 int pir; 120 121 pir = curcpu()->ci_cpuid; 122 return pir; 123 } 124 125 void cpu_boot_secondary_processors(void); 126 127 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 128 #define CPU_INFO_ITERATOR int 129 #define CPU_INFO_FOREACH(cii, ci) \ 130 for (cii = 0, ci = &cpu_info[0]; cii < ncpusfound; cii++, ci++) 131 132 void cpu_unidle(struct cpu_info *); 133 134 #else 135 136 #define PPC_MAXPROCS 1 137 138 #define cpu_number() 0 139 140 #define CPU_IS_PRIMARY(ci) 1 141 #define CPU_INFO_ITERATOR int 142 #define CPU_INFO_FOREACH(cii, ci) \ 143 for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL) 144 145 #define cpu_unidle(ci) 146 147 #endif 148 149 #define CPU_BUSY_CYCLE() do {} while (0) 150 151 #define MAXCPUS PPC_MAXPROCS 152 153 extern struct cpu_info cpu_info[PPC_MAXPROCS]; 154 155 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 156 #define CLKF_PC(frame) ((frame)->srr0) 157 #define CLKF_INTR(frame) ((frame)->depth != 0) 158 159 extern int ppc_cpuidle; 160 extern int ppc_proc_is_64b; 161 extern int ppc_nobat; 162 163 void cpu_bootstrap(void); 164 165 static inline unsigned int 166 cpu_rnd_messybits(void) 167 { 168 unsigned int hi, lo; 169 170 __asm volatile("mftbu %0; mftb %1" : "=r" (hi), "=r" (lo)); 171 172 return (hi ^ lo); 173 } 174 175 /* 176 * This is used during profiling to integrate system time. 177 */ 178 #define PROC_PC(p) (trapframe(p)->srr0) 179 #define PROC_STACK(p) (trapframe(p)->fixreg[1]) 180 181 void delay(unsigned); 182 #define DELAY(n) delay(n) 183 184 #define aston(p) ((p)->p_md.md_astpending = 1) 185 186 /* 187 * Preempt the current process if in interrupt from user mode, 188 * or after the current trap/syscall if in system mode. 189 */ 190 #define need_resched(ci) \ 191 do { \ 192 ci->ci_want_resched = 1; \ 193 if (ci->ci_curproc != NULL) \ 194 aston(ci->ci_curproc); \ 195 } while (0) 196 #define clear_resched(ci) (ci)->ci_want_resched = 0 197 198 #define need_proftick(p) aston(p) 199 200 void signotify(struct proc *); 201 202 extern char *bootpath; 203 204 #ifndef CACHELINESIZE 205 #define CACHELINESIZE 32 /* For now XXX */ 206 #endif 207 208 static __inline void 209 syncicache(void *from, int len) 210 { 211 int l; 212 char *p = from; 213 214 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 215 l = len; 216 217 do { 218 __asm volatile ("dcbst 0,%0" :: "r"(p)); 219 p += CACHELINESIZE; 220 } while ((l -= CACHELINESIZE) > 0); 221 __asm volatile ("sync"); 222 p = from; 223 l = len; 224 do { 225 __asm volatile ("icbi 0,%0" :: "r"(p)); 226 p += CACHELINESIZE; 227 } while ((l -= CACHELINESIZE) > 0); 228 __asm volatile ("isync"); 229 } 230 231 static __inline void 232 invdcache(void *from, int len) 233 { 234 int l; 235 char *p = from; 236 237 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 238 l = len; 239 240 do { 241 __asm volatile ("dcbi 0,%0" :: "r"(p)); 242 p += CACHELINESIZE; 243 } while ((l -= CACHELINESIZE) > 0); 244 __asm volatile ("sync"); 245 } 246 247 static __inline void 248 flushdcache(void *from, int len) 249 { 250 int l; 251 char *p = from; 252 253 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 254 l = len; 255 256 do { 257 __asm volatile ("dcbf 0,%0" :: "r"(p)); 258 p += CACHELINESIZE; 259 } while ((l -= CACHELINESIZE) > 0); 260 __asm volatile ("sync"); 261 } 262 263 #define FUNC_SPR(n, name) \ 264 static __inline u_int32_t ppc_mf ## name (void) \ 265 { \ 266 u_int32_t ret; \ 267 __asm volatile ("mfspr %0," # n : "=r" (ret)); \ 268 return ret; \ 269 } \ 270 static __inline void ppc_mt ## name (u_int32_t val) \ 271 { \ 272 __asm volatile ("mtspr "# n ",%0" :: "r" (val)); \ 273 } \ 274 275 FUNC_SPR(0, mq) 276 FUNC_SPR(1, xer) 277 FUNC_SPR(4, rtcu) 278 FUNC_SPR(5, rtcl) 279 FUNC_SPR(8, lr) 280 FUNC_SPR(9, ctr) 281 FUNC_SPR(18, dsisr) 282 FUNC_SPR(19, dar) 283 FUNC_SPR(22, dec) 284 FUNC_SPR(25, sdr1) 285 FUNC_SPR(26, srr0) 286 FUNC_SPR(27, srr1) 287 FUNC_SPR(256, vrsave) 288 FUNC_SPR(272, sprg0) 289 FUNC_SPR(273, sprg1) 290 FUNC_SPR(274, sprg2) 291 FUNC_SPR(275, sprg3) 292 FUNC_SPR(280, asr) 293 FUNC_SPR(282, ear) 294 FUNC_SPR(287, pvr) 295 FUNC_SPR(311, hior) 296 FUNC_SPR(528, ibat0u) 297 FUNC_SPR(529, ibat0l) 298 FUNC_SPR(530, ibat1u) 299 FUNC_SPR(531, ibat1l) 300 FUNC_SPR(532, ibat2u) 301 FUNC_SPR(533, ibat2l) 302 FUNC_SPR(534, ibat3u) 303 FUNC_SPR(535, ibat3l) 304 FUNC_SPR(560, ibat4u) 305 FUNC_SPR(561, ibat4l) 306 FUNC_SPR(562, ibat5u) 307 FUNC_SPR(563, ibat5l) 308 FUNC_SPR(564, ibat6u) 309 FUNC_SPR(565, ibat6l) 310 FUNC_SPR(566, ibat7u) 311 FUNC_SPR(567, ibat7l) 312 FUNC_SPR(536, dbat0u) 313 FUNC_SPR(537, dbat0l) 314 FUNC_SPR(538, dbat1u) 315 FUNC_SPR(539, dbat1l) 316 FUNC_SPR(540, dbat2u) 317 FUNC_SPR(541, dbat2l) 318 FUNC_SPR(542, dbat3u) 319 FUNC_SPR(543, dbat3l) 320 FUNC_SPR(568, dbat4u) 321 FUNC_SPR(569, dbat4l) 322 FUNC_SPR(570, dbat5u) 323 FUNC_SPR(571, dbat5l) 324 FUNC_SPR(572, dbat6u) 325 FUNC_SPR(573, dbat6l) 326 FUNC_SPR(574, dbat7u) 327 FUNC_SPR(575, dbat7l) 328 FUNC_SPR(1009, hid1) 329 FUNC_SPR(1010, iabr) 330 FUNC_SPR(1017, l2cr) 331 FUNC_SPR(1018, l3cr) 332 FUNC_SPR(1013, dabr) 333 FUNC_SPR(1023, pir) 334 335 static __inline u_int32_t 336 ppc_mftbl (void) 337 { 338 int ret; 339 __asm volatile ("mftb %0" : "=r" (ret)); 340 return ret; 341 } 342 343 344 static __inline u_int64_t 345 ppc_mftb(void) 346 { 347 u_long scratch; 348 u_int64_t tb; 349 350 __asm volatile ("1: mftbu %0; mftb %L0; mftbu %1;" 351 " cmpw 0,%0,%1; bne 1b" : "=r"(tb), "=r"(scratch)); 352 return tb; 353 } 354 355 static __inline void 356 ppc_mttb(u_int64_t tb) 357 { 358 __asm volatile ("mttbl %0" :: "r"(0)); 359 __asm volatile ("mttbu %0" :: "r"((u_int32_t)(tb >> 32))); 360 __asm volatile ("mttbl %0" :: "r"((u_int32_t)(tb & 0xffffffff))); 361 } 362 363 static __inline u_int32_t 364 ppc_mfmsr (void) 365 { 366 int ret; 367 __asm volatile ("mfmsr %0" : "=r" (ret)); 368 return ret; 369 } 370 371 static __inline void 372 ppc_mtmsr (u_int32_t val) 373 { 374 __asm volatile ("mtmsr %0" :: "r" (val)); 375 } 376 377 static __inline void 378 ppc_mtsrin(u_int32_t val, u_int32_t sn_shifted) 379 { 380 __asm volatile ("mtsrin %0,%1" :: "r"(val), "r"(sn_shifted)); 381 } 382 383 u_int64_t ppc64_mfscomc(void); 384 void ppc_mtscomc(u_int32_t); 385 void ppc64_mtscomc(u_int64_t); 386 u_int64_t ppc64_mfscomd(void); 387 void ppc_mtscomd(u_int32_t); 388 u_int32_t ppc_mfhid0(void); 389 void ppc_mthid0(u_int32_t); 390 u_int64_t ppc64_mfhid1(void); 391 void ppc64_mthid1(u_int64_t); 392 u_int64_t ppc64_mfhid4(void); 393 void ppc64_mthid4(u_int64_t); 394 u_int64_t ppc64_mfhid5(void); 395 void ppc64_mthid5(u_int64_t); 396 397 #include <machine/psl.h> 398 399 /* 400 * General functions to enable and disable interrupts 401 * without having inlined assembly code in many functions. 402 */ 403 static __inline void 404 ppc_intr_enable(int enable) 405 { 406 u_int32_t msr; 407 if (enable != 0) { 408 msr = ppc_mfmsr(); 409 msr |= PSL_EE; 410 ppc_mtmsr(msr); 411 } 412 } 413 414 static __inline int 415 ppc_intr_disable(void) 416 { 417 u_int32_t emsr, dmsr; 418 emsr = ppc_mfmsr(); 419 dmsr = emsr & ~PSL_EE; 420 ppc_mtmsr(dmsr); 421 return (emsr & PSL_EE); 422 } 423 424 static __inline u_long 425 intr_disable(void) 426 { 427 return ppc_intr_disable(); 428 } 429 430 static __inline void 431 intr_restore(u_long s) 432 { 433 ppc_intr_enable(s); 434 } 435 436 int ppc_cpuspeed(int *); 437 438 /* 439 * PowerPC CPU types 440 */ 441 #define PPC_CPU_MPC601 1 442 #define PPC_CPU_MPC603 3 443 #define PPC_CPU_MPC604 4 444 #define PPC_CPU_MPC603e 6 445 #define PPC_CPU_MPC603ev 7 446 #define PPC_CPU_MPC750 8 447 #define PPC_CPU_MPC604ev 9 448 #define PPC_CPU_MPC7400 12 449 #define PPC_CPU_IBM970 0x0039 450 #define PPC_CPU_IBM970FX 0x003c 451 #define PPC_CPU_IBM970MP 0x0044 452 #define PPC_CPU_IBM750FX 0x7000 453 #define PPC_CPU_MPC7410 0x800c 454 #define PPC_CPU_MPC7447A 0x8003 455 #define PPC_CPU_MPC7448 0x8004 456 #define PPC_CPU_MPC7450 0x8000 457 #define PPC_CPU_MPC7455 0x8001 458 #define PPC_CPU_MPC7457 0x8002 459 #define PPC_CPU_MPC83xx 0x8083 460 461 /* 462 * This needs to be included late since it relies on definitions higher 463 * up in this file. 464 */ 465 #if defined(MULTIPROCESSOR) && defined(_KERNEL) 466 #include <sys/mplock.h> 467 #endif 468 469 #endif /* _POWERPC_CPU_H_ */ 470