1 /* $OpenBSD: pte.h,v 1.2 2021/05/12 01:20:52 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2019 Brian Bamsch <bbamsch@google.com> 5 * Copyright (c) 2014 Dale Rahn <drahn@dalerahn.com> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #ifndef _RISCV64_PTE_H_ 20 #define _RISCV64_PTE_H_ 21 22 #include "machine/vmparam.h" 23 24 #define Lx_TABLE_ALIGN (4096) 25 26 /* Block and Page attributes */ 27 /* Bits 9:8 are reserved for software */ 28 #define PTE_ATTR_MASK (0x3ffUL) 29 #define PTE_SW_MANAGED (1 << 9) 30 #define PTE_SW_WIRED (1 << 8) 31 #define PTE_D (1 << 7) /* Dirty */ 32 #define PTE_A (1 << 6) /* Accessed */ 33 #define PTE_G (1 << 5) /* Global */ 34 #define PTE_U (1 << 4) /* User */ 35 #define PTE_X (1 << 3) /* Execute */ 36 #define PTE_W (1 << 2) /* Write */ 37 #define PTE_R (1 << 1) /* Read */ 38 #define PTE_V (1 << 0) /* Valid */ 39 #define PTE_RWX (PTE_R | PTE_W | PTE_X) 40 #define PTE_RX (PTE_R | PTE_X) 41 #define PTE_KERN (PTE_V | PTE_R | PTE_W | PTE_A | PTE_D) 42 #define PTE_PROMOTE (PTE_V | PTE_RWX | PTE_D | PTE_A | PTE_G | PTE_U | \ 43 PTE_SW_MANAGED | PTE_SW_WIRED 44 45 /* Level 0 table, 512GiB per entry */ 46 #define L0_SHIFT 39 47 48 /* Level 1 table, 1GiB per entry */ 49 #define L1_SHIFT 30 50 #define L1_SIZE (1UL << L1_SHIFT) 51 #define L1_OFFSET (L1_SIZE - 1) 52 53 /* Level 2 table, 2MiB per entry */ 54 #define L2_SHIFT 21 55 #define L2_SIZE (1UL << L2_SHIFT) 56 #define L2_OFFSET (L2_SIZE - 1) 57 58 /* Level 3 table, 4KiB per entry */ 59 #define L3_SHIFT 12 60 #define L3_SIZE (1UL << L3_SHIFT) 61 #define L3_OFFSET (L3_SIZE - 1) 62 63 /* page mapping */ 64 #define Ln_ENTRIES_SHIFT 9 65 #define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT) 66 #define Ln_ADDR_MASK (Ln_ENTRIES - 1) 67 #define Ln_TABLE_MASK ((1 << 12) - 1) 68 69 /* physical page number mask */ 70 #define PTE_RPGN (((1ULL << 56) - 1) & ~PAGE_MASK) 71 72 #define PTE_PPN0_S 10 73 #define PTE_PPN1_S 19 74 #define PTE_PPN2_S 28 75 #define PTE_PPN3_S 37 76 #define PTE_SIZE 8 77 78 #ifndef _LOCORE 79 typedef uint64_t pt_entry_t; /* page table entry */ 80 typedef uint64_t pn_t; /* page number */ 81 #endif /* !_LOCORE */ 82 83 #endif /* _RISCV64_PTE_H_ */ 84