1 /*- 2 * Copyright (c) 2019 Brian Bamsch <bbamsch@google.com> 3 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> 4 * All rights reserved. 5 * 6 * Portions of this software were developed by SRI International and the 7 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 9 * 10 * Portions of this software were developed by the University of Cambridge 11 * Computer Laboratory as part of the CTSRD Project, with support from the 12 * UK Higher Education Innovation Fund (HEIF). 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. Neither the name of the copyright holder nor the names of its 23 * contributors may be used to endorse or promote products derived from 24 * this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #ifndef _MACHINE_RISCVREG_H_ 40 #define _MACHINE_RISCVREG_H_ 41 42 #define EXCP_SHIFT 0 43 #define EXCP_MASK (0xf << EXCP_SHIFT) 44 #define EXCP_MISALIGNED_FETCH 0 45 #define EXCP_FAULT_FETCH 1 46 #define EXCP_ILLEGAL_INSTRUCTION 2 47 #define EXCP_BREAKPOINT 3 48 #define EXCP_MISALIGNED_LOAD 4 49 #define EXCP_FAULT_LOAD 5 50 #define EXCP_MISALIGNED_STORE 6 51 #define EXCP_FAULT_STORE 7 52 #define EXCP_USER_ECALL 8 53 #define EXCP_SUPERVISOR_ECALL 9 54 #define EXCP_HYPERVISOR_ECALL 10 55 #define EXCP_MACHINE_ECALL 11 56 #define EXCP_INST_PAGE_FAULT 12 57 #define EXCP_LOAD_PAGE_FAULT 13 58 #define EXCP_STORE_PAGE_FAULT 15 59 #define EXCP_INTR (1ul << 63) 60 61 #define MSTATUS_UIE (1 << 0) 62 #define MSTATUS_SIE (1 << 1) 63 #define MSTATUS_MIE (1 << 3) 64 #define MSTATUS_UPIE (1 << 4) 65 #define MSTATUS_SPIE (1 << 5) 66 #define MSTATUS_MPIE (1 << 7) 67 #define MSTATUS_SPP (1 << 8) 68 #define MSTATUS_MPP_SHIFT 11 69 #define MSTATUS_MPP_MASK (0x3 << MSTATUS_MPP_SHIFT) 70 #define MSTATUS_FS_SHIFT 13 71 #define MSTATUS_FS_MASK (0x3 << MSTATUS_FS_SHIFT) 72 #define MSTATUS_XS_SHIFT 15 73 #define MSTATUS_XS_MASK (0x3 << MSTATUS_XS_SHIFT) 74 #define MSTATUS_MPRV (1 << 17) 75 #define MSTATUS_SUM (1 << 18) 76 #define MSTATUS_MXR (1 << 19) 77 #define MSTATUS_TVM (1 << 20) 78 #define MSTATUS_TW (1 << 21) 79 #define MSTATUS_TSR (1 << 22) 80 #define MSTATUS_UXL_SHIFT 32 81 #define MSTATUS_UXL_MASK (0x3 << MSTATUS_UXL_SHIFT) 82 #define MSTATUS_SXL_SHIFT 34 83 #define MSTATUS_SXL_MASK (0x3 << MSTATUS_SXL_SHIFT) 84 #define MSTATUS_SD (1 << (MXLEN - 1)) 85 86 #define SSTATUS_UIE (1 << 0) 87 #define SSTATUS_SIE (1 << 1) 88 #define SSTATUS_UPIE (1 << 4) 89 #define SSTATUS_SPIE (1 << 5) 90 #define SSTATUS_SPP (1 << 8) 91 #define SSTATUS_FS_SHIFT 13 92 #define SSTATUS_FS_MASK (0x3 << SSTATUS_FS_SHIFT) 93 #define SSTATUS_FS_OFF (0x0 << SSTATUS_FS_SHIFT) 94 #define SSTATUS_FS_INITIAL (0x1 << SSTATUS_FS_SHIFT) 95 #define SSTATUS_FS_CLEAN (0x2 << SSTATUS_FS_SHIFT) 96 #define SSTATUS_FS_DIRTY (0x3 << SSTATUS_FS_SHIFT) 97 #define SSTATUS_XS_SHIFT 15 98 #define SSTATUS_XS_MASK (0x3 << SSTATUS_XS_SHIFT) 99 #define SSTATUS_SUM (1 << 18) 100 #define SSTATUS_MXR (1 << 19) 101 #define SSTATUS_UXL_SHIFT 32 102 #define SSTATUS_UXL_MASK (0x3 << SSTATUS_UXL_SHIFT) 103 #define SSTATUS_SD (1 << (SXLEN - 1)) 104 105 #define USTATUS_UIE (1 << 0) 106 #define USTATUS_UPIE (1 << 4) 107 108 #define MSTATUS_PRV_U 0 /* user */ 109 #define MSTATUS_PRV_S 1 /* supervisor */ 110 #define MSTATUS_PRV_H 2 /* hypervisor */ 111 #define MSTATUS_PRV_M 3 /* machine */ 112 113 #define MIE_USIE (1 << 0) 114 #define MIE_SSIE (1 << 1) 115 #define MIE_MSIE (1 << 3) 116 #define MIE_UTIE (1 << 4) 117 #define MIE_STIE (1 << 5) 118 #define MIE_MTIE (1 << 7) 119 #define MIE_UEIE (1 << 8) 120 #define MIE_SEIE (1 << 9) 121 #define MIE_MEIE (1 << 11) 122 123 #define MIP_USIP (1 << 0) 124 #define MIP_SSIP (1 << 1) 125 #define MIP_MSIP (1 << 3) 126 #define MIP_UTIP (1 << 4) 127 #define MIP_STIP (1 << 5) 128 #define MIP_MTIP (1 << 7) 129 #define MIP_UEIP (1 << 8) 130 #define MIP_SEIP (1 << 9) 131 #define MIP_MEIP (1 << 11) 132 133 #define SIE_USIE (1 << 0) 134 #define SIE_SSIE (1 << 1) 135 #define SIE_UTIE (1 << 4) 136 #define SIE_STIE (1 << 5) 137 #define SIE_UEIE (1 << 8) 138 #define SIE_SEIE (1 << 9) 139 140 #define SIP_USIP (1 << 0) 141 #define SIP_SSIP (1 << 1) 142 #define SIP_UTIP (1 << 4) 143 #define SIP_STIP (1 << 5) 144 #define SIP_UEIP (1 << 8) 145 #define SIP_SEIP (1 << 9) 146 147 #define UIE_USIE (1 << 0) 148 #define UIE_UTIE (1 << 4) 149 #define UIE_UEIE (1 << 8) 150 151 #define UIP_USIP (1 << 0) 152 #define UIP_UTIP (1 << 4) 153 #define UIP_UEIP (1 << 8) 154 155 #define PPN(pa) ((pa) >> PAGE_SHIFT) 156 #define SATP_PPN_SHIFT 0 157 #define SATP_PPN_MASK (0xfffffffffffULL << SATP_PPN_SHIFT) 158 #define SATP_PPN(satp) (((satp) & SATP_PPN_MASK) >> SATP_PPN_SHIFT) 159 #define SATP_FORMAT_PPN(ppn) (((uint64_t)(ppn) << SATP_PPN_SHIFT) & SATP_PPN_MASK) 160 #define SATP_ASID_SHIFT 44 161 #define SATP_ASID_MASK (0xffffULL << SATP_ASID_SHIFT) 162 #define SATP_ASID(satp) (((satp) & SATP_ASID_MASK) >> SATP_ASID_SHIFT) 163 #define SATP_FORMAT_ASID(asid) (((uint64_t)(asid) << SATP_ASID_SHIFT) & SATP_ASID_MASK) 164 #define SATP_MODE_SHIFT 60 165 #define SATP_MODE_MASK (0xfULL << SATP_MODE_SHIFT) 166 #define SATP_MODE(mode) (((satp) & SATP_MODE_MASK) >> SATP_MODE_SHIFT) 167 168 #define SATP_MODE_SV39 (8ULL << SATP_MODE_SHIFT) 169 #define SATP_MODE_SV48 (9ULL << SATP_MODE_SHIFT) 170 #define SATP_MODE_SV57 (10ULL << SATP_MODE_SHIFT) 171 #define SATP_MODE_SV64 (11ULL << SATP_MODE_SHIFT) 172 173 /** 174 * As of RISC-V Machine ISA v1.11, the XLEN can vary between 175 * Machine, Supervisor, and User modes. The Machine XLEN (MXLEN) 176 * is resolved from the MXL field of the 'misa' CSR. The 177 * Supervisor XLEN (SXLEN) and User XLEN (UXLEN) are resolved 178 * from the SXL and UXL fields of the 'mstatus' CSR, respectively. 179 * 180 * The Machine XLEN is reset to the widest supported ISA variant 181 * at machine reset. For now, assume that all modes will always 182 * use the same, static XLEN of 64 bits. 183 */ 184 #define XLEN 64 185 #define XLEN_BYTES (XLEN / 8) 186 #define MXLEN XLEN 187 #define SXLEN XLEN 188 #define UXLEN XLEN 189 #define INSN_SIZE 4 190 #define INSN_C_SIZE 2 191 192 // Check if val can fit in the CSR immediate form 193 #define CSR_ZIMM(val) \ 194 (__builtin_constant_p(val) && ((u_long)(val) < 32)) 195 196 #define csr_swap(csr, val) \ 197 ({ if (CSR_ZIMM(val)) \ 198 __asm __volatile("csrrwi %0, " #csr ", %1" \ 199 : "=r" (val) : "i" (val)); \ 200 else \ 201 __asm __volatile("csrrw %0, " #csr ", %1" \ 202 : "=r" (val) : "r" (val)); \ 203 val; \ 204 }) 205 206 #define csr_write(csr, val) \ 207 ({ if (CSR_ZIMM(val)) \ 208 __asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \ 209 else \ 210 __asm __volatile("csrw " #csr ", %0" :: "r" (val)); \ 211 }) 212 213 #define csr_set(csr, val) \ 214 ({ if (CSR_ZIMM(val)) \ 215 __asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \ 216 else \ 217 __asm __volatile("csrs " #csr ", %0" :: "r" (val)); \ 218 }) 219 220 #define csr_clear(csr, val) \ 221 ({ if (CSR_ZIMM(val)) \ 222 __asm __volatile("csrci " #csr ", %0" :: "i" (val)); \ 223 else \ 224 __asm __volatile("csrc " #csr ", %0" :: "r" (val)); \ 225 }) 226 227 #define csr_read(csr) \ 228 ({ u_long val; \ 229 __asm __volatile("csrr %0, " #csr : "=r" (val)); \ 230 val; \ 231 }) 232 233 #endif /* !_MACHINE_RISCVREG_H_ */ 234