1 /* $OpenBSD: cache.h,v 1.3 2008/06/26 05:42:12 ray Exp $ */ 2 /* $NetBSD: cache.h,v 1.7 2006/01/21 00:46:36 uwe Exp $ */ 3 4 /*- 5 * Copyright (c) 2002 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by UCHIYAMA Yasushi. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cache configurations. 35 * 36 * SH3 I/D unified virtual-index physical-tag cache. 37 * SH4 I/D separated virtual-index physical-tag cache. 38 * 39 * 40 * size line-size entry way type 41 * SH7708 4/8K 16B 128 2/4 P0,P2,U0 [1] 42 * P1 [2] 43 * SH7709 4/8K 16B 128 2/4 [1] 44 * SH7709A 16K 16B 256 4 [1] 45 * 46 * SH7750 I$ D$ line-size entry way 47 * 8K 8/16K 32B 256 1 [1] 48 * SH7750 49 * SH7750S 50 * SH7751 I$ D$ line-size entry way 51 * 8K 8/16K 32B 256 1 [1] 52 * 53 * SH7750R 54 * SH7751R I$ D$ line-size entry way 55 * 16K 16/32K 32B 512 2 [1] 56 * 57 * [1] write-through/back selectable 58 * [2] write-through only 59 * 60 * Cache operations. 61 * 62 * There are some rules that must be followed: 63 * 64 * I-cache Sync (all or range): 65 * The goal is to synchronize the instruction stream, 66 * so you may need to write-back dirty data cache 67 * blocks first. If a range is requested, and you 68 * can't synchronize just a range, you have to hit 69 * the whole thing. 70 * 71 * D-cache Write-back Invalidate range: 72 * If you can't WB-Inv a range, you must WB-Inv the 73 * entire D-cache. 74 * 75 * D-cache Invalidate: 76 * If you can't Inv the D-cache without doing a 77 * Write-back, YOU MUST PANIC. This is to catch 78 * errors in calling code. Callers must be aware 79 * of this scenario, and must handle it appropriately 80 * (consider the bus_dma(9) operations). 81 * 82 * D-cache Write-back: 83 * If you can't Write-back without doing an invalidate, 84 * that's fine. Then treat this as a WB-Inv. Skipping 85 * the invalidate is merely an optimization. 86 * 87 * All operations: 88 * Valid virtual addresses must be passed to the 89 * cache operation. 90 * 91 * 92 * sh_icache_sync_all Synchronize I-cache 93 * 94 * sh_icache_sync_range Synchronize I-cache range 95 * 96 * sh_icache_sync_range_index (index ops) 97 * 98 * sh_dcache_wbinv_all Write-back Invalidate D-cache 99 * 100 * sh_dcache_wbinv_range Write-back Invalidate D-cache range 101 * 102 * sh_dcache_wbinv_range_index (index ops) 103 * 104 * sh_dcache_inv_range Invalidate D-cache range 105 * 106 * sh_dcache_wb_range Write-back D-cache range 107 * 108 * If I/D unified cache (SH3), I-cache ops are writeback invalidate 109 * operation. 110 * If write-through mode, sh_dcache_wb_range is no-operation. 111 * 112 */ 113 114 #ifndef _SH_CACHE_H_ 115 #define _SH_CACHE_H_ 116 117 #ifdef _KERNEL 118 struct sh_cache_ops { 119 void (*_icache_sync_all)(void); 120 void (*_icache_sync_range)(vaddr_t, vsize_t); 121 void (*_icache_sync_range_index)(vaddr_t, vsize_t); 122 123 void (*_dcache_wbinv_all)(void); 124 void (*_dcache_wbinv_range)(vaddr_t, vsize_t); 125 void (*_dcache_wbinv_range_index)(vaddr_t, vsize_t); 126 void (*_dcache_inv_range)(vaddr_t, vsize_t); 127 void (*_dcache_wb_range)(vaddr_t, vsize_t); 128 }; 129 130 /* Cache configurations */ 131 #define sh_cache_enable_unified sh_cache_enable_icache 132 extern int sh_cache_enable_icache; 133 extern int sh_cache_enable_dcache; 134 extern int sh_cache_write_through; 135 extern int sh_cache_write_through_p0_u0_p3; 136 extern int sh_cache_write_through_p1; 137 extern int sh_cache_ways; 138 extern int sh_cache_unified; 139 #define sh_cache_size_unified sh_cache_size_icache 140 extern int sh_cache_size_icache; 141 extern int sh_cache_size_dcache; 142 extern int sh_cache_line_size; 143 /* for n-way set associative cache */ 144 extern int sh_cache_way_size; 145 extern int sh_cache_way_shift; 146 extern int sh_cache_entry_mask; 147 148 /* Special mode */ 149 extern int sh_cache_ram_mode; 150 extern int sh_cache_index_mode_icache; 151 extern int sh_cache_index_mode_dcache; 152 153 extern int sh_cache_prefer_mask; 154 155 extern struct sh_cache_ops sh_cache_ops; 156 157 #define sh_icache_sync_all() \ 158 (*sh_cache_ops._icache_sync_all)() 159 160 #define sh_icache_sync_range(v, s) \ 161 (*sh_cache_ops._icache_sync_range)((v), (s)) 162 163 #define sh_icache_sync_range_index(v, s) \ 164 (*sh_cache_ops._icache_sync_range_index)((v), (s)) 165 166 #define sh_dcache_wbinv_all() \ 167 (*sh_cache_ops._dcache_wbinv_all)() 168 169 #define sh_dcache_wbinv_range(v, s) \ 170 (*sh_cache_ops._dcache_wbinv_range)((v), (s)) 171 172 #define sh_dcache_wbinv_range_index(v, s) \ 173 (*sh_cache_ops._dcache_wbinv_range_index)((v), (s)) 174 175 #define sh_dcache_inv_range(v, s) \ 176 (*sh_cache_ops._dcache_inv_range)((v), (s)) 177 178 #define sh_dcache_wb_range(v, s) \ 179 (*sh_cache_ops._dcache_wb_range)((v), (s)) 180 181 void sh_cache_init(void); 182 void sh_cache_information(void); 183 184 #define SH_HAS_UNIFIED_CACHE CPU_IS_SH3 185 #define SH_HAS_VIRTUAL_ALIAS CPU_IS_SH4 186 #define SH_HAS_WRITEBACK_CACHE (!sh_cache_write_through) 187 188 #endif /* _KERNEL */ 189 #endif /* _SH_CACHE_H_ */ 190