1 /* $OpenBSD: cpu.h,v 1.28 2019/03/24 06:09:09 visa Exp $ */ 2 /* $NetBSD: cpu.h,v 1.41 2006/01/21 04:24:12 uwe Exp $ */ 3 4 /*- 5 * Copyright (c) 2002 The NetBSD Foundation, Inc. All rights reserved. 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 37 */ 38 39 /* 40 * SH3/SH4 support. 41 * 42 * T.Horiuchi Brains Corp. 5/22/98 43 */ 44 45 #ifndef _SH_CPU_H_ 46 #define _SH_CPU_H_ 47 48 #include <sh/psl.h> 49 #include <sh/frame.h> 50 51 #ifdef _KERNEL 52 53 /* 54 * Per-CPU information. 55 */ 56 57 #include <machine/intr.h> 58 #include <sys/sched.h> 59 60 struct cpu_info { 61 struct proc *ci_curproc; 62 63 struct schedstate_percpu ci_schedstate; /* scheduler state */ 64 u_int32_t ci_randseed; 65 #ifdef DIAGNOSTIC 66 int ci_mutex_level; 67 #endif 68 #ifdef GPROF 69 struct gmonparam *ci_gmon; 70 #endif 71 }; 72 73 extern struct cpu_info cpu_info_store; 74 #define curcpu() (&cpu_info_store) 75 #define cpu_number() 0 76 #define CPU_IS_PRIMARY(ci) 1 77 #define CPU_INFO_ITERATOR int 78 #define CPU_INFO_FOREACH(cii, ci) \ 79 for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL) 80 #define CPU_INFO_UNIT(ci) 0 81 #define MAXCPUS 1 82 #define cpu_unidle(ci) 83 84 #define CPU_BUSY_CYCLE() do {} while (0) 85 86 87 /* 88 * Arguments to hardclock and gatherstats encapsulate the previous 89 * machine state in an opaque clockframe. 90 */ 91 struct clockframe { 92 int spc; /* program counter at time of interrupt */ 93 int ssr; /* status register at time of interrupt */ 94 int ssp; /* stack pointer at time of interrupt */ 95 }; 96 97 #define CLKF_USERMODE(cf) (!KERNELMODE((cf)->ssr)) 98 #define CLKF_PC(cf) ((cf)->spc) 99 #define CLKF_INTR(cf) 0 /* XXX */ 100 101 /* 102 * This is used during profiling to integrate system time. It can safely 103 * assume that the process is resident. 104 */ 105 #define PROC_PC(p) ((p)->p_md.md_regs->tf_spc) 106 #define PROC_STACK(p) ((p)->p_md.md_regs->tf_r15) 107 108 /* 109 * Preempt the current process if in interrupt from user mode, 110 * or after the current trap/syscall if in system mode. 111 */ 112 #define need_resched(ci) \ 113 do { \ 114 want_resched = 1; \ 115 if (curproc != NULL) \ 116 aston(curproc); \ 117 } while (/*CONSTCOND*/0) 118 #define clear_resched(ci) want_resched = 0 119 120 /* 121 * Give a profiling tick to the current process when the user profiling 122 * buffer pages are invalid. On the MIPS, request an ast to send us 123 * through trap, marking the proc as needing a profiling tick. 124 */ 125 #define need_proftick(p) aston(p) 126 127 /* 128 * Notify the current process (p) that it has a signal pending, 129 * process as soon as possible. 130 */ 131 #define signotify(p) aston(p) 132 133 #define aston(p) ((p)->p_md.md_astpending = 1) 134 135 extern int want_resched; /* need_resched() was called */ 136 137 /* 138 * We need a machine-independent name for this. 139 */ 140 #define DELAY(x) delay(x) 141 142 #define cpu_idle_enter() do { /* nothing */ } while (0) 143 #define cpu_idle_cycle() __asm volatile("sleep") 144 #define cpu_idle_leave() do { /* nothing */ } while (0) 145 146 #endif /* _KERNEL */ 147 148 /* 149 * Logical address space of SH3/SH4 CPU. 150 */ 151 #define SH3_PHYS_MASK 0x1fffffff 152 153 #define SH3_P0SEG_BASE 0x00000000 /* TLB mapped, also U0SEG */ 154 #define SH3_P0SEG_END 0x7fffffff 155 #define SH3_P1SEG_BASE 0x80000000 /* pa == va */ 156 #define SH3_P1SEG_END 0x9fffffff 157 #define SH3_P2SEG_BASE 0xa0000000 /* pa == va, non-cacheable */ 158 #define SH3_P2SEG_END 0xbfffffff 159 #define SH3_P3SEG_BASE 0xc0000000 /* TLB mapped, kernel mode */ 160 #define SH3_P3SEG_END 0xdfffffff 161 #define SH3_P4SEG_BASE 0xe0000000 /* peripheral space */ 162 #define SH3_P4SEG_END 0xffffffff 163 164 #define SH3_P1SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK) 165 #define SH3_P2SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK) 166 #define SH3_PHYS_TO_P1SEG(x) ((uint32_t)(x) | SH3_P1SEG_BASE) 167 #define SH3_PHYS_TO_P2SEG(x) ((uint32_t)(x) | SH3_P2SEG_BASE) 168 #define SH3_P1SEG_TO_P2SEG(x) ((uint32_t)(x) | 0x20000000) 169 #define SH3_P2SEG_TO_P1SEG(x) ((uint32_t)(x) & ~0x20000000) 170 171 #ifdef _KERNEL 172 #ifndef __lint__ 173 174 /* 175 * Switch from P1 (cached) to P2 (uncached). This used to be written 176 * using gcc's assigned goto extension, but gcc4 aggressive optimizations 177 * tend to optimize that away under certain circumstances. 178 */ 179 #define RUN_P2 \ 180 do { \ 181 register uint32_t r0 asm("r0"); \ 182 uint32_t pc; \ 183 __asm volatile( \ 184 " mov.l 1f, %1 ;" \ 185 " mova 2f, %0 ;" \ 186 " or %0, %1 ;" \ 187 " jmp @%1 ;" \ 188 " nop ;" \ 189 " .align 2 ;" \ 190 "1: .long 0x20000000;" \ 191 "2:;" \ 192 : "=r"(r0), "=r"(pc)); \ 193 } while (0) 194 195 /* 196 * Switch from P2 (uncached) back to P1 (cached). We need to be 197 * running on P2 to access cache control, memory-mapped cache and TLB 198 * arrays, etc. and after touching them at least 8 instructinos are 199 * necessary before jumping to P1, so provide that padding here. 200 */ 201 #define RUN_P1 \ 202 do { \ 203 register uint32_t r0 asm("r0"); \ 204 uint32_t pc; \ 205 __asm volatile( \ 206 /*1*/ " mov.l 1f, %1 ;" \ 207 /*2*/ " mova 2f, %0 ;" \ 208 /*3*/ " nop ;" \ 209 /*4*/ " and %0, %1 ;" \ 210 /*5*/ " nop ;" \ 211 /*6*/ " nop ;" \ 212 /*7*/ " nop ;" \ 213 /*8*/ " nop ;" \ 214 " jmp @%1 ;" \ 215 " nop ;" \ 216 " .align 2 ;" \ 217 "1: .long ~0x20000000;" \ 218 "2:;" \ 219 : "=r"(r0), "=r"(pc)); \ 220 } while (0) 221 222 /* 223 * If RUN_P1 is the last thing we do in a function we can omit it, b/c 224 * we are going to return to a P1 caller anyway, but we still need to 225 * ensure there's at least 8 instructions before jump to P1. 226 */ 227 #define PAD_P1_SWITCH __asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop;") 228 229 #else /* __lint__ */ 230 #define RUN_P2 do {} while (/* CONSTCOND */ 0) 231 #define RUN_P1 do {} while (/* CONSTCOND */ 0) 232 #define PAD_P1_SWITCH do {} while (/* CONSTCOND */ 0) 233 #endif 234 #endif 235 236 #if defined(SH4) 237 /* SH4 Processor Version Register */ 238 #define SH4_PVR_ADDR 0xff000030 /* P4 address */ 239 #define SH4_PVR (*(volatile uint32_t *) SH4_PVR_ADDR) 240 #define SH4_PRR_ADDR 0xff000044 /* P4 address */ 241 #define SH4_PRR (*(volatile uint32_t *) SH4_PRR_ADDR) 242 243 #define SH4_PVR_MASK 0xffffff00 244 #define SH4_PVR_SH7750 0x04020500 /* SH7750 */ 245 #define SH4_PVR_SH7750S 0x04020600 /* SH7750S */ 246 #define SH4_PVR_SH775xR 0x04050000 /* SH775xR */ 247 #define SH4_PVR_SH7751 0x04110000 /* SH7751 */ 248 249 #define SH4_PRR_MASK 0xfffffff0 250 #define SH4_PRR_7750R 0x00000100 /* SH7750R */ 251 #define SH4_PRR_7751R 0x00000110 /* SH7751R */ 252 #endif 253 254 /* 255 * pull in #defines for kinds of processors 256 */ 257 #include <machine/cputypes.h> 258 259 #ifdef _KERNEL 260 void sh_cpu_init(int, int); 261 void sh_startup(void); 262 __dead void cpu_reset(void); /* soft reset */ 263 void _cpu_spin(uint32_t); /* for delay loop. */ 264 void delay(int); 265 struct pcb; 266 void savectx(struct pcb *); 267 struct fpreg; 268 void fpu_save(struct fpreg *); 269 void fpu_restore(struct fpreg *); 270 u_int cpu_dump(int (*)(dev_t, daddr_t, caddr_t, size_t), daddr_t *); 271 u_int cpu_dumpsize(void); 272 void dumpconf(void); 273 void dumpsys(void); 274 275 static inline u_long 276 intr_disable(void) 277 { 278 return (u_long)_cpu_intr_suspend(); 279 } 280 281 static inline void 282 intr_restore(u_long s) 283 { 284 _cpu_intr_resume((int)s); 285 } 286 #endif /* _KERNEL */ 287 #endif /* !_SH_CPU_H_ */ 288