1 /* $OpenBSD: cpu.h,v 1.19 2009/03/26 17:24:33 oga Exp $ */ 2 /* $NetBSD: cpu.h,v 1.41 2006/01/21 04:24:12 uwe Exp $ */ 3 4 /*- 5 * Copyright (c) 2002 The NetBSD Foundation, Inc. All rights reserved. 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 37 */ 38 39 /* 40 * SH3/SH4 support. 41 * 42 * T.Horiuchi Brains Corp. 5/22/98 43 */ 44 45 #ifndef _SH_CPU_H_ 46 #define _SH_CPU_H_ 47 48 #include <sh/psl.h> 49 #include <sh/frame.h> 50 51 #ifdef _KERNEL 52 53 /* 54 * Per-CPU information. 55 */ 56 57 #include <sys/sched.h> 58 struct cpu_info { 59 struct proc *ci_curproc; 60 61 struct schedstate_percpu ci_schedstate; /* scheduler state */ 62 u_int32_t ci_randseed; 63 }; 64 65 extern struct cpu_info cpu_info_store; 66 #define curcpu() (&cpu_info_store) 67 #define cpu_number() 0 68 #define CPU_IS_PRIMARY(ci) 1 69 #define CPU_INFO_ITERATOR int 70 #define CPU_INFO_FOREACH(cii, ci) \ 71 for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL) 72 #define CPU_INFO_UNIT(ci) 0 73 #define MAXCPUS 1 74 #define cpu_unidle(ci) 75 76 77 /* 78 * Arguments to hardclock and gatherstats encapsulate the previous 79 * machine state in an opaque clockframe. 80 */ 81 struct clockframe { 82 int spc; /* program counter at time of interrupt */ 83 int ssr; /* status register at time of interrupt */ 84 int ssp; /* stack pointer at time of interrupt */ 85 }; 86 87 #define CLKF_USERMODE(cf) (!KERNELMODE((cf)->ssr)) 88 #define CLKF_PC(cf) ((cf)->spc) 89 #define CLKF_INTR(cf) 0 /* XXX */ 90 91 /* 92 * This is used during profiling to integrate system time. It can safely 93 * assume that the process is resident. 94 */ 95 #define PROC_PC(p) \ 96 (((struct trapframe *)(p)->p_md.md_regs)->tf_spc) 97 98 /* 99 * Preempt the current process if in interrupt from user mode, 100 * or after the current trap/syscall if in system mode. 101 */ 102 #define need_resched(ci) \ 103 do { \ 104 want_resched = 1; \ 105 if (curproc != NULL) \ 106 aston(curproc); \ 107 } while (/*CONSTCOND*/0) 108 #define clear_resched(ci) want_resched = 0 109 110 /* 111 * Give a profiling tick to the current process when the user profiling 112 * buffer pages are invalid. On the MIPS, request an ast to send us 113 * through trap, marking the proc as needing a profiling tick. 114 */ 115 #define need_proftick(p) aston(p) 116 117 /* 118 * Notify the current process (p) that it has a signal pending, 119 * process as soon as possible. 120 */ 121 #define signotify(p) aston(p) 122 123 #define aston(p) ((p)->p_md.md_astpending = 1) 124 125 extern int want_resched; /* need_resched() was called */ 126 127 /* 128 * We need a machine-independent name for this. 129 */ 130 #define DELAY(x) delay(x) 131 132 #define cpu_idle_enter() do { /* nothing */ } while (0) 133 #define cpu_idle_cycle() __asm volatile("sleep") 134 #define cpu_idle_leave() do { /* nothing */ } while (0) 135 136 #endif /* _KERNEL */ 137 138 /* 139 * Logical address space of SH3/SH4 CPU. 140 */ 141 #define SH3_PHYS_MASK 0x1fffffff 142 143 #define SH3_P0SEG_BASE 0x00000000 /* TLB mapped, also U0SEG */ 144 #define SH3_P0SEG_END 0x7fffffff 145 #define SH3_P1SEG_BASE 0x80000000 /* pa == va */ 146 #define SH3_P1SEG_END 0x9fffffff 147 #define SH3_P2SEG_BASE 0xa0000000 /* pa == va, non-cacheable */ 148 #define SH3_P2SEG_END 0xbfffffff 149 #define SH3_P3SEG_BASE 0xc0000000 /* TLB mapped, kernel mode */ 150 #define SH3_P3SEG_END 0xdfffffff 151 #define SH3_P4SEG_BASE 0xe0000000 /* peripheral space */ 152 #define SH3_P4SEG_END 0xffffffff 153 154 #define SH3_P1SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK) 155 #define SH3_P2SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK) 156 #define SH3_PHYS_TO_P1SEG(x) ((uint32_t)(x) | SH3_P1SEG_BASE) 157 #define SH3_PHYS_TO_P2SEG(x) ((uint32_t)(x) | SH3_P2SEG_BASE) 158 #define SH3_P1SEG_TO_P2SEG(x) ((uint32_t)(x) | 0x20000000) 159 #define SH3_P2SEG_TO_P1SEG(x) ((uint32_t)(x) & ~0x20000000) 160 161 #ifdef _KERNEL 162 #ifndef __lint__ 163 164 /* 165 * Switch from P1 (cached) to P2 (uncached). This used to be written 166 * using gcc's assigned goto extension, but gcc4 aggressive optimizations 167 * tend to optimize that away under certain circumstances. 168 */ 169 #define RUN_P2 \ 170 do { \ 171 register uint32_t r0 asm("r0"); \ 172 uint32_t pc; \ 173 __asm volatile( \ 174 " mov.l 1f, %1 ;" \ 175 " mova 2f, %0 ;" \ 176 " or %0, %1 ;" \ 177 " jmp @%1 ;" \ 178 " nop ;" \ 179 " .align 2 ;" \ 180 "1: .long 0x20000000;" \ 181 "2:;" \ 182 : "=r"(r0), "=r"(pc)); \ 183 } while (0) 184 185 /* 186 * Switch from P2 (uncached) back to P1 (cached). We need to be 187 * running on P2 to access cache control, memory-mapped cache and TLB 188 * arrays, etc. and after touching them at least 8 instructinos are 189 * necessary before jumping to P1, so provide that padding here. 190 */ 191 #define RUN_P1 \ 192 do { \ 193 register uint32_t r0 asm("r0"); \ 194 uint32_t pc; \ 195 __asm volatile( \ 196 /*1*/ " mov.l 1f, %1 ;" \ 197 /*2*/ " mova 2f, %0 ;" \ 198 /*3*/ " nop ;" \ 199 /*4*/ " and %0, %1 ;" \ 200 /*5*/ " nop ;" \ 201 /*6*/ " nop ;" \ 202 /*7*/ " nop ;" \ 203 /*8*/ " nop ;" \ 204 " jmp @%1 ;" \ 205 " nop ;" \ 206 " .align 2 ;" \ 207 "1: .long ~0x20000000;" \ 208 "2:;" \ 209 : "=r"(r0), "=r"(pc)); \ 210 } while (0) 211 212 /* 213 * If RUN_P1 is the last thing we do in a function we can omit it, b/c 214 * we are going to return to a P1 caller anyway, but we still need to 215 * ensure there's at least 8 instructions before jump to P1. 216 */ 217 #define PAD_P1_SWITCH __asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop;") 218 219 #else /* __lint__ */ 220 #define RUN_P2 do {} while (/* CONSTCOND */ 0) 221 #define RUN_P1 do {} while (/* CONSTCOND */ 0) 222 #define PAD_P1_SWITCH do {} while (/* CONSTCOND */ 0) 223 #endif 224 #endif 225 226 #if defined(SH4) 227 /* SH4 Processor Version Register */ 228 #define SH4_PVR_ADDR 0xff000030 /* P4 address */ 229 #define SH4_PVR (*(volatile uint32_t *) SH4_PVR_ADDR) 230 #define SH4_PRR_ADDR 0xff000044 /* P4 address */ 231 #define SH4_PRR (*(volatile uint32_t *) SH4_PRR_ADDR) 232 233 #define SH4_PVR_MASK 0xffffff00 234 #define SH4_PVR_SH7750 0x04020500 /* SH7750 */ 235 #define SH4_PVR_SH7750S 0x04020600 /* SH7750S */ 236 #define SH4_PVR_SH775xR 0x04050000 /* SH775xR */ 237 #define SH4_PVR_SH7751 0x04110000 /* SH7751 */ 238 239 #define SH4_PRR_MASK 0xfffffff0 240 #define SH4_PRR_7750R 0x00000100 /* SH7750R */ 241 #define SH4_PRR_7751R 0x00000110 /* SH7751R */ 242 #endif 243 244 /* 245 * pull in #defines for kinds of processors 246 */ 247 #include <machine/cputypes.h> 248 249 #ifdef _KERNEL 250 void sh_cpu_init(int, int); 251 void sh_startup(void); 252 __dead void cpu_reset(void); /* soft reset */ 253 void _cpu_spin(uint32_t); /* for delay loop. */ 254 void delay(int); 255 struct pcb; 256 void savectx(struct pcb *); 257 struct fpreg; 258 void fpu_save(struct fpreg *); 259 void fpu_restore(struct fpreg *); 260 u_int cpu_dump(int (*)(dev_t, daddr64_t, caddr_t, size_t), daddr64_t *); 261 u_int cpu_dumpsize(void); 262 void dumpconf(void); 263 void dumpsys(void); 264 #endif /* _KERNEL */ 265 #endif /* !_SH_CPU_H_ */ 266