1 /* $OpenBSD: cpu.h,v 1.14 2008/07/18 23:43:31 art Exp $ */ 2 /* $NetBSD: cpu.h,v 1.41 2006/01/21 04:24:12 uwe Exp $ */ 3 4 /*- 5 * Copyright (c) 2002 The NetBSD Foundation, Inc. All rights reserved. 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 37 */ 38 39 /* 40 * SH3/SH4 support. 41 * 42 * T.Horiuchi Brains Corp. 5/22/98 43 */ 44 45 #ifndef _SH_CPU_H_ 46 #define _SH_CPU_H_ 47 48 #include <sh/psl.h> 49 #include <sh/frame.h> 50 51 #ifdef _KERNEL 52 53 /* 54 * Per-CPU information. 55 */ 56 57 #include <sys/sched.h> 58 struct cpu_info { 59 struct proc *ci_curproc; 60 61 struct schedstate_percpu ci_schedstate; /* scheduler state */ 62 }; 63 64 extern struct cpu_info cpu_info_store; 65 #define curcpu() (&cpu_info_store) 66 #define cpu_number() 0 67 #define CPU_IS_PRIMARY(ci) 1 68 #define CPU_INFO_ITERATOR int 69 #define CPU_INFO_FOREACH(cii, ci) \ 70 for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL) 71 72 73 /* 74 * Arguments to hardclock and gatherstats encapsulate the previous 75 * machine state in an opaque clockframe. 76 */ 77 struct clockframe { 78 int spc; /* program counter at time of interrupt */ 79 int ssr; /* status register at time of interrupt */ 80 int ssp; /* stack pointer at time of interrupt */ 81 }; 82 83 #define CLKF_USERMODE(cf) (!KERNELMODE((cf)->ssr)) 84 #define CLKF_PC(cf) ((cf)->spc) 85 #define CLKF_INTR(cf) 0 /* XXX */ 86 87 /* 88 * This is used during profiling to integrate system time. It can safely 89 * assume that the process is resident. 90 */ 91 #define PROC_PC(p) \ 92 (((struct trapframe *)(p)->p_md.md_regs)->tf_spc) 93 94 /* 95 * Preempt the current process if in interrupt from user mode, 96 * or after the current trap/syscall if in system mode. 97 */ 98 #define need_resched(ci) \ 99 do { \ 100 want_resched = 1; \ 101 if (curproc != NULL) \ 102 aston(curproc); \ 103 } while (/*CONSTCOND*/0) 104 #define clear_resched(ci) want_resched = 0 105 106 /* 107 * Give a profiling tick to the current process when the user profiling 108 * buffer pages are invalid. On the MIPS, request an ast to send us 109 * through trap, marking the proc as needing a profiling tick. 110 */ 111 #define need_proftick(p) aston(p) 112 113 /* 114 * Notify the current process (p) that it has a signal pending, 115 * process as soon as possible. 116 */ 117 #define signotify(p) aston(p) 118 119 #define aston(p) ((p)->p_md.md_astpending = 1) 120 121 extern int want_resched; /* need_resched() was called */ 122 123 #define cpu_wait(p) ((void)(p)) 124 /* 125 * We need a machine-independent name for this. 126 */ 127 #define DELAY(x) delay(x) 128 129 #define cpu_idle_enter() do { /* nothing */ } while (0) 130 #define cpu_idle_cycle() __asm volatile("sleep") 131 #define cpu_idle_leave() do { /* nothing */ } while (0) 132 133 #endif /* _KERNEL */ 134 135 /* 136 * Logical address space of SH3/SH4 CPU. 137 */ 138 #define SH3_PHYS_MASK 0x1fffffff 139 140 #define SH3_P0SEG_BASE 0x00000000 /* TLB mapped, also U0SEG */ 141 #define SH3_P0SEG_END 0x7fffffff 142 #define SH3_P1SEG_BASE 0x80000000 /* pa == va */ 143 #define SH3_P1SEG_END 0x9fffffff 144 #define SH3_P2SEG_BASE 0xa0000000 /* pa == va, non-cacheable */ 145 #define SH3_P2SEG_END 0xbfffffff 146 #define SH3_P3SEG_BASE 0xc0000000 /* TLB mapped, kernel mode */ 147 #define SH3_P3SEG_END 0xdfffffff 148 #define SH3_P4SEG_BASE 0xe0000000 /* peripheral space */ 149 #define SH3_P4SEG_END 0xffffffff 150 151 #define SH3_P1SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK) 152 #define SH3_P2SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK) 153 #define SH3_PHYS_TO_P1SEG(x) ((uint32_t)(x) | SH3_P1SEG_BASE) 154 #define SH3_PHYS_TO_P2SEG(x) ((uint32_t)(x) | SH3_P2SEG_BASE) 155 #define SH3_P1SEG_TO_P2SEG(x) ((uint32_t)(x) | 0x20000000) 156 #define SH3_P2SEG_TO_P1SEG(x) ((uint32_t)(x) & ~0x20000000) 157 158 #ifdef _KERNEL 159 #ifndef __lint__ 160 161 /* 162 * Switch from P1 (cached) to P2 (uncached). This used to be written 163 * using gcc's assigned goto extension, but gcc4 aggressive optimizations 164 * tend to optimize that away under certain circumstances. 165 */ 166 #define RUN_P2 \ 167 do { \ 168 register uint32_t r0 asm("r0"); \ 169 uint32_t pc; \ 170 __asm volatile( \ 171 " mov.l 1f, %1 ;" \ 172 " mova 2f, %0 ;" \ 173 " or %0, %1 ;" \ 174 " jmp @%1 ;" \ 175 " nop ;" \ 176 " .align 2 ;" \ 177 "1: .long 0x20000000;" \ 178 "2:;" \ 179 : "=r"(r0), "=r"(pc)); \ 180 } while (0) 181 182 /* 183 * Switch from P2 (uncached) back to P1 (cached). We need to be 184 * running on P2 to access cache control, memory-mapped cache and TLB 185 * arrays, etc. and after touching them at least 8 instructinos are 186 * necessary before jumping to P1, so provide that padding here. 187 */ 188 #define RUN_P1 \ 189 do { \ 190 register uint32_t r0 asm("r0"); \ 191 uint32_t pc; \ 192 __asm volatile( \ 193 /*1*/ " mov.l 1f, %1 ;" \ 194 /*2*/ " mova 2f, %0 ;" \ 195 /*3*/ " nop ;" \ 196 /*4*/ " and %0, %1 ;" \ 197 /*5*/ " nop ;" \ 198 /*6*/ " nop ;" \ 199 /*7*/ " nop ;" \ 200 /*8*/ " nop ;" \ 201 " jmp @%1 ;" \ 202 " nop ;" \ 203 " .align 2 ;" \ 204 "1: .long ~0x20000000;" \ 205 "2:;" \ 206 : "=r"(r0), "=r"(pc)); \ 207 } while (0) 208 209 /* 210 * If RUN_P1 is the last thing we do in a function we can omit it, b/c 211 * we are going to return to a P1 caller anyway, but we still need to 212 * ensure there's at least 8 instructions before jump to P1. 213 */ 214 #define PAD_P1_SWITCH __asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop;") 215 216 #else /* __lint__ */ 217 #define RUN_P2 do {} while (/* CONSTCOND */ 0) 218 #define RUN_P1 do {} while (/* CONSTCOND */ 0) 219 #define PAD_P1_SWITCH do {} while (/* CONSTCOND */ 0) 220 #endif 221 #endif 222 223 #if defined(SH4) 224 /* SH4 Processor Version Register */ 225 #define SH4_PVR_ADDR 0xff000030 /* P4 address */ 226 #define SH4_PVR (*(volatile uint32_t *) SH4_PVR_ADDR) 227 #define SH4_PRR_ADDR 0xff000044 /* P4 address */ 228 #define SH4_PRR (*(volatile uint32_t *) SH4_PRR_ADDR) 229 230 #define SH4_PVR_MASK 0xffffff00 231 #define SH4_PVR_SH7750 0x04020500 /* SH7750 */ 232 #define SH4_PVR_SH7750S 0x04020600 /* SH7750S */ 233 #define SH4_PVR_SH775xR 0x04050000 /* SH775xR */ 234 #define SH4_PVR_SH7751 0x04110000 /* SH7751 */ 235 236 #define SH4_PRR_MASK 0xfffffff0 237 #define SH4_PRR_7750R 0x00000100 /* SH7750R */ 238 #define SH4_PRR_7751R 0x00000110 /* SH7751R */ 239 #endif 240 241 /* 242 * pull in #defines for kinds of processors 243 */ 244 #include <machine/cputypes.h> 245 246 #ifdef _KERNEL 247 void sh_cpu_init(int, int); 248 void sh_startup(void); 249 __dead void cpu_reset(void); /* soft reset */ 250 void _cpu_spin(uint32_t); /* for delay loop. */ 251 void delay(int); 252 struct pcb; 253 void savectx(struct pcb *); 254 struct fpreg; 255 void fpu_save(struct fpreg *); 256 void fpu_restore(struct fpreg *); 257 u_int cpu_dump(int (*)(dev_t, daddr64_t, caddr_t, size_t), daddr64_t *); 258 u_int cpu_dumpsize(void); 259 void dumpconf(void); 260 void dumpsys(void); 261 #endif /* _KERNEL */ 262 #endif /* !_SH_CPU_H_ */ 263