1 /* $OpenBSD: mmu_sh4.h,v 1.2 2008/06/26 05:42:12 ray Exp $ */ 2 /* $NetBSD: mmu_sh4.h,v 1.6 2006/03/04 01:55:03 uwe Exp $ */ 3 4 /*- 5 * Copyright (c) 2002 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by UCHIYAMA Yasushi. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _SH_MMU_SH4_H_ 34 #define _SH_MMU_SH4_H_ 35 #include <sh/devreg.h> 36 37 /* ITLB 4-entry full-associative UTLB 64-entry full-associative */ 38 #define SH4_PTEH 0xff000000 39 #define SH4_PTEH_VPN_MASK 0xfffffc00 40 #define SH4_PTEH_ASID_MASK 0x000000ff 41 #define SH4_PTEL 0xff000004 42 #define SH4_PTEL_WT 0x00000001 43 #define SH4_PTEL_SH 0x00000002 44 #define SH4_PTEL_D 0x00000004 45 #define SH4_PTEL_C 0x00000008 46 #define SH4_PTEL_PR_SHIFT 5 47 #define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */ 48 #define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */ 49 #define SH4_PTEL_SZ_1K 0x00000000 50 #define SH4_PTEL_SZ_4K 0x00000010 51 #define SH4_PTEL_SZ_64K 0x00000080 52 #define SH4_PTEL_SZ_1M 0x00000090 53 #define SH4_PTEL_V 0x00000100 54 #define SH4_PTEL_HWBITS 0x1ffff1ff /* [28:12]PFN [8:0]attr. */ 55 56 #define SH4_PTEA 0xff000034 57 #define SH4_PTEA_SA_MASK 0x00000007 58 #define SH4_PTEA_SA_TC 0x00000008 59 #define SH4_TTB 0xff000008 60 #define SH4_TEA 0xff00000c 61 #define SH4_MMUCR 0xff000010 62 #define SH4_MMUCR_AT 0x00000001 63 #define SH4_MMUCR_TI 0x00000004 64 #define SH4_MMUCR_SV 0x00000100 65 #define SH4_MMUCR_SQMD 0x00000200 66 #define SH4_MMUCR_URC_SHIFT 10 67 #define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */ 68 #define SH4_MMUCR_URB_SHIFT 18 69 #define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */ 70 #define SH4_MMUCR_LRUI_SHIFT 26 71 #define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */ 72 73 #define SH4_MMUCR_MASK (SH4_MMUCR_LRUT_MASK | SH4_MMUCR_URB_MASK | \ 74 SH4_MMUCR_URC_MASK | SH4_MMUCR_SQMD | SH4_MMUCR_SV | SH4_MMUCR_AT) 75 /* 76 * memory-mapped TLB 77 * must be access from P2-area program. 78 * branch to the other area must be maed at least 8 instruction 79 * after access. 80 */ 81 #define SH4_ITLB_ENTRY 4 82 #define SH4_UTLB_ENTRY 64 83 84 /* ITLB */ 85 #define SH4_ITLB_AA 0xf2000000 86 /* address specification (common for address and data array(0,1)) */ 87 #define SH4_ITLB_E_SHIFT 8 88 #define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */ 89 /* data specification */ 90 /* address-array */ 91 #define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 92 #define SH4_ITLB_AA_V 0x00000100 93 #define SH4_ITLB_AA_VPN_SHIFT 10 94 #define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 95 /* data-array 1 */ 96 #define SH4_ITLB_DA1 0xf3000000 97 #define SH4_ITLB_DA1_SH 0x00000002 98 #define SH4_ITLB_DA1_C 0x00000008 99 #define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 100 #define SH4_ITLB_DA1_SZ_1K 0x00000000 101 #define SH4_ITLB_DA1_SZ_4K 0x00000010 102 #define SH4_ITLB_DA1_SZ_64K 0x00000080 103 #define SH4_ITLB_DA1_SZ_1M 0x00000090 104 #define SH4_ITLB_DA1_PR 0x00000040 105 #define SH4_ITLB_DA1_V 0x00000100 106 #define SH4_ITLB_DA1_PPN_SHIFT 11 107 #define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 108 /* data-array 2 */ 109 #define SH4_ITLB_DA2 0xf3800000 110 #define SH4_ITLB_DA2_SA_MASK 0x00000003 111 #define SH4_ITLB_DA2_TC 0x00000004 112 113 /* UTLB */ 114 #define SH4_UTLB_AA 0xf6000000 115 /* address specification (common for address and data array(0,1)) */ 116 #define SH4_UTLB_E_SHIFT 8 117 #define SH4_UTLB_E_MASK 0x00003f00 118 #define SH4_UTLB_A 0x00000080 119 /* data specification */ 120 /* address-array */ 121 #define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 122 #define SH4_UTLB_AA_D 0x00000200 123 #define SH4_UTLB_AA_V 0x00000100 124 #define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 125 /* data-array 1 */ 126 #define SH4_UTLB_DA1 0xf7000000 127 #define SH4_UTLB_DA1_WT 0x00000001 128 #define SH4_UTLB_DA1_SH 0x00000002 129 #define SH4_UTLB_DA1_D 0x00000004 130 #define SH4_UTLB_DA1_C 0x00000008 131 #define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 132 #define SH4_UTLB_DA1_SZ_1K 0x00000000 133 #define SH4_UTLB_DA1_SZ_4K 0x00000010 134 #define SH4_UTLB_DA1_SZ_64K 0x00000080 135 #define SH4_UTLB_DA1_SZ_1M 0x00000090 136 #define SH4_UTLB_DA1_PR_SHIFT 5 137 #define SH4_UTLB_DA1_PR_MASK 0x00000060 138 #define SH4_UTLB_DA1_V 0x00000100 139 #define SH4_UTLB_DA1_PPN_SHIFT 11 140 #define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 141 /* data-array 2 */ 142 #define SH4_UTLB_DA2 0xf7800000 143 #define SH4_UTLB_DA2_SA_MASK 0x00000003 144 #define SH4_UTLB_DA2_TC 0x00000004 145 146 #define SH4_TLB_DISABLE *(volatile uint32_t *)SH4_MMUCR = SH4_MMUCR_TI 147 #endif /* !_SH_MMU_SH4_H_ */ 148