1 /* $OpenBSD: iommureg.h,v 1.2 2001/08/18 21:30:00 jason Exp $ */ 2 /* $NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp $ */ 3 4 /* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. All advertising materials mentioning features or use of this software 26 * must display the following acknowledgement: 27 * This product includes software developed by the University of 28 * California, Berkeley and its contributors. 29 * 4. Neither the name of the University nor the names of its contributors 30 * may be used to endorse or promote products derived from this software 31 * without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 * 45 * @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 46 */ 47 48 #ifndef _SPARC64_DEV_IOMMUREG_H_ 49 #define _SPARC64_DEV_IOMMUREG_H_ 50 51 /* 52 * UltraSPARC IOMMU registers, common to both the sbus and PCI 53 * controllers. 54 */ 55 56 /* iommmu registers */ 57 struct iommureg { 58 u_int64_t iommu_cr; /* IOMMU control register */ 59 u_int64_t iommu_tsb; /* IOMMU TSB base register */ 60 u_int64_t iommu_flush; /* IOMMU flush register */ 61 }; 62 63 /* streaming buffer registers */ 64 struct iommu_strbuf { 65 u_int64_t strbuf_ctl; /* streaming buffer control reg */ 66 u_int64_t strbuf_pgflush; /* streaming buffer page flush */ 67 u_int64_t strbuf_flushsync;/* streaming buffer flush sync */ 68 }; 69 70 /* streaming buffer control register */ 71 #define STRBUF_EN 0x000000000000000001LL 72 #define STRBUF_D 0x000000000000000002LL 73 74 /* control register bits */ 75 #define IOMMUCR_TSB1K 0x000000000000000000LL /* Nummber of entries in IOTSB */ 76 #define IOMMUCR_TSB2K 0x000000000000010000LL 77 #define IOMMUCR_TSB4K 0x000000000000020000LL 78 #define IOMMUCR_TSB8K 0x000000000000030000LL 79 #define IOMMUCR_TSB16K 0x000000000000040000LL 80 #define IOMMUCR_TSB32K 0x000000000000050000LL 81 #define IOMMUCR_TSB64K 0x000000000000060000LL 82 #define IOMMUCR_TSB128K 0x000000000000070000LL 83 #define IOMMUCR_TSBMASK 0xfffffffffffff8ffffLL /* Mask for above */ 84 #define IOMMUCR_8KPG 0x000000000000000000LL /* 8K iommu page size */ 85 #define IOMMUCR_64KPG 0x000000000000000004LL /* 64K iommu page size */ 86 #define IOMMUCR_DE 0x000000000000000002LL /* Diag enable */ 87 #define IOMMUCR_EN 0x000000000000000001LL /* Enable IOMMU */ 88 89 /* 90 * IOMMU stuff 91 */ 92 #define IOTTE_V 0x8000000000000000LL /* Entry valid */ 93 #define IOTTE_64K 0x2000000000000000LL /* 8K or 64K page? */ 94 #define IOTTE_8K 0x0000000000000000LL 95 #define IOTTE_STREAM 0x1000000000000000LL /* Is page streamable? */ 96 #define IOTTE_LOCAL 0x0800000000000000LL /* Accesses to same bus segment? */ 97 #define IOTTE_PAMASK 0x000001ffffffe000LL /* Let's assume this is correct */ 98 #define IOTTE_C 0x0000000000000010LL /* Accesses to cacheable space */ 99 #define IOTTE_W 0x0000000000000002LL /* Writeable */ 100 101 /* 102 * On sun4u each bus controller has a separate IOMMU. The IOMMU has 103 * a TSB which must be page aligned and physically contiguous. Mappings 104 * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility 105 * with the CPU's MMU. 106 * 107 * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the 108 * following size segments: 109 * 110 * VA size VA base TSB size tsbsize 111 * -------- -------- --------- ------- 112 * 8MB ff800000 8K 0 113 * 16MB ff000000 16K 1 114 * 32MB fe000000 32K 2 115 * 64MB fc000000 64K 3 116 * 128MB f8000000 128K 4 117 * 256MB f0000000 256K 5 118 * 512MB e0000000 512K 6 119 * 1GB c0000000 1MB 7 120 * 121 * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use 122 * this scheme to determine the IOVA base address. Instead, bits 31-29 are 123 * used to check against the Target Address Space register in the IIi and 124 * the the IOMMU is used if they hit. God knows what goes on in the IIe. 125 * 126 */ 127 128 129 #define IOTSB_VEND (0xffffffffffffffffLL<<PGSHIFT) 130 #define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz)+10)) 131 132 #define MAKEIOTTE(pa,w,c,s) (((pa)&IOTTE_PAMASK)|((w)?IOTTE_W:0)|((c)?IOTTE_C:0)|((s)?IOTTE_STREAM:0)|(IOTTE_V|IOTTE_8K)) 133 #define IOTSBSLOT(va,sz) ((u_int)(((vaddr_t)(va))-(is->is_dvmabase))>>PGSHIFT) 134 135 /* 136 * interrupt map stuff. this belongs elsewhere. 137 */ 138 139 #define INTMAP_V 0x080000000LL /* Interrupt valid (enabled) */ 140 #define INTMAP_TID 0x07c000000LL /* UPA target ID mask */ 141 #define INTMAP_IGN 0x0000007c0LL /* Interrupt group no (sbus only). */ 142 #define INTMAP_INO 0x00000003fLL /* Interrupt number */ 143 #define INTMAP_INR (INTMAP_IGN|INTMAP_INO) 144 #define INTMAP_SBUSSLOT 0x000000018LL /* SBUS slot # */ 145 #define INTMAP_PCIBUS 0x000000010LL /* PCI bus number (A or B) */ 146 #define INTMAP_PCISLOT 0x00000000cLL /* PCI slot # */ 147 #define INTMAP_PCIINT 0x000000003LL /* PCI interrupt #A,#B,#C,#D */ 148 #define INTMAP_OBIO 0x000000020LL /* Onboard device */ 149 #define INTMAP_LSHIFT 11 /* Encode level in vector */ 150 #define INTLEVENCODE(x) (((x)&0x0f)<<INTMAP_LSHIFT) 151 #define INTLEV(x) (((x)>>INTMAP_LSHIFT)&0x0f) 152 #define INTVEC(x) ((x)&INTMAP_INR) 153 #define INTSLOT(x) (((x)>>3)&0x7) 154 #define INTPRI(x) ((x)&0x7) 155 #define INTINO(x) ((x)&INTMAP_INO) 156 157 #define INTPCI_MAXOBINO 0x16 /* maximum OBIO INO value for PCI */ 158 #define INTPCIOBINOX(x) ((x)&0x1f) /* OBIO ino index (for PCI machines) */ 159 #define INTPCIINOX(x) (((x)&0x1c)>>2) /* PCI ino index */ 160 161 #endif /* _SPARC64_DEV_IOMMUREG_H_ */ 162