1 /* $OpenBSD: vpci.c,v 1.20 2016/05/19 09:18:42 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2008 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/device.h> 20 #include <sys/errno.h> 21 #include <sys/malloc.h> 22 #include <sys/systm.h> 23 24 #include <uvm/uvm_extern.h> 25 26 #define _SPARC_BUS_DMA_PRIVATE 27 #include <machine/bus.h> 28 #include <machine/autoconf.h> 29 #include <machine/hypervisor.h> 30 #include <machine/openfirm.h> 31 32 #include <dev/pci/pcivar.h> 33 #include <dev/pci/pcireg.h> 34 35 #include <sparc64/dev/viommuvar.h> 36 #include <sparc64/dev/msivar.h> 37 38 extern struct sparc_pci_chipset _sparc_pci_chipset; 39 40 struct vpci_msi_msg { 41 uint32_t mm_version; 42 uint8_t mm_reserved[3]; 43 uint8_t mm_type; 44 uint64_t mm_sysino; 45 uint64_t mm_reserved1; 46 uint64_t mm_stick; 47 uint16_t mm_reserved2[3]; 48 uint16_t mm_reqid; 49 uint64_t mm_addr; 50 uint64_t mm_data; 51 uint64_t mm_reserved3; 52 }; 53 54 struct vpci_range { 55 u_int32_t cspace; 56 u_int32_t child_hi; 57 u_int32_t child_lo; 58 u_int32_t phys_hi; 59 u_int32_t phys_lo; 60 u_int32_t size_hi; 61 u_int32_t size_lo; 62 }; 63 64 struct vpci_pbm { 65 struct vpci_softc *vp_sc; 66 uint64_t vp_devhandle; 67 68 struct vpci_range *vp_range; 69 pci_chipset_tag_t vp_pc; 70 int vp_nrange; 71 72 bus_space_tag_t vp_memt; 73 bus_space_tag_t vp_iot; 74 bus_dma_tag_t vp_dmat; 75 struct iommu_state vp_is; 76 77 struct msi_eq *vp_meq; 78 bus_addr_t vp_msiaddr; 79 int vp_msinum; 80 struct intrhand **vp_msi; 81 82 int vp_flags; 83 }; 84 85 struct vpci_softc { 86 struct device sc_dv; 87 bus_dma_tag_t sc_dmat; 88 bus_space_tag_t sc_bust; 89 int sc_node; 90 }; 91 92 int vpci_match(struct device *, void *, void *); 93 void vpci_attach(struct device *, struct device *, void *); 94 void vpci_init_iommu(struct vpci_softc *, struct vpci_pbm *); 95 void vpci_init_msi(struct vpci_softc *, struct vpci_pbm *); 96 int vpci_print(void *, const char *); 97 98 pci_chipset_tag_t vpci_alloc_chipset(struct vpci_pbm *, int, 99 pci_chipset_tag_t); 100 bus_space_tag_t vpci_alloc_mem_tag(struct vpci_pbm *); 101 bus_space_tag_t vpci_alloc_io_tag(struct vpci_pbm *); 102 bus_space_tag_t vpci_alloc_bus_tag(struct vpci_pbm *, const char *, 103 int, int, int); 104 bus_dma_tag_t vpci_alloc_dma_tag(struct vpci_pbm *); 105 106 int vpci_conf_size(pci_chipset_tag_t, pcitag_t); 107 pcireg_t vpci_conf_read(pci_chipset_tag_t, pcitag_t, int); 108 void vpci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 109 110 int vpci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 111 int vpci_bus_map(bus_space_tag_t, bus_space_tag_t, bus_addr_t, 112 bus_size_t, int, bus_space_handle_t *); 113 paddr_t vpci_bus_mmap(bus_space_tag_t, bus_space_tag_t, bus_addr_t, off_t, 114 int, int); 115 void *vpci_intr_establish(bus_space_tag_t, bus_space_tag_t, int, int, int, 116 int (*)(void *), void *, const char *); 117 void vpci_intr_ack(struct intrhand *); 118 void vpci_msi_ack(struct intrhand *); 119 120 int vpci_msi_eq_intr(void *); 121 122 int vpci_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, int, 123 bus_size_t, bus_size_t, int, bus_dmamap_t *); 124 void vpci_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 125 int vpci_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 126 void *, bus_size_t, struct proc *, int); 127 void vpci_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 128 int vpci_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, 129 bus_size_t, bus_size_t, bus_dma_segment_t *, int, int *, int); 130 int vpci_dmamem_map(bus_dma_tag_t, bus_dma_tag_t, bus_dma_segment_t *, 131 int, size_t, caddr_t *, int); 132 void vpci_dmamem_unmap(bus_dma_tag_t, bus_dma_tag_t, caddr_t, size_t); 133 134 int 135 vpci_match(struct device *parent, void *match, void *aux) 136 { 137 struct mainbus_attach_args *ma = aux; 138 139 if (strcmp(ma->ma_name, "pci") != 0) 140 return (0); 141 142 return OF_is_compatible(ma->ma_node, "SUNW,sun4v-pci"); 143 } 144 145 void 146 vpci_attach(struct device *parent, struct device *self, void *aux) 147 { 148 struct vpci_softc *sc = (struct vpci_softc *)self; 149 struct mainbus_attach_args *ma = aux; 150 struct pcibus_attach_args pba; 151 struct vpci_pbm *pbm; 152 int *busranges = NULL, nranges; 153 154 sc->sc_dmat = ma->ma_dmatag; 155 sc->sc_bust = ma->ma_bustag; 156 sc->sc_node = ma->ma_node; 157 158 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 159 if (pbm == NULL) 160 panic("vpci: can't alloc vpci pbm"); 161 162 pbm->vp_sc = sc; 163 pbm->vp_devhandle = (ma->ma_reg[0].ur_paddr >> 32) & 0x0fffffff; 164 165 if (getprop(ma->ma_node, "ranges", sizeof(struct vpci_range), 166 &pbm->vp_nrange, (void **)&pbm->vp_range)) 167 panic("vpci: can't get ranges"); 168 169 if (getprop(ma->ma_node, "bus-range", sizeof(int), &nranges, 170 (void **)&busranges)) 171 panic("vpci: can't get bus-range"); 172 173 printf(": bus %d to %d, ", busranges[0], busranges[1]); 174 175 pbm->vp_memt = vpci_alloc_mem_tag(pbm); 176 pbm->vp_iot = vpci_alloc_io_tag(pbm); 177 pbm->vp_dmat = vpci_alloc_dma_tag(pbm); 178 179 pbm->vp_pc = vpci_alloc_chipset(pbm, ma->ma_node, &_sparc_pci_chipset); 180 pbm->vp_pc->bustag = pbm->vp_memt; 181 182 vpci_init_iommu(sc, pbm); 183 vpci_init_msi(sc, pbm); 184 185 bzero(&pba, sizeof(pba)); 186 pba.pba_busname = "pci"; 187 pba.pba_domain = pci_ndomains++; 188 pba.pba_bus = busranges[0]; 189 pba.pba_pc = pbm->vp_pc; 190 pba.pba_flags = pbm->vp_flags; 191 pba.pba_dmat = pbm->vp_dmat; 192 pba.pba_memt = pbm->vp_memt; 193 pba.pba_iot = pbm->vp_iot; 194 pba.pba_pc->conf_size = vpci_conf_size; 195 pba.pba_pc->conf_read = vpci_conf_read; 196 pba.pba_pc->conf_write = vpci_conf_write; 197 pba.pba_pc->intr_map = vpci_intr_map; 198 199 free(busranges, M_DEVBUF, 0); 200 201 config_found(&sc->sc_dv, &pba, vpci_print); 202 } 203 204 void 205 vpci_init_iommu(struct vpci_softc *sc, struct vpci_pbm *pbm) 206 { 207 struct iommu_state *is = &pbm->vp_is; 208 int tsbsize = 8; 209 u_int32_t iobase = 0x80000000; 210 char *name; 211 212 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 213 if (name == NULL) 214 panic("couldn't malloc iommu name"); 215 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 216 217 viommu_init(name, is, tsbsize, iobase); 218 is->is_devhandle = pbm->vp_devhandle; 219 } 220 221 void 222 vpci_init_msi(struct vpci_softc *sc, struct vpci_pbm *pbm) 223 { 224 u_int32_t msi_addr_range[3]; 225 u_int32_t msi_eq_devino[3] = { 0, 36, 24 }; 226 uint64_t sysino; 227 int msis, msi_eq_size; 228 int err; 229 230 if (OF_getprop(sc->sc_node, "msi-address-ranges", 231 msi_addr_range, sizeof(msi_addr_range)) <= 0) 232 return; 233 pbm->vp_msiaddr = msi_addr_range[1]; 234 pbm->vp_msiaddr |= ((bus_addr_t)msi_addr_range[0]) << 32; 235 236 msis = getpropint(sc->sc_node, "#msi", 256); 237 pbm->vp_msi = mallocarray(msis, sizeof(*pbm->vp_msi), M_DEVBUF, 238 M_NOWAIT | M_ZERO); 239 if (pbm->vp_msi == NULL) 240 return; 241 242 msi_eq_size = getpropint(sc->sc_node, "msi-eq-size", 256); 243 pbm->vp_meq = msi_eq_alloc(sc->sc_dmat, msi_eq_size); 244 if (pbm->vp_meq == NULL) 245 goto free_table; 246 247 err = hv_pci_msiq_conf(pbm->vp_devhandle, 0, 248 pbm->vp_meq->meq_map->dm_segs[0].ds_addr, 249 pbm->vp_meq->meq_nentries); 250 if (err != H_EOK) 251 goto free_queue; 252 253 OF_getprop(sc->sc_node, "msi-eq-to-devino", 254 msi_eq_devino, sizeof(msi_eq_devino)); 255 err = hv_intr_devino_to_sysino(pbm->vp_devhandle, 256 msi_eq_devino[2], &sysino); 257 if (err != H_EOK) 258 goto disable_queue; 259 260 if (vpci_intr_establish(sc->sc_bust, sc->sc_bust, sysino, 261 IPL_HIGH, 0, vpci_msi_eq_intr, pbm, sc->sc_dv.dv_xname) == NULL) 262 goto disable_queue; 263 264 err = hv_pci_msiq_setvalid(pbm->vp_devhandle, 0, PCI_MSIQ_VALID); 265 if (err != H_EOK) { 266 printf("%s: pci_msiq_setvalid: err %d\n", __func__, err); 267 goto disable_queue; 268 } 269 270 err = hv_pci_msiq_setstate(pbm->vp_devhandle, 0, PCI_MSIQSTATE_IDLE); 271 if (err != H_EOK) { 272 printf("%s: pci_msiq_setstate: err %d\n", __func__, err); 273 goto disable_queue; 274 } 275 276 pbm->vp_flags |= PCI_FLAGS_MSI_ENABLED; 277 return; 278 279 disable_queue: 280 hv_pci_msiq_conf(pbm->vp_devhandle, 0, 0, 0); 281 free_queue: 282 msi_eq_free(sc->sc_dmat, pbm->vp_meq); 283 free_table: 284 free(pbm->vp_msi, M_DEVBUF, 0); 285 } 286 287 int 288 vpci_print(void *aux, const char *p) 289 { 290 if (p == NULL) 291 return (UNCONF); 292 return (QUIET); 293 } 294 295 int 296 vpci_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 297 { 298 return PCIE_CONFIG_SPACE_SIZE; 299 } 300 301 pcireg_t 302 vpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 303 { 304 struct vpci_pbm *pbm = pc->cookie; 305 uint64_t error_flag, data; 306 307 hv_pci_config_get(pbm->vp_devhandle, PCITAG_OFFSET(tag), reg, 4, 308 &error_flag, &data); 309 310 return (error_flag ? (pcireg_t)~0 : data); 311 } 312 313 void 314 vpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 315 { 316 struct vpci_pbm *pbm = pc->cookie; 317 uint64_t error_flag; 318 319 hv_pci_config_put(pbm->vp_devhandle, PCITAG_OFFSET(tag), reg, 4, 320 data, &error_flag); 321 } 322 323 /* 324 * Bus-specific interrupt mapping 325 */ 326 int 327 vpci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 328 { 329 struct vpci_pbm *pbm = pa->pa_pc->cookie; 330 uint64_t devhandle = pbm->vp_devhandle; 331 uint64_t devino = INTINO(*ihp); 332 uint64_t sysino; 333 int err; 334 335 if (*ihp != (pci_intr_handle_t)-1) { 336 err = hv_intr_devino_to_sysino(devhandle, devino, &sysino); 337 if (err != H_EOK) 338 return (-1); 339 340 KASSERT(sysino == INTVEC(sysino)); 341 *ihp = sysino; 342 return (0); 343 } 344 345 return (-1); 346 } 347 348 bus_space_tag_t 349 vpci_alloc_mem_tag(struct vpci_pbm *pp) 350 { 351 return (vpci_alloc_bus_tag(pp, "mem", 352 0x02, /* 32-bit mem space (where's the #define???) */ 353 ASI_PRIMARY, ASI_PRIMARY_LITTLE)); 354 } 355 356 bus_space_tag_t 357 vpci_alloc_io_tag(struct vpci_pbm *pp) 358 { 359 return (vpci_alloc_bus_tag(pp, "io", 360 0x01, /* IO space (where's the #define???) */ 361 ASI_PRIMARY, ASI_PRIMARY_LITTLE)); 362 } 363 364 bus_space_tag_t 365 vpci_alloc_bus_tag(struct vpci_pbm *pbm, const char *name, int ss, 366 int asi, int sasi) 367 { 368 struct vpci_softc *sc = pbm->vp_sc; 369 struct sparc_bus_space_tag *bt; 370 371 bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO); 372 if (bt == NULL) 373 panic("vpci: could not allocate bus tag"); 374 375 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)", 376 sc->sc_dv.dv_xname, name, ss, asi); 377 378 bt->cookie = pbm; 379 bt->parent = sc->sc_bust; 380 bt->default_type = ss; 381 bt->asi = asi; 382 bt->sasi = sasi; 383 bt->sparc_bus_map = vpci_bus_map; 384 bt->sparc_bus_mmap = vpci_bus_mmap; 385 bt->sparc_intr_establish = vpci_intr_establish; 386 return (bt); 387 } 388 389 bus_dma_tag_t 390 vpci_alloc_dma_tag(struct vpci_pbm *pbm) 391 { 392 struct vpci_softc *sc = pbm->vp_sc; 393 bus_dma_tag_t dt, pdt = sc->sc_dmat; 394 395 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 396 if (dt == NULL) 397 panic("vpci: could not alloc dma tag"); 398 399 dt->_cookie = pbm; 400 dt->_parent = pdt; 401 dt->_dmamap_create = vpci_dmamap_create; 402 dt->_dmamap_destroy = viommu_dvmamap_destroy; 403 dt->_dmamap_load = viommu_dvmamap_load; 404 dt->_dmamap_load_raw = viommu_dvmamap_load_raw; 405 dt->_dmamap_unload = viommu_dvmamap_unload; 406 dt->_dmamap_sync = viommu_dvmamap_sync; 407 dt->_dmamem_alloc = viommu_dvmamem_alloc; 408 dt->_dmamem_free = viommu_dvmamem_free; 409 return (dt); 410 } 411 412 pci_chipset_tag_t 413 vpci_alloc_chipset(struct vpci_pbm *pbm, int node, pci_chipset_tag_t pc) 414 { 415 pci_chipset_tag_t npc; 416 417 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 418 if (npc == NULL) 419 panic("vpci: could not allocate pci_chipset_tag_t"); 420 memcpy(npc, pc, sizeof *pc); 421 npc->cookie = pbm; 422 npc->rootnode = node; 423 return (npc); 424 } 425 426 #define BUS_DMA_FIND_PARENT(t, fn) \ 427 if (t->_parent == NULL) \ 428 panic("null bus_dma parent (" #fn ")"); \ 429 for (t = t->_parent; t->fn == NULL; t = t->_parent) \ 430 if (t->_parent == NULL) \ 431 panic("no bus_dma " #fn " located"); 432 433 int 434 vpci_dmamap_create(bus_dma_tag_t t, bus_dma_tag_t t0, bus_size_t size, 435 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 436 bus_dmamap_t *dmamap) 437 { 438 struct vpci_pbm *vp = t->_cookie; 439 440 return (viommu_dvmamap_create(t, t0, &vp->vp_is, size, nsegments, 441 maxsegsz, boundary, flags, dmamap)); 442 } 443 444 int 445 vpci_bus_map(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t offset, 446 bus_size_t size, int flags, bus_space_handle_t *hp) 447 { 448 struct vpci_pbm *pbm = t->cookie; 449 int i, ss = t->default_type; 450 451 if (t->parent == 0 || t->parent->sparc_bus_map == 0) 452 panic("vpci_bus_map: invalid parent"); 453 454 if (flags & BUS_SPACE_MAP_PROMADDRESS) { 455 return ((*t->parent->sparc_bus_map) 456 (t, t0, offset, size, flags, hp)); 457 } 458 459 for (i = 0; i < pbm->vp_nrange; i++) { 460 bus_addr_t paddr; 461 462 if (((pbm->vp_range[i].cspace >> 24) & 0x03) != ss) 463 continue; 464 465 paddr = pbm->vp_range[i].phys_lo + offset; 466 paddr |= ((bus_addr_t)pbm->vp_range[i].phys_hi) << 32; 467 return ((*t->parent->sparc_bus_map) 468 (t, t0, paddr, size, flags, hp)); 469 } 470 471 return (EINVAL); 472 } 473 474 paddr_t 475 vpci_bus_mmap(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t paddr, 476 off_t off, int prot, int flags) 477 { 478 bus_addr_t offset = paddr; 479 struct vpci_pbm *pbm = t->cookie; 480 int i, ss = t->default_type; 481 482 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) 483 panic("vpci_bus_mmap: invalid parent"); 484 485 for (i = 0; i < pbm->vp_nrange; i++) { 486 bus_addr_t paddr; 487 488 if (((pbm->vp_range[i].cspace >> 24) & 0x03) != ss) 489 continue; 490 491 paddr = pbm->vp_range[i].phys_lo + offset; 492 paddr |= ((bus_addr_t)pbm->vp_range[i].phys_hi) << 32; 493 return ((*t->parent->sparc_bus_mmap) 494 (t, t0, paddr, off, prot, flags)); 495 } 496 497 return (-1); 498 } 499 500 void * 501 vpci_intr_establish(bus_space_tag_t t, bus_space_tag_t t0, int ihandle, 502 int level, int flags, int (*handler)(void *), void *arg, const char *what) 503 { 504 struct vpci_pbm *pbm = t->cookie; 505 uint64_t sysino = INTVEC(ihandle); 506 struct intrhand *ih; 507 int err; 508 509 ih = bus_intr_allocate(t0, handler, arg, ihandle, level, 510 NULL, NULL, what); 511 if (ih == NULL) 512 return (NULL); 513 514 if (flags & BUS_INTR_ESTABLISH_MPSAFE) 515 ih->ih_mpsafe = 1; 516 517 if (ihandle & PCI_INTR_MSI) { 518 pci_chipset_tag_t pc = pbm->vp_pc; 519 pcitag_t tag = ihandle & ~PCI_INTR_MSI; 520 int msinum = pbm->vp_msinum++; 521 522 if (ih->ih_name) 523 evcount_attach(&ih->ih_count, ih->ih_name, NULL); 524 else 525 evcount_attach(&ih->ih_count, "unknown", NULL); 526 527 ih->ih_ack = vpci_msi_ack; 528 529 pbm->vp_msi[msinum] = ih; 530 ih->ih_number = msinum; 531 532 pci_msi_enable(pc, tag, pbm->vp_msiaddr, msinum); 533 534 err = hv_pci_msi_setmsiq(pbm->vp_devhandle, msinum, 0, 0); 535 if (err != H_EOK) { 536 printf("%s: pci_msi_setmsiq: err %d\n", __func__, err); 537 return (NULL); 538 } 539 540 err = hv_pci_msi_setvalid(pbm->vp_devhandle, msinum, PCI_MSI_VALID); 541 if (err != H_EOK) { 542 printf("%s: pci_msi_setvalid: err %d\n", __func__, err); 543 return (NULL); 544 } 545 546 err = hv_pci_msi_setstate(pbm->vp_devhandle, msinum, PCI_MSISTATE_IDLE); 547 if (err != H_EOK) { 548 printf("%s: pci_msi_setstate: err %d\n", __func__, err); 549 return (NULL); 550 } 551 552 return (ih); 553 } 554 555 intr_establish(ih->ih_pil, ih); 556 ih->ih_ack = vpci_intr_ack; 557 558 err = hv_intr_settarget(sysino, ih->ih_cpu->ci_upaid); 559 if (err != H_EOK) 560 return (NULL); 561 562 /* Clear pending interrupts. */ 563 err = hv_intr_setstate(sysino, INTR_IDLE); 564 if (err != H_EOK) 565 return (NULL); 566 567 err = hv_intr_setenabled(sysino, INTR_ENABLED); 568 if (err != H_EOK) 569 return (NULL); 570 571 return (ih); 572 } 573 574 void 575 vpci_intr_ack(struct intrhand *ih) 576 { 577 hv_intr_setstate(ih->ih_number, INTR_IDLE); 578 } 579 580 void 581 vpci_msi_ack(struct intrhand *ih) 582 { 583 } 584 585 int 586 vpci_msi_eq_intr(void *arg) 587 { 588 struct vpci_pbm *pbm = arg; 589 struct msi_eq *meq = pbm->vp_meq; 590 struct vpci_msi_msg *msg; 591 uint64_t head, tail; 592 struct intrhand *ih; 593 int msinum; 594 int err; 595 596 err = hv_pci_msiq_gethead(pbm->vp_devhandle, 0, &head); 597 if (err != H_EOK) 598 printf("%s: pci_msiq_gethead: %d\n", __func__, err); 599 600 err = hv_pci_msiq_gettail(pbm->vp_devhandle, 0, &tail); 601 if (err != H_EOK) 602 printf("%s: pci_msiq_gettail: %d\n", __func__, err); 603 604 if (head == tail) 605 return (0); 606 607 while (head != tail) { 608 msg = (struct vpci_msi_msg *)(meq->meq_va + head); 609 610 if (msg->mm_type == 0) 611 break; 612 msg->mm_type = 0; 613 614 msinum = msg->mm_data; 615 ih = pbm->vp_msi[msinum]; 616 err = hv_pci_msi_setstate(pbm->vp_devhandle, 617 msinum, PCI_MSISTATE_IDLE); 618 if (err != H_EOK) 619 printf("%s: pci_msi_setstate: %d\n", __func__, err); 620 621 send_softint(-1, ih->ih_pil, ih); 622 623 head += sizeof(struct vpci_msi_msg); 624 head &= ((meq->meq_nentries * sizeof(struct vpci_msi_msg)) - 1); 625 } 626 627 err = hv_pci_msiq_sethead(pbm->vp_devhandle, 0, head); 628 if (err != H_EOK) 629 printf("%s: pci_msiq_sethead: %d\n", __func__, err); 630 631 return (1); 632 } 633 634 const struct cfattach vpci_ca = { 635 sizeof(struct vpci_softc), vpci_match, vpci_attach 636 }; 637 638 struct cfdriver vpci_cd = { 639 NULL, "vpci", DV_DULL 640 }; 641