xref: /openbsd/sys/arch/sparc64/dev/zs.c (revision cecf84d4) 
1 /*	$OpenBSD: zs.c,v 1.27 2015/02/05 12:04:58 miod Exp $	*/
2 /*	$NetBSD: zs.c,v 1.29 2001/05/30 15:24:24 lukem Exp $	*/
3 
4 /*-
5  * Copyright (c) 1996 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to The NetBSD Foundation
9  * by Gordon W. Ross.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  * POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * Zilog Z8530 Dual UART driver (machine-dependent part)
35  *
36  * Runs two serial lines per chip using slave drivers.
37  * Plain tty/async lines use the zstty slave.
38  * Sun keyboard/mouse uses the zskbd/zsms slaves.
39  */
40 
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/conf.h>
44 #include <sys/device.h>
45 #include <sys/file.h>
46 #include <sys/ioctl.h>
47 #include <sys/kernel.h>
48 #include <sys/proc.h>
49 #include <sys/tty.h>
50 #include <sys/time.h>
51 #include <sys/syslog.h>
52 
53 #include <machine/autoconf.h>
54 #include <machine/openfirm.h>
55 #include <machine/conf.h>
56 #include <machine/cpu.h>
57 #include <machine/psl.h>
58 #include <machine/z8530var.h>
59 
60 #include <dev/cons.h>
61 #include <dev/ic/z8530reg.h>
62 #include <sparc64/dev/fhcvar.h>
63 #include <ddb/db_output.h>
64 
65 #include <sparc64/dev/cons.h>
66 
67 struct cfdriver zs_cd = {
68 	NULL, "zs", DV_TTY
69 };
70 
71 /*
72  * Some warts needed by z8530tty.c -
73  * The default parity REALLY needs to be the same as the PROM uses,
74  * or you can not see messages done with printf during boot-up...
75  */
76 int zs_def_cflag = (CREAD | CS8 | HUPCL);
77 int zs_major = 12;
78 
79 /*
80  * The Sun provides a 4.9152 MHz clock to the ZS chips.
81  */
82 #define PCLK	(9600 * 512)	/* PCLK pin input clock rate */
83 
84 #define	ZS_DELAY()
85 
86 /* The layout of this is hardware-dependent (padding, order). */
87 struct zschan {
88 	volatile u_char	zc_csr;		/* ctrl,status, and indirect access */
89 	u_char		zc_xxx0;
90 	volatile u_char	zc_data;	/* data */
91 	u_char		zc_xxx1;
92 };
93 struct zsdevice {
94 	/* Yes, they are backwards. */
95 	struct	zschan zs_chan_b;
96 	struct	zschan zs_chan_a;
97 };
98 
99 /* ZS channel used as the console device (if any) */
100 void *zs_conschan_get, *zs_conschan_put;
101 
102 static u_char zs_init_reg[16] = {
103 	0,	/* 0: CMD (reset, etc.) */
104 	0,	/* 1: No interrupts yet. */
105 	0,	/* 2: IVECT */
106 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
107 	ZSWR4_CLK_X16 | ZSWR4_ONESB,
108 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
109 	0,	/* 6: TXSYNC/SYNCLO */
110 	0,	/* 7: RXSYNC/SYNCHI */
111 	0,	/* 8: alias for data port */
112 	ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR,
113 	0,	/*10: Misc. TX/RX control bits */
114 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
115 	((PCLK/32)/9600)-2,	/*12: BAUDLO (default=9600) */
116 	0,			/*13: BAUDHI (default=9600) */
117 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
118 	ZSWR15_BREAK_IE,
119 };
120 
121 /* Console ops */
122 static int  zscngetc(dev_t);
123 static void zscnputc(dev_t, int);
124 static void zscnpollc(dev_t, int);
125 
126 struct consdev zs_consdev = {
127 	NULL,
128 	NULL,
129 	zscngetc,
130 	zscnputc,
131 	zscnpollc,
132 	NULL,
133 };
134 
135 
136 /****************************************************************
137  * Autoconfig
138  ****************************************************************/
139 
140 /* Definition of the driver for autoconfig. */
141 static int  zs_match_sbus(struct device *, void *, void *);
142 static void zs_attach_sbus(struct device *, struct device *, void *);
143 
144 static int  zs_match_fhc(struct device *, void *, void *);
145 static void zs_attach_fhc(struct device *, struct device *, void *);
146 
147 static void zs_attach(struct zsc_softc *, struct zsdevice *, int);
148 static int  zs_print(void *, const char *name);
149 
150 struct cfattach zs_sbus_ca = {
151 	sizeof(struct zsc_softc), zs_match_sbus, zs_attach_sbus
152 };
153 
154 struct cfattach zs_fhc_ca = {
155 	sizeof(struct zsc_softc), zs_match_fhc, zs_attach_fhc
156 };
157 
158 extern int stdinnode;
159 extern int fbnode;
160 
161 /* Interrupt handlers. */
162 static int zshard(void *);
163 static void zssoft(void *);
164 
165 static int zs_get_speed(struct zs_chanstate *);
166 
167 /* Console device support */
168 static int zs_console_flags(int, int, int);
169 
170 /*
171  * Is the zs chip present?
172  */
173 static int
174 zs_match_sbus(parent, vcf, aux)
175 	struct device *parent;
176 	void *vcf;
177 	void *aux;
178 {
179 	struct cfdata *cf = vcf;
180 	struct sbus_attach_args *sa = aux;
181 
182 	if (strcmp(cf->cf_driver->cd_name, sa->sa_name) != 0)
183 		return (0);
184 
185 	return (1);
186 }
187 
188 static int
189 zs_match_fhc(parent, vcf, aux)
190 	struct device *parent;
191 	void *vcf;
192 	void *aux;
193 {
194 	struct cfdata *cf = vcf;
195 	struct fhc_attach_args *fa = aux;
196 
197 	if (strcmp(cf->cf_driver->cd_name, fa->fa_name) != 0)
198 		return (0);
199 	return (1);
200 }
201 
202 static void
203 zs_attach_sbus(parent, self, aux)
204 	struct device *parent;
205 	struct device *self;
206 	void *aux;
207 {
208 	struct zsc_softc *zsc = (void *) self;
209 	struct sbus_attach_args *sa = aux;
210 	struct zsdevice *zsaddr;
211 	bus_space_handle_t kvaddr;
212 
213 	if (sa->sa_nintr == 0) {
214 		printf(" no interrupt lines\n");
215 		return;
216 	}
217 
218 	/* Only map registers once. */
219 	if (sa->sa_npromvaddrs) {
220 		/*
221 		 * We're converting from a 32-bit pointer to a 64-bit
222 		 * pointer.  Since the 32-bit entity is negative, but
223 		 * the kernel is still mapped into the lower 4GB
224 		 * range, this needs to be zero-extended.
225 		 *
226 		 * XXXXX If we map the kernel and devices into the
227 		 * high 4GB range, this needs to be changed to
228 		 * sign-extend the address.
229 		 */
230 		zsaddr = (struct zsdevice *)
231 		    (unsigned long int)sa->sa_promvaddrs[0];
232 	} else {
233 		if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, sa->sa_offset,
234 		    sa->sa_size, BUS_SPACE_MAP_LINEAR, 0, &kvaddr) != 0) {
235 			printf("%s @ sbus: cannot map registers\n",
236 			       self->dv_xname);
237 			return;
238 		}
239 		zsaddr = (struct zsdevice *)
240 		    bus_space_vaddr(sa->sa_bustag, kvaddr);
241 	}
242 
243 	zsc->zsc_bustag = sa->sa_bustag;
244 	zsc->zsc_dmatag = sa->sa_dmatag;
245 	zsc->zsc_promunit = getpropint(sa->sa_node, "slave", -2);
246 	zsc->zsc_node = sa->sa_node;
247 
248 	zs_attach(zsc, zsaddr, sa->sa_pri);
249 }
250 
251 static void
252 zs_attach_fhc(parent, self, aux)
253 	struct device *parent;
254 	struct device *self;
255 	void *aux;
256 {
257 	struct zsc_softc *zsc = (void *) self;
258 	struct fhc_attach_args *fa = aux;
259 	struct zsdevice *zsaddr;
260 	bus_space_handle_t kvaddr;
261 
262 	if (fa->fa_nreg < 1 && fa->fa_npromvaddrs < 1) {
263 		printf(": no registers\n");
264 		return;
265 	}
266 
267 	if (fa->fa_nintr < 1) {
268 		printf(": no interrupts\n");
269 		return;
270 	}
271 
272 	if (fa->fa_npromvaddrs) {
273 		/*
274 		 * We're converting from a 32-bit pointer to a 64-bit
275 		 * pointer.  Since the 32-bit entity is negative, but
276 		 * the kernel is still mapped into the lower 4GB
277 		 * range, this needs to be zero-extended.
278 		 *
279 		 * XXXXX If we map the kernel and devices into the
280 		 * high 4GB range, this needs to be changed to
281 		 * sign-extend the address.
282 		 */
283 		zsaddr = (struct zsdevice *)
284 		    (unsigned long int)fa->fa_promvaddrs[0];
285 	} else {
286 		if (fhc_bus_map(fa->fa_bustag, fa->fa_reg[0].fbr_slot,
287 		    fa->fa_reg[0].fbr_offset, fa->fa_reg[0].fbr_size,
288 		    BUS_SPACE_MAP_LINEAR, &kvaddr) != 0) {
289 			printf("%s @ fhc: cannot map registers\n",
290 			    self->dv_xname);
291 			return;
292 		}
293 		zsaddr = (struct zsdevice *)
294 		    bus_space_vaddr(fa->fa_bustag, kvaddr);
295 	}
296 
297 	zsc->zsc_bustag = fa->fa_bustag;
298 	zsc->zsc_dmatag = NULL;
299 	zsc->zsc_promunit = getpropint(fa->fa_node, "slave", -2);
300 	zsc->zsc_node = fa->fa_node;
301 
302 	zs_attach(zsc, zsaddr, fa->fa_intr[0]);
303 }
304 
305 /*
306  * Attach a found zs.
307  *
308  * USE ROM PROPERTY keyboard FOR KEYBOARD/MOUSE?
309  */
310 static void
311 zs_attach(zsc, zsd, pri)
312 	struct zsc_softc *zsc;
313 	struct zsdevice *zsd;
314 	int pri;
315 {
316 	struct zsc_attach_args zsc_args;
317 	struct zs_chanstate *cs;
318 	int s, channel, softpri = PIL_TTY;
319 
320 	if (zsd == NULL) {
321 		printf("configuration incomplete\n");
322 		return;
323 	}
324 
325 	printf(" softpri %d\n", softpri);
326 
327 	/*
328 	 * Initialize software state for each channel.
329 	 */
330 	for (channel = 0; channel < 2; channel++) {
331 		struct zschan *zc;
332 		struct device *child;
333 
334 		zsc_args.type = "serial";
335 		if (getproplen(zsc->zsc_node, "keyboard") == 0) {
336 			if (channel == 0)
337 				zsc_args.type = "keyboard";
338 			if (channel == 1)
339 				zsc_args.type = "mouse";
340 		}
341 
342 		zsc_args.channel = channel;
343 		cs = &zsc->zsc_cs_store[channel];
344 		zsc->zsc_cs[channel] = cs;
345 
346 		cs->cs_channel = channel;
347 		cs->cs_private = NULL;
348 		cs->cs_ops = &zsops_null;
349 		cs->cs_brg_clk = PCLK / 16;
350 
351 		zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b;
352 
353 		zsc_args.consdev = NULL;
354 		zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit,
355 						    zsc->zsc_node,
356 						    channel);
357 
358 		if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) {
359 			zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV;
360 			zsc_args.consdev = &zs_consdev;
361 		}
362 
363 		if (getproplen(zsc->zsc_node, channel == 0 ?
364 		    "port-a-ignore-cd" : "port-b-ignore-cd") == 0) {
365 			zsc_args.hwflags |= ZS_HWFLAG_NO_DCD;
366 		}
367 
368 		if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) {
369 			zs_conschan_get = zc;
370 		}
371 		if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) {
372 			zs_conschan_put = zc;
373 		}
374 		/* Childs need to set cn_dev, etc */
375 
376 		cs->cs_reg_csr  = &zc->zc_csr;
377 		cs->cs_reg_data = &zc->zc_data;
378 
379 		bcopy(zs_init_reg, cs->cs_creg, 16);
380 		bcopy(zs_init_reg, cs->cs_preg, 16);
381 
382 		/* XXX: Consult PROM properties for this?! */
383 		cs->cs_defspeed = zs_get_speed(cs);
384 		cs->cs_defcflag = zs_def_cflag;
385 
386 		/* Make these correspond to cs_defcflag (-crtscts) */
387 		cs->cs_rr0_dcd = ZSRR0_DCD;
388 		cs->cs_rr0_cts = 0;
389 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
390 		cs->cs_wr5_rts = 0;
391 
392 		/*
393 		 * Clear the master interrupt enable.
394 		 * The INTENA is common to both channels,
395 		 * so just do it on the A channel.
396 		 */
397 		if (channel == 0) {
398 			zs_write_reg(cs, 9, 0);
399 		}
400 
401 		/*
402 		 * Look for a child driver for this channel.
403 		 * The child attach will setup the hardware.
404 		 */
405 		if (!(child =
406 		      config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print))) {
407 			/* No sub-driver.  Just reset it. */
408 			u_char reset = (channel == 0) ?
409 				ZSWR9_A_RESET : ZSWR9_B_RESET;
410 			s = splzs();
411 			zs_write_reg(cs,  9, reset);
412 			splx(s);
413 		}
414 	}
415 
416 	/*
417 	 * Now safe to install interrupt handlers.
418 	 */
419 	if (bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, zshard,
420 	    zsc, zsc->zsc_dev.dv_xname) == NULL)
421 		panic("zsattach: could not establish interrupt");
422 	if (!(zsc->zsc_softintr = softintr_establish(softpri, zssoft, zsc)))
423 		panic("zsattach: could not establish soft interrupt");
424 
425 	/*
426 	 * Set the master interrupt enable and interrupt vector.
427 	 * (common to both channels, do it on A)
428 	 */
429 	cs = zsc->zsc_cs[0];
430 	s = splhigh();
431 	/* interrupt vector */
432 	zs_write_reg(cs, 2, zs_init_reg[2]);
433 	/* master interrupt control (enable) */
434 	zs_write_reg(cs, 9, zs_init_reg[9]);
435 	splx(s);
436 
437 }
438 
439 static int
440 zs_print(aux, name)
441 	void *aux;
442 	const char *name;
443 {
444 	struct zsc_attach_args *args = aux;
445 
446 	if (name != NULL)
447 		printf("%s: ", name);
448 
449 	if (args->channel != -1)
450 		printf(" channel %d", args->channel);
451 
452 	return (UNCONF);
453 }
454 
455 static int
456 zshard(arg)
457 	void *arg;
458 {
459 	struct zsc_softc *zsc = (struct zsc_softc *)arg;
460 	int rval = 0;
461 
462 	while (zsc_intr_hard(zsc))
463 		rval = 1;
464 	if ((zsc->zsc_cs[0] && zsc->zsc_cs[0]->cs_softreq) ||
465 	    (zsc->zsc_cs[1] && zsc->zsc_cs[1]->cs_softreq))
466 		softintr_schedule(zsc->zsc_softintr);
467 	return (rval);
468 }
469 
470 /*
471  * We need this only for TTY_DEBUG purposes.
472  */
473 static void
474 zssoft(arg)
475 	void *arg;
476 {
477 	struct zsc_softc *zsc = (struct zsc_softc *)arg;
478 	int s;
479 
480 	/* Make sure we call the tty layer at spltty. */
481 	s = spltty();
482 	(void)zsc_intr_soft(zsc);
483 #ifdef TTY_DEBUG
484 	{
485 		struct zstty_softc *zst0 = zsc->zsc_cs[0]->cs_private;
486 		struct zstty_softc *zst1 = zsc->zsc_cs[1]->cs_private;
487 		if (zst0->zst_overflows || zst1->zst_overflows ) {
488 			struct trapframe *frame = (struct trapframe *)arg;
489 
490 			printf("zs silo overflow from %p\n",
491 			       (long)frame->tf_pc);
492 		}
493 	}
494 #endif
495 	splx(s);
496 }
497 
498 
499 /*
500  * Compute the current baud rate given a ZS channel.
501  */
502 static int
503 zs_get_speed(cs)
504 	struct zs_chanstate *cs;
505 {
506 	int tconst;
507 
508 	tconst = zs_read_reg(cs, 12);
509 	tconst |= zs_read_reg(cs, 13) << 8;
510 	return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
511 }
512 
513 /*
514  * MD functions for setting the baud rate and control modes.
515  */
516 int
517 zs_set_speed(cs, bps)
518 	struct zs_chanstate *cs;
519 	int bps;	/* bits per second */
520 {
521 	int tconst, real_bps;
522 
523 	if (bps == 0)
524 		return (0);
525 
526 #ifdef	DIAGNOSTIC
527 	if (cs->cs_brg_clk == 0)
528 		panic("zs_set_speed");
529 #endif
530 
531 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
532 	if (tconst < 0)
533 		return (EINVAL);
534 
535 	/* Convert back to make sure we can do it. */
536 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
537 
538 	/* XXX - Allow some tolerance here? */
539 	if (real_bps != bps)
540 		return (EINVAL);
541 
542 	cs->cs_preg[12] = tconst;
543 	cs->cs_preg[13] = tconst >> 8;
544 
545 	/* Caller will stuff the pending registers. */
546 	return (0);
547 }
548 
549 int
550 zs_set_modes(cs, cflag)
551 	struct zs_chanstate *cs;
552 	int cflag;
553 {
554 	int s;
555 
556 	/*
557 	 * Output hardware flow control on the chip is horrendous:
558 	 * if carrier detect drops, the receiver is disabled, and if
559 	 * CTS drops, the transmitter is stopped IN MID CHARACTER!
560 	 * Therefore, NEVER set the HFC bit, and instead use the
561 	 * status interrupt to detect CTS changes.
562 	 */
563 	s = splzs();
564 	cs->cs_rr0_pps = 0;
565 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
566 		cs->cs_rr0_dcd = 0;
567 		if ((cflag & MDMBUF) == 0)
568 			cs->cs_rr0_pps = ZSRR0_DCD;
569 	} else
570 		cs->cs_rr0_dcd = ZSRR0_DCD;
571 	if ((cflag & CRTSCTS) != 0) {
572 		cs->cs_wr5_dtr = ZSWR5_DTR;
573 		cs->cs_wr5_rts = ZSWR5_RTS;
574 		cs->cs_rr0_cts = ZSRR0_CTS;
575 #if 0 /* JLW */
576 	} else if ((cflag & CDTRCTS) != 0) {
577 		cs->cs_wr5_dtr = 0;
578 		cs->cs_wr5_rts = ZSWR5_DTR;
579 		cs->cs_rr0_cts = ZSRR0_CTS;
580 #endif
581 	} else if ((cflag & MDMBUF) != 0) {
582 		cs->cs_wr5_dtr = 0;
583 		cs->cs_wr5_rts = ZSWR5_DTR;
584 		cs->cs_rr0_cts = ZSRR0_DCD;
585 	} else {
586 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
587 		cs->cs_wr5_rts = 0;
588 		cs->cs_rr0_cts = 0;
589 	}
590 	splx(s);
591 
592 	/* Caller will stuff the pending registers. */
593 	return (0);
594 }
595 
596 
597 /*
598  * Read or write the chip with suitable delays.
599  */
600 
601 u_char
602 zs_read_reg(cs, reg)
603 	struct zs_chanstate *cs;
604 	u_char reg;
605 {
606 	u_char val;
607 
608 	*cs->cs_reg_csr = reg;
609 	ZS_DELAY();
610 	val = *cs->cs_reg_csr;
611 	ZS_DELAY();
612 	return (val);
613 }
614 
615 void
616 zs_write_reg(cs, reg, val)
617 	struct zs_chanstate *cs;
618 	u_char reg, val;
619 {
620 	*cs->cs_reg_csr = reg;
621 	ZS_DELAY();
622 	*cs->cs_reg_csr = val;
623 	ZS_DELAY();
624 }
625 
626 u_char
627 zs_read_csr(cs)
628 	struct zs_chanstate *cs;
629 {
630 	u_char val;
631 
632 	val = *cs->cs_reg_csr;
633 	ZS_DELAY();
634 	return (val);
635 }
636 
637 void
638 zs_write_csr(cs, val)
639 	struct zs_chanstate *cs;
640 	u_char val;
641 {
642 	*cs->cs_reg_csr = val;
643 	ZS_DELAY();
644 }
645 
646 u_char
647 zs_read_data(cs)
648 	struct zs_chanstate *cs;
649 {
650 	u_char val;
651 
652 	val = *cs->cs_reg_data;
653 	ZS_DELAY();
654 	return (val);
655 }
656 
657 void
658 zs_write_data(cs, val)
659 	struct zs_chanstate *cs;
660 	u_char val;
661 {
662 	*cs->cs_reg_data = val;
663 	ZS_DELAY();
664 }
665 
666 /****************************************************************
667  * Console support functions (Sun specific!)
668  * Note: this code is allowed to know about the layout of
669  * the chip registers, and uses that to keep things simple.
670  * XXX - I think I like the mvme167 code better. -gwr
671  ****************************************************************/
672 
673 extern void Debugger(void);
674 
675 /*
676  * Handle user request to enter kernel debugger.
677  */
678 void
679 zs_abort(cs)
680 	struct zs_chanstate *cs;
681 {
682 	volatile struct zschan *zc = zs_conschan_get;
683 	int rr0;
684 
685 	/* Wait for end of break to avoid PROM abort. */
686 	/* XXX - Limit the wait? */
687 	do {
688 		rr0 = zc->zc_csr;
689 		ZS_DELAY();
690 	} while (rr0 & ZSRR0_BREAK);
691 
692 #if defined(KGDB)
693 	zskgdb(cs);
694 #elif defined(DDB)
695 	{
696 		extern int db_active;
697 
698 		if (!db_active)
699 			Debugger();
700 		else
701 			/* Debugger is probably hozed */
702 			callrom();
703 	}
704 #else
705 	printf("stopping on keyboard abort\n");
706 	callrom();
707 #endif
708 }
709 
710 
711 /*
712  * Polled input char.
713  */
714 int
715 zs_getc(arg)
716 	void *arg;
717 {
718 	volatile struct zschan *zc = arg;
719 	int s, c, rr0;
720 
721 	s = splhigh();
722 	/* Wait for a character to arrive. */
723 	do {
724 		rr0 = zc->zc_csr;
725 		ZS_DELAY();
726 	} while ((rr0 & ZSRR0_RX_READY) == 0);
727 
728 	c = zc->zc_data;
729 	ZS_DELAY();
730 	splx(s);
731 
732 	return (c);
733 }
734 
735 /*
736  * Polled output char.
737  */
738 void
739 zs_putc(arg, c)
740 	void *arg;
741 	int c;
742 {
743 	volatile struct zschan *zc = arg;
744 	int s, rr0;
745 
746 	s = splhigh();
747 
748 	/* Wait for transmitter to become ready. */
749 	do {
750 		rr0 = zc->zc_csr;
751 		ZS_DELAY();
752 	} while ((rr0 & ZSRR0_TX_READY) == 0);
753 
754 	/*
755 	 * Send the next character.
756 	 * Now you'd think that this could be followed by a ZS_DELAY()
757 	 * just like all the other chip accesses, but it turns out that
758 	 * the `transmit-ready' interrupt isn't de-asserted until
759 	 * some period of time after the register write completes
760 	 * (more than a couple instructions).  So to avoid stray
761 	 * interrupts we put in the 2us delay regardless of cpu model.
762 	 */
763 	zc->zc_data = c;
764 	delay(2);
765 
766 	splx(s);
767 }
768 
769 /*****************************************************************/
770 
771 
772 
773 
774 /*
775  * Polled console input putchar.
776  */
777 static int
778 zscngetc(dev)
779 	dev_t dev;
780 {
781 	return (zs_getc(zs_conschan_get));
782 }
783 
784 /*
785  * Polled console output putchar.
786  */
787 static void
788 zscnputc(dev, c)
789 	dev_t dev;
790 	int c;
791 {
792 	zs_putc(zs_conschan_put, c);
793 }
794 
795 int swallow_zsintrs;
796 
797 static void
798 zscnpollc(dev, on)
799 	dev_t dev;
800 	int on;
801 {
802 	/*
803 	 * Need to tell zs driver to acknowledge all interrupts or we get
804 	 * annoying spurious interrupt messages.  This is because mucking
805 	 * with spl() levels during polling does not prevent interrupts from
806 	 * being generated.
807 	 */
808 
809 	if (on)
810 		swallow_zsintrs++;
811 	else
812 		swallow_zsintrs--;
813 }
814 
815 int
816 zs_console_flags(promunit, node, channel)
817 	int promunit;
818 	int node;
819 	int channel;
820 {
821 	int cookie, flags = 0;
822 	u_int options;
823 	char buf[255];
824 
825 	/*
826 	 * We'll just to the OBP grovelling down here since that's
827 	 * the only type of firmware we support.
828 	 */
829 	options = OF_finddevice("/options");
830 
831 	/* Default to channel 0 if there are no explicit prom args */
832 	cookie = 0;
833 
834 	if (node == OF_instance_to_package(OF_stdin())) {
835 		if (OF_getprop(options, "input-device",
836 		    buf, sizeof(buf)) != -1) {
837 			if (strncmp("ttyb", buf, strlen("ttyb")) == 0)
838 				cookie = 1;
839 		}
840 
841 		if (channel == cookie)
842 			flags |= ZS_HWFLAG_CONSOLE_INPUT;
843 	}
844 
845 	if (node == OF_instance_to_package(OF_stdout())) {
846 		if (OF_getprop(options, "output-device",
847 		    buf, sizeof(buf)) != -1) {
848 			if (strncmp("ttyb", buf, strlen("ttyb")) == 0)
849 				cookie = 1;
850 		}
851 
852 		if (channel == cookie)
853 			flags |= ZS_HWFLAG_CONSOLE_OUTPUT;
854 	}
855 
856 	return (flags);
857 }
858