1 /* $OpenBSD: fpu_explode.c,v 1.6 2022/10/16 01:22:39 jsg Exp $ */ 2 /* $NetBSD: fpu_explode.c,v 1.5 2000/08/03 18:32:08 eeh Exp $ */ 3 4 /* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 42 */ 43 44 /* 45 * FPU subroutines: `explode' the machine's `packed binary' format numbers 46 * into our internal format. 47 */ 48 49 #include <sys/types.h> 50 #include <sys/systm.h> 51 52 #include <machine/ieee.h> 53 #include <machine/instr.h> 54 #include <machine/reg.h> 55 56 #include <sparc64/fpu/fpu_arith.h> 57 #include <sparc64/fpu/fpu_emu.h> 58 #include <sparc64/fpu/fpu_extern.h> 59 60 /* 61 * N.B.: in all of the following, we assume the FP format is 62 * 63 * --------------------------- 64 * | s | exponent | fraction | 65 * --------------------------- 66 * 67 * (which represents -1**s * 1.fraction * 2**exponent), so that the 68 * sign bit is way at the top (bit 31), the exponent is next, and 69 * then the remaining bits mark the fraction. A zero exponent means 70 * zero or denormalized (0.fraction rather than 1.fraction), and the 71 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 72 * 73 * Since the sign bit is always the topmost bit---this holds even for 74 * integers---we set that outside all the *tof functions. Each function 75 * returns the class code for the new number (but note that we use 76 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 77 */ 78 79 /* 80 * int -> fpn. 81 */ 82 int 83 fpu_itof(register struct fpn *fp, register u_int i) 84 { 85 86 if (i == 0) 87 return (FPC_ZERO); 88 /* 89 * The value FP_1 represents 2^FP_LG, so set the exponent 90 * there and let normalization fix it up. Convert negative 91 * numbers to sign-and-magnitude. Note that this relies on 92 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 93 */ 94 fp->fp_exp = FP_LG; 95 fp->fp_mant[0] = (fp->fp_sign && (int)i < 0) ? -i : i; 96 fp->fp_mant[1] = 0; 97 fp->fp_mant[2] = 0; 98 fp->fp_mant[3] = 0; 99 fpu_norm(fp); 100 return (FPC_NUM); 101 } 102 103 /* 104 * 64-bit int -> fpn. 105 */ 106 int 107 fpu_xtof(register struct fpn *fp, register u_int64_t i) 108 { 109 if (i == 0) 110 return (FPC_ZERO); 111 112 /* 113 * The value FP_1 represents 2^FP_LG, so set the exponent 114 * there and let normalization fix it up. Convert negative 115 * numbers to sign-and-magnitude. Note that this relies on 116 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 117 */ 118 fp->fp_exp = FP_LG2; 119 i = (fp->fp_sign && (int64_t)i < 0) ? -i : i; 120 fp->fp_mant[0] = (i >> 32) & 0xffffffff; 121 fp->fp_mant[1] = (i >> 0) & 0xffffffff; 122 fp->fp_mant[2] = 0; 123 fp->fp_mant[3] = 0; 124 fpu_norm(fp); 125 return (FPC_NUM); 126 } 127 128 #define mask(nbits) ((1L << (nbits)) - 1) 129 130 /* 131 * All external floating formats convert to internal in the same manner, 132 * as defined here. Note that only normals get an implied 1.0 inserted. 133 */ 134 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 135 if (exp == 0) { \ 136 if (allfrac == 0) \ 137 return (FPC_ZERO); \ 138 fp->fp_exp = 1 - expbias; \ 139 fp->fp_mant[0] = f0; \ 140 fp->fp_mant[1] = f1; \ 141 fp->fp_mant[2] = f2; \ 142 fp->fp_mant[3] = f3; \ 143 fpu_norm(fp); \ 144 return (FPC_NUM); \ 145 } \ 146 if (exp == (2 * expbias + 1)) { \ 147 if (allfrac == 0) \ 148 return (FPC_INF); \ 149 fp->fp_mant[0] = f0; \ 150 fp->fp_mant[1] = f1; \ 151 fp->fp_mant[2] = f2; \ 152 fp->fp_mant[3] = f3; \ 153 return (FPC_QNAN); \ 154 } \ 155 fp->fp_exp = exp - expbias; \ 156 fp->fp_mant[0] = FP_1 | f0; \ 157 fp->fp_mant[1] = f1; \ 158 fp->fp_mant[2] = f2; \ 159 fp->fp_mant[3] = f3; \ 160 return (FPC_NUM) 161 162 /* 163 * 32-bit single precision -> fpn. 164 * We assume a single occupies at most (64-FP_LG) bits in the internal 165 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 166 */ 167 int 168 fpu_stof(register struct fpn *fp, register u_int i) 169 { 170 register int exp; 171 register u_int frac, f0, f1; 172 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 173 174 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 175 frac = i & mask(SNG_FRACBITS); 176 f0 = frac >> SNG_SHIFT; 177 f1 = frac << (32 - SNG_SHIFT); 178 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 179 } 180 181 /* 182 * 64-bit double -> fpn. 183 * We assume this uses at most (96-FP_LG) bits. 184 */ 185 int 186 fpu_dtof(register struct fpn *fp, register u_int i, register u_int j) 187 { 188 register int exp; 189 register u_int frac, f0, f1, f2; 190 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 191 192 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 193 frac = i & mask(DBL_FRACBITS - 32); 194 f0 = frac >> DBL_SHIFT; 195 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 196 f2 = j << (32 - DBL_SHIFT); 197 frac |= j; 198 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 199 } 200 201 /* 202 * 128-bit extended -> fpn. 203 */ 204 int 205 fpu_qtof(register struct fpn *fp, register u_int i, register u_int j, 206 register u_int k, register u_int l) 207 { 208 register int exp; 209 register u_int frac, f0, f1, f2, f3; 210 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */ 211 212 /* 213 * Note that ext and fpn `line up', hence no shifting needed. 214 */ 215 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 216 frac = i & mask(EXT_FRACBITS - 3 * 32); 217 f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT)); 218 f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT)); 219 f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT)); 220 f3 = l << EXT_SHIFT; 221 frac |= j | k | l; 222 FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3); 223 } 224 225 /* 226 * Explode the contents of a register / regpair / regquad. 227 * If the input is a signalling NaN, an NV (invalid) exception 228 * will be set. (Note that nothing but NV can occur until ALU 229 * operations are performed.) 230 */ 231 void 232 fpu_explode(register struct fpemu *fe, register struct fpn *fp, int type, 233 int reg) 234 { 235 register u_int s, *space; 236 u_int64_t l, *xspace; 237 238 xspace = (u_int64_t *)&fe->fe_fpstate->fs_regs[reg & ~1]; 239 l = xspace[0]; 240 space = &fe->fe_fpstate->fs_regs[reg]; 241 s = space[0]; 242 fp->fp_sign = (type == FTYPE_LNG) ? l >> 63 : s >> 31; 243 fp->fp_sticky = 0; 244 DPRINTF(FPE_INSN, ("fpu_explode: ")); 245 switch (type) { 246 case FTYPE_LNG: 247 DPRINTF(FPE_INSN, ("LNG: %llx", l)); 248 s = fpu_xtof(fp, l); 249 break; 250 251 case FTYPE_INT: 252 DPRINTF(FPE_INSN, ("INT: %x", s)); 253 s = fpu_itof(fp, s); 254 break; 255 256 case FTYPE_SNG: 257 DPRINTF(FPE_INSN, ("SNG: %x", s)); 258 s = fpu_stof(fp, s); 259 break; 260 261 case FTYPE_DBL: 262 DPRINTF(FPE_INSN, ("DBL: %x %x", s, space[1])); 263 s = fpu_dtof(fp, s, space[1]); 264 break; 265 266 case FTYPE_EXT: 267 DPRINTF(FPE_INSN, ("EXT: %x %x %x %x", s, space[1], 268 space[2], space[3])); 269 s = fpu_qtof(fp, s, space[1], space[2], space[3]); 270 break; 271 272 default: 273 panic("fpu_explode"); 274 } 275 DPRINTF(FPE_INSN, ("\n")); 276 277 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 278 /* 279 * Input is a signalling NaN. All operations that return 280 * an input NaN operand put it through a ``NaN conversion'', 281 * which basically just means ``turn on the quiet bit''. 282 * We do this here so that all NaNs internally look quiet 283 * (we can tell signalling ones by their class). 284 */ 285 fp->fp_mant[0] |= FP_QUIETBIT; 286 fe->fe_cx = FSR_NV; /* assert invalid operand */ 287 s = FPC_SNAN; 288 } 289 fp->fp_class = s; 290 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' : 291 ((type == FTYPE_INT) ? 'i' : 292 ((type == FTYPE_SNG) ? 's' : 293 ((type == FTYPE_DBL) ? 'd' : 294 ((type == FTYPE_EXT) ? 'q' : '?')))), 295 reg)); 296 DUMPFPN(FPE_REG, fp); 297 DPRINTF(FPE_REG, ("\n")); 298 } 299