1 /* $OpenBSD: bus.h,v 1.30 2016/05/04 18:26:12 kettenis Exp $ */ 2 /* $NetBSD: bus.h,v 1.31 2001/09/21 15:30:41 wiz Exp $ */ 3 4 /*- 5 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1997-1999, 2001 Eduardo E. Horvath. All rights reserved. 36 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 37 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #ifndef _MACHINE_BUS_H_ 67 #define _MACHINE_BUS_H_ 68 69 #include <machine/ctlreg.h> 70 71 /* 72 * Debug hooks 73 */ 74 75 #define BSDB_ACCESS 0x01 76 #define BSDB_MAP 0x02 77 #define BSDB_ASSERT 0x04 78 #define BSDB_MAPDETAIL 0x08 79 #define BSDB_ALL_ACCESS 0x10 80 extern int bus_space_debug; 81 82 #define BSHDB_ACCESS 0x01 83 #define BSHDB_NO_ACCESS 0x02 84 85 #if defined(BUS_SPACE_DEBUG) 86 #ifndef _MACHINE_BUS_H_ 87 #include <sys/systm.h> 88 #endif 89 #define BUS_SPACE_PRINTF(l, s) do { \ 90 if(bus_space_debug & (l)) printf s; \ 91 } while(0) 92 #define BUS_SPACE_TRACE(t, h, s) do { \ 93 if ( (((bus_space_debug & BSDB_ALL_ACCESS) != 0) && \ 94 (((h).bh_flags & BSHDB_NO_ACCESS) == 0)) || \ 95 (((bus_space_debug & BSDB_ACCESS) != 0) && \ 96 (((h).bh_flags & BSHDB_ACCESS) != 0))) \ 97 printf s; \ 98 } while(0) 99 #define BUS_SPACE_SET_FLAGS(t, h, f) ((h).bh_flags |= (f)) 100 #define BUS_SPACE_CLEAR_FLAGS(t, h, f) ((h).bh_flags &= ~(f)) 101 #define BUS_SPACE_FLAG_DECL(s) int s 102 #define BUS_SPACE_SAVE_FLAGS(t, h, s) (s = (h).bh_flags) 103 #define BUS_SPACE_RESTORE_FLAGS(t, h, s) (s = (h).bh_flags) 104 #define BUS_SPACE_ASSERT(t, h, o, n) do { \ 105 if (bus_space_debug & BSDB_ASSERT) \ 106 bus_space_assert(t, &(h), o, n); \ 107 } while(0) 108 #else /* BUS_SPACE_DEBUG */ 109 #define BUS_SPACE_PRINTF(l, s) 110 #define BUS_SPACE_TRACE(t, h, s) 111 #define BUS_SPACE_SET_FLAGS(t, h, f) 112 #define BUS_SPACE_CLEAR_FLAGS(t, h, f) 113 #define BUS_SPACE_FLAG_DECL(s) 114 #define BUS_SPACE_SAVE_FLAGS(t, h, s) 115 #define BUS_SPACE_RESTORE_FLAGS(t, h, s) 116 #define BUS_SPACE_ASSERT(t, h, o, n) 117 #endif /* BUS_SPACE_DEBUG */ 118 119 120 /* 121 * UPA and SBus spaces are non-cached and big endian 122 * (except for RAM and PROM) 123 * 124 * PCI spaces are non-cached and little endian 125 */ 126 127 enum bus_type { 128 UPA_BUS_SPACE, 129 SBUS_BUS_SPACE, 130 PCI_CONFIG_BUS_SPACE, 131 PCI_IO_BUS_SPACE, 132 PCI_MEMORY_BUS_SPACE, 133 LAST_BUS_SPACE 134 }; 135 /* For backwards compatibility */ 136 #define SPARC_BUS_SPACE UPA_BUS_SPACE 137 138 /* 139 * Bus address and size types 140 */ 141 typedef const struct sparc_bus_space_tag *bus_space_tag_t; 142 typedef u_long bus_addr_t; 143 typedef u_long bus_size_t; 144 145 146 typedef struct _bus_space_handle { 147 paddr_t bh_ptr; 148 #ifdef BUS_SPACE_DEBUG 149 bus_space_tag_t bh_tag; 150 bus_size_t bh_size; 151 int bh_flags; 152 #endif 153 } bus_space_handle_t; 154 155 /* For buses which have an iospace. */ 156 #define BUS_ADDR_IOSPACE(x) ((x)>>32) 157 #define BUS_ADDR_PADDR(x) ((x)&0xffffffff) 158 #define BUS_ADDR(io, pa) ((((bus_addr_t)io)<<32)|(pa)) 159 160 /* 161 * Access methods for bus resources and address space. 162 */ 163 164 struct sparc_bus_space_tag { 165 void *cookie; 166 bus_space_tag_t parent; 167 enum bus_type default_type; 168 u_int8_t asi; 169 u_int8_t sasi; 170 char name[32]; 171 172 int (*sparc_bus_alloc)(bus_space_tag_t, 173 bus_space_tag_t, 174 bus_addr_t, bus_addr_t, 175 bus_size_t, bus_size_t, bus_size_t, 176 int, bus_addr_t *, bus_space_handle_t *); 177 178 void (*sparc_bus_free)(bus_space_tag_t, 179 bus_space_tag_t, 180 bus_space_handle_t, bus_size_t); 181 182 int (*sparc_bus_map)(bus_space_tag_t, 183 bus_space_tag_t, 184 bus_addr_t, bus_size_t, 185 int, bus_space_handle_t *); 186 187 int (*sparc_bus_protect)(bus_space_tag_t, 188 bus_space_tag_t, 189 bus_space_handle_t, bus_size_t, int); 190 191 int (*sparc_bus_unmap)(bus_space_tag_t, 192 bus_space_tag_t, 193 bus_space_handle_t, bus_size_t); 194 195 int (*sparc_bus_subregion)(bus_space_tag_t, 196 bus_space_tag_t, 197 bus_space_handle_t, bus_size_t, 198 bus_size_t, bus_space_handle_t *); 199 200 paddr_t (*sparc_bus_mmap)(bus_space_tag_t, 201 bus_space_tag_t, 202 bus_addr_t, off_t, int, int); 203 204 void *(*sparc_intr_establish)(bus_space_tag_t, 205 bus_space_tag_t, 206 int, int, int, 207 int (*)(void *), void *, 208 const char *); 209 210 bus_addr_t (*sparc_bus_addr)(bus_space_tag_t, 211 bus_space_tag_t, bus_space_handle_t); 212 }; 213 214 /* 215 * Bus space function prototypes. 216 */ 217 int bus_space_alloc( 218 bus_space_tag_t, 219 bus_addr_t, /* reg start */ 220 bus_addr_t, /* reg end */ 221 bus_size_t, /* size */ 222 bus_size_t, /* alignment */ 223 bus_size_t, /* boundary */ 224 int, /* flags */ 225 bus_addr_t *, 226 bus_space_handle_t *); 227 void bus_space_free( 228 bus_space_tag_t, 229 bus_space_handle_t, 230 bus_size_t); 231 int bus_space_map( 232 bus_space_tag_t, 233 bus_addr_t, 234 bus_size_t, 235 int, /*flags*/ 236 bus_space_handle_t *); 237 int bus_space_protect( 238 bus_space_tag_t, 239 bus_space_handle_t, 240 bus_size_t, 241 int); /*flags*/ 242 int bus_space_unmap( 243 bus_space_tag_t, 244 bus_space_handle_t, 245 bus_size_t); 246 int bus_space_subregion( 247 bus_space_tag_t, 248 bus_space_handle_t, 249 bus_size_t, 250 bus_size_t, 251 bus_space_handle_t *); 252 static void bus_space_barrier( 253 bus_space_tag_t, 254 bus_space_handle_t, 255 bus_size_t, 256 bus_size_t, 257 int); 258 paddr_t bus_space_mmap( 259 bus_space_tag_t, 260 bus_addr_t, /*addr*/ 261 off_t, /*offset*/ 262 int, /*prot*/ 263 int); /*flags*/ 264 void *bus_intr_establish( 265 bus_space_tag_t, 266 int, /*bus-specific intr*/ 267 int, /*device class level, 268 see machine/intr.h*/ 269 int, /*flags*/ 270 int (*)(void *), /*handler*/ 271 void *, /*handler arg*/ 272 const char *); /*what*/ 273 void *bus_intr_allocate( 274 bus_space_tag_t, 275 int (*)(void *), /*handler*/ 276 void *, /*handler arg*/ 277 int, /*number*/ 278 int, /*pil*/ 279 volatile u_int64_t *, /*map*/ 280 volatile u_int64_t *, /*clr*/ 281 const char *); /*what*/ 282 void bus_intr_free(void *); 283 void bus_space_render_tag( 284 bus_space_tag_t, 285 char *, 286 size_t); 287 void *bus_space_vaddr( 288 bus_space_tag_t, 289 bus_space_handle_t); 290 291 #ifdef BUS_SPACE_DEBUG 292 void bus_space_assert(bus_space_tag_t, 293 const bus_space_handle_t *, 294 bus_size_t, int); 295 void bus_space_render_tag(bus_space_tag_t, char*, size_t); 296 #endif /* BUS_SPACE_DEBUG */ 297 298 299 #define _BS_PRECALL(t,f) \ 300 while (t->f == NULL) \ 301 t = t->parent; 302 #define _BS_POSTCALL 303 304 #define _BS_CALL(t,f) \ 305 (*(t)->f) 306 307 /* flags for bus_space_barrier() */ 308 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 309 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 310 311 static inline void 312 bus_space_barrier(t, h, o, s, f) 313 bus_space_tag_t t; 314 bus_space_handle_t h; 315 bus_size_t o; 316 bus_size_t s; 317 int f; 318 { 319 #ifdef notyet 320 switch (f) { 321 case (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE): 322 membar(LoadLoad|StoreStore); 323 break; 324 case BUS_SPACE_BARRIER_READ: 325 membar(LoadLoad); 326 break; 327 case BUS_SPACE_BARRIER_WRITE: 328 membar(StoreStore); 329 break; 330 default: 331 break; 332 } 333 #else 334 membar(Sync); 335 #endif 336 } 337 338 #include <sparc64/sparc64/busop.h> 339 340 /* flags for bus space map functions */ 341 #define BUS_SPACE_MAP_CACHEABLE 0x0001 342 #define BUS_SPACE_MAP_LINEAR 0x0002 343 #define BUS_SPACE_MAP_READONLY 0x0004 344 #define BUS_SPACE_MAP_PREFETCHABLE 0x0008 345 #define BUS_SPACE_MAP_PROMADDRESS 0x0010 346 #define BUS_SPACE_MAP_BUS1 0x0100 /* placeholders for bus functions... */ 347 #define BUS_SPACE_MAP_BUS2 0x0200 348 #define BUS_SPACE_MAP_BUS3 0x0400 349 #define BUS_SPACE_MAP_BUS4 0x0800 350 351 352 /* flags for bus_intr_establish() */ 353 #define BUS_INTR_ESTABLISH_MPSAFE 0x0001 354 #define BUS_INTR_ESTABLISH_SOFTINTR 0x0002 355 356 /* 357 * Flags used in various bus DMA methods. 358 */ 359 #define BUS_DMA_WAITOK 0x0000 /* safe to sleep (pseudo-flag) */ 360 #define BUS_DMA_NOWAIT 0x0001 /* not safe to sleep */ 361 #define BUS_DMA_ALLOCNOW 0x0002 /* perform resource allocation now */ 362 #define BUS_DMA_COHERENT 0x0004 /* hint: map memory DMA coherent */ 363 #define BUS_DMA_NOWRITE 0x0008 /* I suppose the following two should default on */ 364 #define BUS_DMA_BUS1 0x0010 /* placeholders for bus functions... */ 365 #define BUS_DMA_BUS2 0x0020 366 #define BUS_DMA_BUS3 0x0040 367 #define BUS_DMA_BUS4 0x0080 368 #define BUS_DMA_STREAMING 0x0100 /* hint: sequential, unidirectional */ 369 #define BUS_DMA_READ 0x0200 /* mapping is device -> memory only */ 370 #define BUS_DMA_WRITE 0x0400 /* mapping is memory -> device only */ 371 #define BUS_DMA_ZERO 0x0800 /* zero memory in dmamem_alloc */ 372 #define BUS_DMA_OVERRUN 0x1000 /* tolerate DMA overruns */ 373 374 #define BUS_DMA_NOCACHE BUS_DMA_BUS1 375 #define BUS_DMA_DVMA BUS_DMA_BUS2 /* Don't bother with alignment */ 376 #define BUS_DMA_24BIT BUS_DMA_BUS3 /* 24bit device */ 377 378 #define BUS_DMA_RAW BUS_DMA_STREAMING 379 380 /* Forwards needed by prototypes below. */ 381 struct mbuf; 382 struct uio; 383 384 /* 385 * Operations performed by bus_dmamap_sync(). 386 */ 387 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 388 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 389 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 390 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 391 392 typedef struct sparc_bus_dma_tag *bus_dma_tag_t; 393 typedef struct sparc_bus_dmamap *bus_dmamap_t; 394 395 /* 396 * bus_dma_segment_t 397 * 398 * Describes a single contiguous DMA transaction. Values 399 * are suitable for programming into DMA registers. 400 */ 401 struct sparc_bus_dma_segment { 402 bus_addr_t ds_addr; /* DVMA address */ 403 bus_size_t ds_len; /* length of transfer */ 404 /* 405 * The following is to support bus_dmamem_alloc()'s 406 * odd interface. Only the values in the first 407 * segment are used. This means that 3/5ths of 408 * most segments are useless space (and mbufs use 1024 409 * segments). 410 */ 411 bus_size_t _ds_boundary; /* don't cross this */ 412 bus_size_t _ds_align; /* align to this */ 413 void *_ds_mlist; /* XXX - dmamap_alloc'ed pages */ 414 }; 415 typedef struct sparc_bus_dma_segment bus_dma_segment_t; 416 417 418 /* 419 * bus_dma_tag_t 420 * 421 * A machine-dependent opaque type describing the implementation of 422 * DMA for a given bus. 423 */ 424 struct sparc_bus_dma_tag { 425 void *_cookie; /* cookie used in the guts */ 426 struct sparc_bus_dma_tag* _parent; 427 428 /* 429 * DMA mapping methods. 430 */ 431 int (*_dmamap_create)(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, 432 int, bus_size_t, bus_size_t, int, bus_dmamap_t *); 433 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 434 int (*_dmamap_load)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 435 void *, bus_size_t, struct proc *, int); 436 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dma_tag_t, 437 bus_dmamap_t, struct mbuf *, int); 438 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 439 struct uio *, int); 440 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 441 bus_dma_segment_t *, int, bus_size_t, int); 442 void (*_dmamap_unload)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 443 void (*_dmamap_sync)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 444 bus_addr_t, bus_size_t, int); 445 446 /* 447 * DMA memory utility functions. 448 */ 449 int (*_dmamem_alloc)(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, 450 bus_size_t, bus_size_t, bus_dma_segment_t *, int, int *, 451 int); 452 void (*_dmamem_free)(bus_dma_tag_t, bus_dma_tag_t, 453 bus_dma_segment_t *, int); 454 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_tag_t, 455 bus_dma_segment_t *, int, size_t, caddr_t *, int); 456 void (*_dmamem_unmap)(bus_dma_tag_t, bus_dma_tag_t, caddr_t, 457 size_t); 458 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_tag_t, 459 bus_dma_segment_t *, int, off_t, int, int); 460 }; 461 462 #define _BD_PRECALL(t,f) \ 463 while (t->f == NULL) { \ 464 t = t->_parent; \ 465 } 466 #define _BD_CALL(t,f) \ 467 (*(t)->f) 468 #define _BD_POSTCALL 469 470 static inline int 471 bus_dmamap_create(bus_dma_tag_t t, bus_size_t s, int n, bus_size_t m, 472 bus_size_t b, int f, bus_dmamap_t *p) 473 { 474 int r; 475 const bus_dma_tag_t t0 = t; 476 _BD_PRECALL(t, _dmamap_create); 477 r = _BD_CALL(t, _dmamap_create)(t, t0, s, n, m, b, f, p); 478 _BD_POSTCALL; 479 return (r); 480 } 481 static inline void 482 bus_dmamap_destroy(bus_dma_tag_t t, bus_dmamap_t p) 483 { 484 const bus_dma_tag_t t0 = t; 485 _BD_PRECALL(t, _dmamap_destroy); 486 _BD_CALL(t, _dmamap_destroy)(t, t0, p); 487 _BD_POSTCALL; 488 } 489 static inline int 490 bus_dmamap_load(bus_dma_tag_t t, bus_dmamap_t m, void *b, bus_size_t s, 491 struct proc *p, int f) 492 { 493 const bus_dma_tag_t t0 = t; 494 int r; 495 _BD_PRECALL(t, _dmamap_load); 496 r = _BD_CALL(t, _dmamap_load)(t, t0, m, b, s, p, f); 497 _BD_POSTCALL; 498 return (r); 499 } 500 static inline int 501 bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t m, struct mbuf *b, 502 int f) 503 { 504 const bus_dma_tag_t t0 = t; 505 int r; 506 _BD_PRECALL(t, _dmamap_load_mbuf); 507 r = _BD_CALL(t, _dmamap_load_mbuf)(t, t0, m, b, f); 508 _BD_POSTCALL; 509 return (r); 510 } 511 static inline int 512 bus_dmamap_load_uio(bus_dma_tag_t t, bus_dmamap_t m, struct uio * u, int f) 513 { 514 const bus_dma_tag_t t0 = t; 515 int r; 516 _BD_PRECALL(t, _dmamap_load_uio); 517 r = _BD_CALL(t, _dmamap_load_uio)(t, t0, m, u, f); 518 _BD_POSTCALL; 519 return (r); 520 } 521 static inline int 522 bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t m, bus_dma_segment_t *sg, 523 int n, bus_size_t s, int f) 524 { 525 const bus_dma_tag_t t0 = t; 526 int r; 527 _BD_PRECALL(t, _dmamap_load_raw); 528 r = _BD_CALL(t, _dmamap_load_raw)(t, t0, m, sg, n, s, f); 529 _BD_POSTCALL; 530 return (r); 531 } 532 static inline void 533 bus_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t p) 534 { 535 const bus_dma_tag_t t0 = t; 536 _BD_PRECALL(t, _dmamap_unload); 537 _BD_CALL(t, _dmamap_unload)(t, t0, p); 538 _BD_POSTCALL; 539 } 540 static inline void 541 bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t p, bus_addr_t o, bus_size_t l, 542 int ops) 543 { 544 const bus_dma_tag_t t0 = t; 545 _BD_PRECALL(t, _dmamap_sync); 546 _BD_CALL(t, _dmamap_sync)(t, t0, p, o, l, ops); 547 _BD_POSTCALL; 548 } 549 static inline int 550 bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t s, bus_size_t a, bus_size_t b, 551 bus_dma_segment_t *sg, int n, int *r, int f) 552 { 553 const bus_dma_tag_t t0 = t; 554 int ret; 555 _BD_PRECALL(t, _dmamem_alloc); 556 ret = _BD_CALL(t, _dmamem_alloc)(t, t0, s, a, b, sg, n, r, f); 557 _BD_POSTCALL; 558 return (ret); 559 } 560 static inline void 561 bus_dmamem_free(bus_dma_tag_t t, bus_dma_segment_t *sg, int n) 562 { 563 const bus_dma_tag_t t0 = t; 564 _BD_PRECALL(t, _dmamem_free); 565 _BD_CALL(t, _dmamem_free)(t, t0, sg, n); 566 _BD_POSTCALL; 567 } 568 static inline int 569 bus_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *sg, int n, size_t s, 570 caddr_t *k, int f) 571 { 572 const bus_dma_tag_t t0 = t; 573 int r; 574 _BD_PRECALL(t, _dmamem_map); 575 r = _BD_CALL(t, _dmamem_map)(t, t0, sg, n, s, k, f); 576 _BD_POSTCALL; 577 return (r); 578 } 579 static inline void 580 bus_dmamem_unmap(bus_dma_tag_t t, caddr_t k, size_t s) 581 { 582 const bus_dma_tag_t t0 = t; 583 _BD_PRECALL(t, _dmamem_unmap); 584 _BD_CALL(t, _dmamem_unmap)(t, t0, k, s); 585 _BD_POSTCALL; 586 } 587 static inline paddr_t 588 bus_dmamem_mmap(bus_dma_tag_t t, bus_dma_segment_t *sg, int n, off_t o, int p, 589 int f) 590 { 591 const bus_dma_tag_t t0 = t; 592 int r; 593 _BD_PRECALL(t, _dmamem_mmap); 594 r = _BD_CALL(t, _dmamem_mmap)(t, t0, sg, n, o, p, f); 595 _BD_POSTCALL; 596 return (r); 597 } 598 599 /* 600 * bus_dmamap_t 601 * 602 * Describes a DMA mapping. 603 */ 604 struct sparc_bus_dmamap { 605 /* 606 * PRIVATE MEMBERS: not for use by machine-independent code. 607 */ 608 bus_addr_t _dm_dvmastart; /* start and size of allocated */ 609 bus_size_t _dm_dvmasize; /* DVMA segment for this map */ 610 611 bus_size_t _dm_size; /* largest DMA transfer mappable */ 612 bus_size_t _dm_maxsegsz; /* largest possible segment */ 613 bus_size_t _dm_boundary; /* don't cross this */ 614 int _dm_segcnt; /* number of segs this map can map */ 615 int _dm_flags; /* misc. flags */ 616 #define _DM_TYPE_LOAD 0 617 #define _DM_TYPE_SEGS 1 618 #define _DM_TYPE_UIO 2 619 #define _DM_TYPE_MBUF 3 620 int _dm_type; /* mapping type: raw, uio, mbuf, etc */ 621 void *_dm_source; /* source mbuf/uio/etc. for unload */ 622 623 void *_dm_cookie; /* cookie for bus-specific functions */ 624 625 /* 626 * PUBLIC MEMBERS: these are used by machine-independent code. 627 */ 628 bus_size_t dm_mapsize; /* size of the mapping */ 629 int dm_nsegs; /* # valid segments in mapping */ 630 631 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 632 }; 633 634 #endif /* _MACHINE_BUS_H_ */ 635 636