1 /* $OpenBSD: ctlreg.h,v 1.27 2016/03/07 13:21:51 naddy Exp $ */ 2 /* $NetBSD: ctlreg.h,v 1.28 2001/08/06 23:55:34 eeh Exp $ */ 3 4 /* 5 * Copyright (c) 1996-2001 Eduardo Horvath 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 */ 26 /* 27 * Copyright (c) 2001 Jake Burkholder. 28 * All rights reserved. 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 1. Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * 2. Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in the 37 * documentation and/or other materials provided with the distribution. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 45 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 46 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 47 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 48 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 49 * SUCH DAMAGE. 50 */ 51 52 #ifndef _SPARC64_CTLREG_ 53 #define _SPARC64_CTLREG_ 54 55 /* 56 * Sun 4u control registers. (includes address space definitions 57 * and some registers in control space). 58 */ 59 60 /* 61 * membar operand macros for use in other macros when # is a special 62 * character. Keep these in sync with what the hardware expects. 63 */ 64 #define C_Lookaside (0) 65 #define C_MemIssue (1) 66 #define C_Sync (2) 67 #define M_LoadLoad (0) 68 #define M_StoreLoad (1) 69 #define M_LoadStore (2) 70 #define M_StoreStore (3) 71 72 #define CMASK_SHIFT (4) 73 #define MMASK_SHIFT (0) 74 75 #define CMASK_GEN(bit) ((1 << (bit)) << CMASK_SHIFT) 76 #define MMASK_GEN(bit) ((1 << (bit)) << MMASK_SHIFT) 77 78 /* 79 * The Alternate address spaces. 80 * 81 * 0x00-0x7f are privileged 82 * 0x80-0xff can be used by users 83 */ 84 85 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 86 87 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 88 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 89 90 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 91 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 92 93 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 94 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 95 96 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 97 #define ASI_AS_IF_USER_SECONDARY_LITTIE 0x19 /* [4u] secondary user address space, little endian */ 98 99 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 100 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 101 102 #define ASI_SCRATCHPAD 0x20 /* [4v] scratchpad registers */ 103 #define ASI_MMU_CONTEXTID 0x21 /* [4v] MMU context */ 104 105 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 106 #define ASI_QUEUE 0x25 /* [4v] interrupt queue registers */ 107 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 108 109 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 110 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 111 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 112 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 113 114 #define ASI_DCACHE_INVALIDATE 0x42 /* [III] invalidate D-cache */ 115 #define ASI_DCACHE_UTAG 0x43 /* [III] diagnostic access to D-cache micro tag */ 116 #define ASI_DCACHE_SNOOP_TAG 0x44 /* [III] diagnostic access to D-cache snoop tag RAM */ 117 118 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 119 120 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 121 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 122 123 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 124 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 125 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 126 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 127 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 128 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 129 130 #define ASI_SCRATCH 0x4f /* [VI] scratch registers */ 131 132 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */ 133 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */ 134 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */ 135 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */ 136 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */ 137 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */ 138 139 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 140 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 141 142 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 143 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 144 145 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 146 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 147 148 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 149 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 150 151 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 152 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 153 #define ASI_PRIMARY_NOFAULT 0x82 /* [4u] primary address space, no fault */ 154 #define ASI_SECONDARY_NOFAULT 0x83 /* [4u] secondary address space, no fault */ 155 156 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 157 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 158 #define ASI_PRIMARY_NOFAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 159 #define ASI_SECONDARY_NOFAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 160 161 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 162 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 163 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 164 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 165 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 166 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 167 168 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 169 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 170 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 171 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 172 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 173 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 174 175 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 176 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 177 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 178 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 179 180 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 181 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 182 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 183 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 184 185 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 186 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 187 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 188 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 189 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 190 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 191 192 193 /* 194 * These are the shorter names used by Solaris 195 */ 196 197 #define ASI_N ASI_NUCLEUS 198 #define ASI_NL ASI_NUCLEUS_LITTLE 199 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 200 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 201 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 202 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 203 #define ASI_P ASI_PRIMARY 204 #define ASI_S ASI_SECONDARY 205 #define ASI_PNF ASI_PRIMARY_NOFAULT 206 #define ASI_SNF ASI_SECONDARY_NOFAULT 207 #define ASI_PL ASI_PRIMARY_LITTLE 208 #define ASI_SL ASI_SECONDARY_LITTLE 209 #define ASI_PNFL ASI_PRIMARY_NOFAULT_LITTLE 210 #define ASI_SNFL ASI_SECONDARY_NOFAULT_LITTLE 211 #define ASI_FL8_P ASI_FL8_PRIMARY 212 #define ASI_FL8_S ASI_FL8_SECONDARY 213 #define ASI_FL16_P ASI_FL16_PRIMARY 214 #define ASI_FL16_S ASI_FL16_SECONDARY 215 #define ASI_FL8_PL ASI_FL8_PRIMARY_LITTLE 216 #define ASI_FL8_SL ASI_FL8_SECONDARY_LITTLE 217 #define ASI_FL16_PL ASI_FL16_PRIMARY_LITTLE 218 #define ASI_FL16_SL ASI_FL16_SECONDARY_LITTLE 219 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 220 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 221 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 222 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 223 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 224 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 225 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 226 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 227 #define ASI_BLK_P ASI_BLOCK_PRIMARY 228 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 229 #define ASI_BLK_S ASI_BLOCK_SECONDARY 230 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 231 232 /* Alternative spellings */ 233 #define ASI_PRIMARY_NO_FAULT ASI_PRIMARY_NOFAULT 234 #define ASI_PRIMARY_NO_FAULT_LITTLE ASI_PRIMARY_NOFAULT_LITTLE 235 #define ASI_SECONDARY_NO_FAULT ASI_SECONDARY_NOFAULT 236 #define ASI_SECONDARY_NO_FAULT_LITTLE ASI_SECONDARY_NOFAULT_LITTLE 237 238 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d) 239 #define LITTLE_ASI(x) ((x) & ASI_LITTLE) 240 241 /* 242 * %tick: cpu cycle counter 243 */ 244 #define TICK_NPT 0x8000000000000000 /* trap on non priv access */ 245 #define TICK_TICKS 0x7fffffffffffffff /* counter bits */ 246 247 /* 248 * The following are 4u control registers 249 */ 250 251 /* Get the CPU's UPA port ID */ 252 #define UPA_CR_MID(x) (((x) >> 17) & 0x1f) 253 #define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG)) 254 255 /* Get the CPU's Fireplane agent ID */ 256 #define FIREPLANE_CR_AID(x) (((x) >> 17) & 0x3ff) 257 #define CPU_FIREPLANEID FIREPLANE_CR_AID(ldxa(0, ASI_MID_REG)) 258 259 /* Get the CPU's Jupiter Bus interrupt target ID */ 260 #define JUPITER_CR_ITID(x) ((x) & 0x3ff) 261 #define CPU_JUPITERID JUPITER_CR_ITID(ldxa(0, ASI_MID_REG)) 262 263 /* 264 * [4u] MMU and Cache Control Register (MCCR) 265 * use ASI = 0x45 266 */ 267 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 268 #define MCCR 0x00 269 270 /* MCCR Bits and their meanings */ 271 #define MCCR_DMMU_EN 0x08 272 #define MCCR_IMMU_EN 0x04 273 #define MCCR_DCACHE_EN 0x02 274 #define MCCR_ICACHE_EN 0x01 275 276 277 /* 278 * MMU control registers 279 */ 280 281 /* Choose an MMU */ 282 #define ASI_DMMU 0x58 283 #define ASI_IMMU 0x50 284 285 /* Other assorted MMU ASIs */ 286 #define ASI_IMMU_8KPTR 0x51 287 #define ASI_IMMU_64KPTR 0x52 288 #define ASI_IMMU_DATA_IN 0x54 289 #define ASI_IMMU_TLB_DATA 0x55 290 #define ASI_IMMU_TLB_TAG 0x56 291 #define ASI_DMMU_8KPTR 0x59 292 #define ASI_DMMU_64KPTR 0x5a 293 #define ASI_DMMU_DATA_IN 0x5c 294 #define ASI_DMMU_TLB_DATA 0x5d 295 #define ASI_DMMU_TLB_TAG 0x5e 296 297 /* 298 * The following are the control registers 299 * They work on both MMUs unless noted. 300 * III = cheetah only 301 * 302 * Register contents are defined later on individual registers. 303 */ 304 #define TSB_TAG_TARGET 0x0 305 #define TLB_DATA_IN 0x0 306 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 307 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 308 #define SFSR 0x18 309 #define SFAR 0x20 /* fault address -- DMMU only */ 310 #define TSB 0x28 311 #define TLB_TAG_ACCESS 0x30 312 #define VIRTUAL_WATCHPOINT 0x38 313 #define PHYSICAL_WATCHPOINT 0x40 314 #define TSB_PEXT 0x48 /* III primary ext */ 315 #define TSB_SEXT 0x50 /* III 2ndary ext -- DMMU only */ 316 #define TSB_NEXT 0x58 /* III nucleus ext */ 317 318 /* Tag Target bits */ 319 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 320 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 321 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 322 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 323 324 /* SFSR bits for both D_SFSR and I_SFSR */ 325 #define SFSR_NF 0x1000000 /* Non-faulting load */ 326 #define SFSR_ASI(x) ((x)>>16) 327 #define SFSR_TM 0x0008000 /* TLB miss */ 328 #define SFSR_FT_VA_OOR_2 0x0002000 /* IMMU: jumpl or return to unsupportd VA */ 329 #define SFSR_FT_VA_OOR_1 0x0001000 /* fault at unsupported VA */ 330 #define SFSR_FT_NFO 0x0000800 /* DMMU: Access to page marked NFO */ 331 #define SFSR_ILL_ASI 0x0000400 /* DMMU: Illegal (unsupported) ASI */ 332 #define SFSR_FT_IO_ATOMIC 0x0000200 /* DMMU: Atomic access to noncacheable page */ 333 #define SFSR_FT_ILL_NF 0x0000100 /* DMMU: NF load or flush to page marked E (has side effects) */ 334 #define SFSR_FT_PRIV 0x0000080 /* Privilege violation */ 335 #define SFSR_FT_E 0x0000040 /* DMUU: value of E bit associated address */ 336 #define SFSR_CTXT(x) (((x)>>4)&0x3) 337 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 338 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 339 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 340 #define SFSR_PRIV 0x0000008 /* value of PSTATE.PRIV for faulting access */ 341 #define SFSR_W 0x0000004 /* DMMU: attempted write */ 342 #define SFSR_OW 0x0000002 /* Overwrite; prev fault was still valid */ 343 #define SFSR_FV 0x0000001 /* Fault is valid */ 344 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 345 346 #define SFSR_BITS "\20\31NF\20TM\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV" 347 348 /* ASFR bits */ 349 #define ASFR_ME 0x100000000LL 350 #define ASFR_PRIV 0x080000000LL 351 #define ASFR_ISAP 0x040000000LL 352 #define ASFR_ETP 0x020000000LL 353 #define ASFR_IVUE 0x010000000LL 354 #define ASFR_TO 0x008000000LL 355 #define ASFR_BERR 0x004000000LL 356 #define ASFR_LDP 0x002000000LL 357 #define ASFR_CP 0x001000000LL 358 #define ASFR_WP 0x000800000LL 359 #define ASFR_EDP 0x000400000LL 360 #define ASFR_UE 0x000200000LL 361 #define ASFR_CE 0x000100000LL 362 #define ASFR_ETS 0x0000f0000LL 363 #define ASFT_P_SYND 0x00000ffffLL 364 365 #define AFSR_BITS "\20" \ 366 "\20ME\37PRIV\36ISAP\35ETP\34IVUE\33TO\32BERR\31LDP\30CP\27WP\26EDP" \ 367 "\25UE\24CE" 368 369 /* 370 * Here's the spitfire TSB control register bits. 371 * 372 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 373 */ 374 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 375 #define TSB_SIZE_1K 0x01 376 #define TSB_SIZE_2K 0x02 377 #define TSB_SIZE_4K 0x03 378 #define TSB_SIZE_8K 0x04 379 #define TSB_SIZE_16K 0x05 380 #define TSB_SIZE_32K 0x06 381 #define TSB_SIZE_64K 0x07 382 #define TSB_SPLIT 0x1000 383 #define TSB_BASE 0xffffffffffffe000 384 385 /* TLB Tag Access bits */ 386 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 387 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 388 389 /* 390 * TLB demap registers. TTEs are defined in v9pte.h 391 * 392 * Use the address space to select between IMMU and DMMU. 393 * The address of the register selects which context register 394 * to read the ASI from. 395 * 396 * The data stored in the register is interpreted as the VA to 397 * use. The DEMAP_CTX_<> registers ignore the address and demap the 398 * entire ASI. 399 * 400 */ 401 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 402 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 403 404 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 405 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 406 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 407 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 408 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 409 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 410 411 /* 412 * Interrupt registers. This really gets hairy. 413 */ 414 415 /* IRSR -- Interrupt Receive Status Ragister */ 416 #define ASI_IRSR 0x49 417 #define IRSR 0x00 418 #define IRSR_BUSY 0x020 419 #define IRSR_MID(x) (x&0x1f) 420 421 /* IRDR -- Interrupt Receive Data Registers */ 422 #define ASI_IRDR 0x7f 423 #define IRDR_0H 0x40 424 #define IRDR_0L 0x48 /* unimplemented */ 425 #define IRDR_1H 0x50 426 #define IRDR_1L 0x58 /* unimplemented */ 427 #define IRDR_2H 0x60 428 #define IRDR_2L 0x68 /* unimplemented */ 429 #define IRDR_3H 0x70 /* unimplemented */ 430 #define IRDR_3L 0x78 /* unimplemented */ 431 432 /* SOFTINT ASRs */ 433 #define SET_SOFTINT %asr20 /* Sets these bits */ 434 #define CLEAR_SOFTINT %asr21 /* Clears these bits */ 435 #define SOFTINT %asr22 /* Reads the register */ 436 #define TICK_CMPR %asr23 437 438 #define TICK_INT 0x01 /* level-14 clock tick */ 439 #define SOFTINT1 (0x1<<1) 440 #define SOFTINT2 (0x1<<2) 441 #define SOFTINT3 (0x1<<3) 442 #define SOFTINT4 (0x1<<4) 443 #define SOFTINT5 (0x1<<5) 444 #define SOFTINT6 (0x1<<6) 445 #define SOFTINT7 (0x1<<7) 446 #define SOFTINT8 (0x1<<8) 447 #define SOFTINT9 (0x1<<9) 448 #define SOFTINT10 (0x1<<10) 449 #define SOFTINT11 (0x1<<11) 450 #define SOFTINT12 (0x1<<12) 451 #define SOFTINT13 (0x1<<13) 452 #define SOFTINT14 (0x1<<14) 453 #define SOFTINT15 (0x1<<15) 454 #define STICK_INT (0x1<<16) 455 456 /* Interrupt Dispatch -- usually reserved for cross-calls */ 457 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */ 458 #define IDSR 0x00 459 #define IDSR_NACK 0x02 460 #define IDSR_BUSY 0x01 461 462 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 463 464 /* Interrupt delivery initiation */ 465 #define IDCR(x) ((((u_int64_t)(x)) << 14) | 0x70) 466 467 #define IDDR_0H 0x40 /* Store data to send in these regs */ 468 #define IDDR_0L 0x48 /* unimplemented */ 469 #define IDDR_1H 0x50 470 #define IDDR_1L 0x58 /* unimplemented */ 471 #define IDDR_2H 0x60 472 #define IDDR_2L 0x68 /* unimplemented */ 473 #define IDDR_3H 0x80 /* unimplemented */ 474 #define IDDR_3L 0x88 /* unimplemented */ 475 476 /* 477 * Error registers 478 */ 479 480 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 481 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 482 #define AFAR 0x00 483 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 484 #define AFSR 0x00 485 486 #define ASI_P_EER 0x4b /* Error enable register */ 487 #define P_EER 0x00 488 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 489 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 490 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 491 492 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 493 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 494 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 495 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 496 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 497 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 498 499 500 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 501 502 #ifndef _LOCORE 503 /* 504 * GCC __asm constructs for doing assembly stuff. 505 */ 506 507 /* 508 * ``Routines'' to load and store from/to alternate address space. 509 * The location can be a variable, the asi value (address space indicator) 510 * must be a constant. 511 * 512 * N.B.: You can put as many special functions here as you like, since 513 * they cost no kernel space or time if they are not used. 514 * 515 * These were static inline functions, but gcc screws up the constraints 516 * on the address space identifiers (the "n"umeric value part) because 517 * it inlines too late, so we have to use the funny valued-macro syntax. 518 */ 519 520 /* 521 * Apparently the definition of bypass ASIs is that they all use the 522 * D$ so we need to flush the D$ to make sure we don't get data pollution. 523 */ 524 525 #define sparc_membar(mask) do { \ 526 if (mask) \ 527 __asm volatile("membar %0" : : "n" (mask) : "memory"); \ 528 else \ 529 __asm volatile("" : : : "memory"); \ 530 } while(0) 531 532 #define membar sparc_membar 533 #define Lookaside CMASK_GEN(C_Lookaside) 534 #define MemIssue CMASK_GEN(C_MemIssue) 535 #define Sync CMASK_GEN(C_Sync) 536 #define LoadLoad MMASK_GEN(M_LoadLoad) 537 #define StoreLoad MMASK_GEN(M_StoreLoad) 538 #define LoadStore MMASK_GEN(M_LoadStore) 539 #define StoreStore MMASK_GEN(M_StoreStore) 540 541 #define sparc_wr(name, val, xor) \ 542 do { \ 543 if (__builtin_constant_p(xor)) \ 544 __asm volatile("wr %%g0, %0, %%" #name \ 545 : : "rI" ((val) ^ (xor)) : "%g0"); \ 546 else \ 547 __asm volatile("wr %0, %1, %%" #name \ 548 : : "r" (val), "rI" (xor) : "%g0"); \ 549 } while(0) 550 551 #define sparc_wrpr(name, val, xor) \ 552 do { \ 553 if (__builtin_constant_p(xor)) \ 554 __asm volatile("wrpr %%g0, %0, %%" #name \ 555 : : "rI" ((val) ^ (xor)) : "%g0"); \ 556 else \ 557 __asm volatile("wrpr %0, %1, %%" #name \ 558 : : "r" (val), "rI" (xor) : "%g0"); \ 559 __asm volatile("" : : : "memory"); \ 560 } while(0) 561 562 563 #define sparc_rd(name) sparc_rd_ ## name() 564 #define GEN_RD(name) \ 565 extern __inline u_int64_t sparc_rd_ ## name(void); \ 566 extern __inline u_int64_t \ 567 sparc_rd_ ## name() \ 568 { \ 569 u_int64_t r; \ 570 __asm volatile("rd %%" #name ", %0" : \ 571 "=r" (r) : : "%g0"); \ 572 return (r); \ 573 } 574 575 #define sparc_rdpr(name) sparc_rdpr_ ## name() 576 #define GEN_RDPR(name) \ 577 extern __inline u_int64_t sparc_rdpr_ ## name(void); \ 578 extern __inline u_int64_t \ 579 sparc_rdpr_ ## name() \ 580 { \ 581 u_int64_t r; \ 582 __asm volatile("rdpr %%" #name ", %0" : \ 583 "=r" (r) : : "%g0"); \ 584 return (r); \ 585 } 586 587 GEN_RD(asi); 588 GEN_RD(fprs); 589 GEN_RD(asr22); 590 GEN_RD(sys_tick); 591 GEN_RD(sys_tick_cmpr); 592 GEN_RDPR(tick); 593 GEN_RDPR(tba); 594 GEN_RDPR(pstate); 595 GEN_RDPR(pil); 596 GEN_RDPR(cwp); 597 GEN_RDPR(cansave); 598 GEN_RDPR(canrestore); 599 GEN_RDPR(cleanwin); 600 GEN_RDPR(otherwin); 601 GEN_RDPR(wstate); 602 GEN_RDPR(ver); 603 /* 604 * Before adding GEN_RDPRs for other registers, see Errata 50 (E.g,. in 605 * the US-IIi manual) regarding tstate, pc and npc reads. 606 */ 607 608 /* Generate ld*a/st*a functions for non-constant ASI's. */ 609 #define LDNC_GEN(tp, o) \ 610 extern __inline tp o ## _asi(paddr_t); \ 611 extern __inline tp \ 612 o ## _asi(paddr_t va) \ 613 { \ 614 tp r; \ 615 __asm volatile( \ 616 #o " [%1] %%asi, %0" \ 617 : "=r" (r) \ 618 : "r" ((volatile tp *)va) \ 619 : "%g0"); \ 620 return (r); \ 621 } \ 622 extern __inline tp o ## _nc(paddr_t, int); \ 623 extern __inline tp \ 624 o ## _nc(paddr_t va, int asi) \ 625 { \ 626 sparc_wr(asi, asi, 0); \ 627 return (o ## _asi(va)); \ 628 } 629 630 LDNC_GEN(u_char, lduba); 631 LDNC_GEN(u_short, lduha); 632 LDNC_GEN(u_int, lduwa); 633 LDNC_GEN(u_int64_t, ldxa); 634 635 LDNC_GEN(int, lda); 636 637 #define LDC_GEN(va, asi, op, opa, type) ({ \ 638 type __r ## op ## type; \ 639 if(asi == ASI_PRIMARY || \ 640 (sizeof(type) == 1 && asi == ASI_PRIMARY_LITTLE)) \ 641 __r ## op ## type = *((volatile type *)va); \ 642 else \ 643 __asm volatile(#opa " [%1] " #asi ", %0" \ 644 : "=r" (__r ## op ## type) \ 645 : "r" ((volatile type *)va) \ 646 : "%g0"); \ 647 __r ## op ## type; \ 648 }) 649 650 #ifdef __OPTIMIZE__ 651 #define LD_GENERIC(va, asi, op, type) (__builtin_constant_p(asi) ? \ 652 LDC_GEN((va), asi, op, op ## a, type) : op ## a_nc((va), asi)) 653 #else /* __OPTIMIZE */ 654 #define LD_GENERIC(va, asi, op, type) (op ## a_nc((va), asi)) 655 #endif /* __OPTIMIZE__ */ 656 657 #define lduba(va, asi) LD_GENERIC(va, asi, ldub, u_int8_t) 658 #define lduha(va, asi) LD_GENERIC(va, asi, lduh, u_int16_t) 659 #define lduwa(va, asi) LD_GENERIC(va, asi, lduw, u_int32_t) 660 #define ldxa(va, asi) LD_GENERIC(va, asi, ldx, u_int64_t) 661 662 #define STNC_GEN(tp, o) \ 663 extern __inline void o ## _asi(paddr_t, tp); \ 664 extern __inline void \ 665 o ## _asi(paddr_t va, tp val) \ 666 { \ 667 __asm volatile( \ 668 #o " %0, [%1] %%asi" \ 669 : \ 670 : "r" (val), "r" ((volatile tp *)va) \ 671 : "memory"); \ 672 } \ 673 extern __inline void o ## _nc(paddr_t, int, tp); \ 674 extern __inline void \ 675 o ## _nc(paddr_t va, int asi, tp val) \ 676 { \ 677 sparc_wr(asi, asi, 0); \ 678 o ## _asi(va, val); \ 679 } 680 681 STNC_GEN(u_int8_t, stba); 682 STNC_GEN(u_int16_t, stha); 683 STNC_GEN(u_int32_t, stwa); 684 STNC_GEN(u_int64_t, stxa); 685 686 STNC_GEN(u_int, sta); 687 688 #define STC_GEN(va, asi, val, op, opa, type) ({ \ 689 if(asi == ASI_PRIMARY || \ 690 (sizeof(type) == 1 && asi == ASI_PRIMARY_LITTLE)) \ 691 *((volatile type *)va) = val; \ 692 else \ 693 __asm volatile(#opa " %0, [%1] " #asi \ 694 : : "r" (val), "r" ((volatile type *)va) \ 695 : "memory"); \ 696 }) 697 698 #ifdef __OPTIMIZE__ 699 #define ST_GENERIC(va, asi, val, op, type) (__builtin_constant_p(asi) ? \ 700 STC_GEN((va), (asi), (val), op, op ## a, type) : \ 701 op ## a_nc((va), asi, (val))) 702 #else /* __OPTIMIZE__ */ 703 #define ST_GENERIC(va, asi, val, op, type) (op ## a_nc((va), asi, (val))) 704 #endif /* __OPTIMIZE__ */ 705 706 #define stba(va, asi, val) ST_GENERIC(va, asi, val, stb, u_int8_t) 707 #define stha(va, asi, val) ST_GENERIC(va, asi, val, sth, u_int16_t) 708 #define stwa(va, asi, val) ST_GENERIC(va, asi, val, stw, u_int32_t) 709 #define stxa(va, asi, val) ST_GENERIC(va, asi, val, stx, u_int64_t) 710 711 712 extern __inline void asi_set(int); 713 extern __inline 714 void asi_set(int asi) 715 { 716 sparc_wr(asi, asi, 0); 717 } 718 719 extern __inline u_int8_t asi_get(void); 720 extern __inline 721 u_int8_t asi_get(void) 722 { 723 return sparc_rd(asi); 724 } 725 726 /* flush address from instruction cache */ 727 extern __inline void flush(void *); 728 extern __inline 729 void flush(void *p) 730 { 731 __asm volatile("flush %0" 732 : : "r" (p) 733 : "memory"); 734 } 735 736 /* Read 64-bit %tick and %sys_tick registers. */ 737 #define tick() (sparc_rdpr(tick) & TICK_TICKS) 738 #define sys_tick() (sparc_rd(sys_tick) & TICK_TICKS) 739 extern u_int64_t stick(void); 740 741 extern void tick_enable(void); 742 743 extern void tickcmpr_set(u_int64_t); 744 extern void sys_tickcmpr_set(u_int64_t); 745 extern void stickcmpr_set(u_int64_t); 746 747 #endif /* _LOCORE */ 748 #endif /* _SPARC64_CTLREG_ */ 749