1 /* $OpenBSD: instr.h,v 1.7 2003/07/13 07:00:48 jason Exp $ */ 2 /* $NetBSD: instr.h,v 1.3 2000/01/10 03:53:20 eeh Exp $ */ 3 4 /* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)instr.h 8.1 (Berkeley) 6/11/93 42 */ 43 44 /* see also Appendix F of the SPARC version 8 document */ 45 enum IOP { IOP_OP2, IOP_CALL, IOP_reg, IOP_mem }; 46 enum IOP2 { IOP2_UNIMP, IOP2_BPcc, IOP2_Bicc, IOP2_BPr, 47 IOP2_SETHI, IOP2_FBPfcc, IOP2_FBfcc, IOP2_CBccc }; 48 enum IOP3_reg { 49 IOP3_ADD, IOP3_AND, IOP3_OR, IOP3_XOR, 50 IOP3_SUB, IOP3_ANDN, IOP3_ORN, IOP3_XNOR, 51 IOP3_ADDX, IOP3_MULX, IOP3_UMUL, IOP3_SMUL, 52 IOP3_SUBX, IOP3_UDIVX, IOP3_UDIV, IOP3_SDIV, 53 IOP3_ADDcc, IOP3_ANDcc, IOP3_ORcc, IOP3_XORcc, 54 IOP3_SUBcc, IOP3_ANDNcc, IOP3_ORNcc, IOP3_XNORcc, 55 IOP3_ADDXcc, IOP3_rerr19, IOP3_UMULcc, IOP3_SMULcc, 56 IOP3_SUBXcc, IOP3_rerr1d, IOP3_UDIVcc, IOP3_SDIVcc, 57 IOP3_TADDcc, IOP3_TSUBcc, IOP3_TADDccTV, IOP3_TSUBccTV, 58 IOP3_MULScc, IOP3_SLL, IOP3_SRL, IOP3_SRA, 59 IOP3_RDASR_RDY_STBAR, IOP3_RDPSR, IOP3_RDWIM, IOP3_RDTGBR, 60 IOP3_MOVcc, IOP3_SDIVX, IOP3_POPC, IOP3_MOVr, 61 IOP3_WRASR_WRY, IOP3_WRPSR, IOP3_WRWIM, IOP3_WRTBR, 62 IOP3_FPop1, IOP3_FPop2, IOP3_CPop1, IOP3_CPop2, 63 IOP3_JMPL, IOP3_RETT, IOP3_Ticc, IOP3_FLUSH, 64 IOP3_SAVE, IOP3_RESTORE, IOP3_DONE_RETRY, IOP3_rerr3f 65 }; 66 enum IOP3_mem { 67 IOP3_LD, IOP3_LDUB, IOP3_LDUH, IOP3_LDD, 68 IOP3_ST, IOP3_STB, IOP3_STH, IOP3_STD, 69 IOP3_LDSW, IOP3_LDSB, IOP3_LDSH, IOP3_LDX, 70 IOP3_merr0c, IOP3_LDSTUB, IOP3_STX, IOP3_SWAP, 71 IOP3_LDA, IOP3_LDUBA, IOP3_LDUHA, IOP3_LDDA, 72 IOP3_STA, IOP3_STBA, IOP3_STHA, IOP3_STDA, 73 IOP3_LDSWA, IOP3_LDSBA, IOP3_LDSHA, IOP3_LDXA, 74 IOP3_merr1c, IOP3_LDSTUBA, IOP3_STXA, IOP3_SWAPA, 75 IOP3_LDF, IOP3_LDFSR, IOP3_LDQF, IOP3_LDDF, 76 IOP3_STF, IOP3_STFSR, IOP3_STQF, IOP3_STDF, 77 IOP3_merr28, IOP3_merr29, IOP3_merr2a, IOP3_merr2b, 78 IOP3_merr2c, IOP3_PREFETCH, IOP3_merr2e, IOP3_merr2f, 79 IOP3_LFC, IOP3_LDCSR, IOP3_LDQFA, IOP3_LDDC, 80 IOP3_STC, IOP3_STCSR, IOP3_STQFA, IOP3_STDC, 81 IOP3_merr38, IOP3_merr39, IOP3_merr3a, IOP3_merr3b, 82 IOP3_CASA, IOP3_PREFETCHA, IOP3_CASXA, IOP3_merr3f 83 }; 84 85 /* 86 * Integer condition codes. 87 */ 88 #define Icc_N 0x0 /* never */ 89 #define Icc_E 0x1 /* equal (equiv. zero) */ 90 #define Icc_LE 0x2 /* less or equal */ 91 #define Icc_L 0x3 /* less */ 92 #define Icc_LEU 0x4 /* less or equal unsigned */ 93 #define Icc_CS 0x5 /* carry set (equiv. less unsigned) */ 94 #define Icc_NEG 0x6 /* negative */ 95 #define Icc_VS 0x7 /* overflow set */ 96 #define Icc_A 0x8 /* always */ 97 #define Icc_NE 0x9 /* not equal (equiv. not zero) */ 98 #define Icc_G 0xa /* greater */ 99 #define Icc_GE 0xb /* greater or equal */ 100 #define Icc_GU 0xc /* greater unsigned */ 101 #define Icc_CC 0xd /* carry clear (equiv. gtr or eq unsigned) */ 102 #define Icc_POS 0xe /* positive */ 103 #define Icc_VC 0xf /* overflow clear */ 104 105 /* 106 * Integer registers. 107 */ 108 #define I_G0 0 109 #define I_G1 1 110 #define I_G2 2 111 #define I_G3 3 112 #define I_G4 4 113 #define I_G5 5 114 #define I_G6 6 115 #define I_G7 7 116 #define I_O0 8 117 #define I_O1 9 118 #define I_O2 10 119 #define I_O3 11 120 #define I_O4 12 121 #define I_O5 13 122 #define I_O6 14 123 #define I_O7 15 124 #define I_L0 16 125 #define I_L1 17 126 #define I_L2 18 127 #define I_L3 19 128 #define I_L4 20 129 #define I_L5 21 130 #define I_L6 22 131 #define I_L7 23 132 #define I_I0 24 133 #define I_I1 25 134 #define I_I2 26 135 #define I_I3 27 136 #define I_I4 28 137 #define I_I5 29 138 #define I_I6 30 139 #define I_I7 31 140 141 /* 142 * An instruction. 143 */ 144 union instr { 145 int i_int; /* as a whole */ 146 147 /* 148 * The first level of decoding is to use the top 2 bits. 149 * This gives us one of three `formats', which usually give 150 * a second level of decoding. 151 */ 152 struct { 153 u_int i_op:2; /* first-level decode */ 154 u_int :30; 155 } i_any; 156 157 /* 158 * Format 1 instructions: CALL (undifferentiated). 159 */ 160 struct { 161 u_int :2; /* 01 */ 162 int i_disp:30; /* displacement */ 163 } i_call; 164 165 /* 166 * Format 2 instructions (SETHI, UNIMP, and branches, plus illegal 167 * unused codes). 168 */ 169 struct { 170 u_int :2; /* 00 */ 171 u_int :5; 172 u_int i_op2:3; /* second-level decode */ 173 u_int :22; 174 } i_op2; 175 176 /* UNIMP, SETHI */ 177 struct { 178 u_int :2; /* 00 */ 179 u_int i_rd:5; /* destination register */ 180 u_int i_op2:3; /* opcode: UNIMP or SETHI */ 181 u_int i_imm:22; /* immediate value */ 182 } i_imm22; 183 184 /* branches: Bicc, FBfcc, CBccc */ 185 struct { 186 u_int :2; /* 00 */ 187 u_int i_annul:1; /* annul bit */ 188 u_int i_cond:4; /* condition codes */ 189 u_int i_op2:3; /* opcode: {Bi,FBf,CBc}cc */ 190 int i_disp:22; /* branch displacement */ 191 } i_branch; 192 193 /* more branches: BPcc, FBPfcc */ 194 struct { 195 u_int :2; /* 00 */ 196 u_int i_annul:1; /* annul bit */ 197 u_int i_cond:4; /* condition codes */ 198 u_int i_op2:3; /* opcode: {BP,FBPf}cc */ 199 u_int i_cc:2; /* condition code selector */ 200 u_int i_pred:1; /* branch prediction bit */ 201 int i_disp:19; /* branch displacement */ 202 } i_branch_p; 203 204 /* one last branch: BPr */ 205 struct { 206 u_int :2; /* 00 */ 207 u_int i_annul:1; /* annul bit */ 208 u_int :1; /* 0 */ 209 u_int i_rcond:4; /* register condition */ 210 u_int :3; /* 011 */ 211 int i_disphi:2; /* branch displacement, hi bits */ 212 u_int i_pred:1; /* branch prediction bit */ 213 u_int i_rs1:1; /* source register 1 */ 214 u_int i_displo:16; /* branch displacement, lo bits */ 215 } i_branch_pr; 216 217 218 /* 219 * Format 3 instructions (memory reference; arithmetic, logical, 220 * shift, and other miscellaneous operations). The second-level 221 * decode almost always makes use of an `rd' and `rs1', however 222 * (see also IOP3_reg and IOP3_mem). 223 * 224 * Beyond that, the low 14 bits may be broken up in one of three 225 * different ways, if at all: 226 * 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem] 227 * 1 bit of imm=1 + 13 bits of signed immediate [reg & mem] 228 * 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only] 229 */ 230 struct { 231 u_int :2; /* 10 or 11 */ 232 u_int i_rd:5; /* destination register */ 233 u_int i_op3:6; /* second-level decode */ 234 u_int i_rs1:5; /* source register 1 */ 235 u_int i_low14:14; /* varies */ 236 } i_op3; 237 238 /* 239 * Memory forms. These set i_op=3 and use simm13 or asi layout. 240 * Memory references without an ASI should use 0, but the actual 241 * ASI field is simply ignored. 242 */ 243 struct { 244 u_int :2; /* 11 only */ 245 u_int i_rd:5; /* destination register */ 246 u_int i_op3:6; /* second-level decode (see IOP3_mem) */ 247 u_int i_rs1:5; /* source register 1 */ 248 u_int i_i:1; /* immediate vs asi */ 249 u_int i_low13:13; /* depend on i bit */ 250 } i_loadstore; 251 252 /* 253 * Memory and register forms. 254 * These come in quite a variety and we do not 255 * attempt to break them down much. 256 */ 257 struct { 258 u_int :2; /* 10 or 11 */ 259 u_int i_rd:5; /* destination register */ 260 u_int i_op3:6; /* second-level decode */ 261 u_int i_rs1:5; /* source register 1 */ 262 u_int i_i:1; /* immediate bit (1) */ 263 int i_simm13:13; /* signed immediate */ 264 } i_simm13; 265 struct { 266 u_int :2; /* 10 or 11 */ 267 u_int i_rd:5; /* destination register */ 268 u_int i_op3:6; /* second-level decode */ 269 u_int i_rs1:5; /* source register 1 */ 270 u_int i_i:1; /* immediate vs asi */ 271 u_int i_asi:8; /* asi */ 272 u_int i_rs2:5; /* source register 2 */ 273 } i_asi; 274 struct { 275 u_int :2; /* 10 only (register, no memory) */ 276 u_int i_rd:5; /* destination register */ 277 u_int i_op3:6; /* second-level decode (see IOP3_reg) */ 278 u_int i_rs1:5; /* source register 1 */ 279 u_int i_opf:9; /* coprocessor 3rd-level decode */ 280 u_int i_rs2:5; /* source register 2 */ 281 } i_opf; 282 283 /* 284 * Format 4 instructions (movcc, fmovr, fmovcc, and tcc). The 285 * second-level decode almost always makes use of an `rd' and either 286 * `rs1' or `cond'. 287 * 288 * Beyond that, the low 14 bits may be broken up in one of three 289 * different ways, if at all: 290 * 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem] 291 * 1 bit of imm=1 + 13 bits of signed immediate [reg & mem] 292 * 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only] */ 293 struct { 294 u_int :2; /* 10 */ 295 u_int i_rd:5; /* destination register */ 296 u_int i_op3:6; /* second-level decode */ 297 u_int i_rs1:5; /* source register 1 */ 298 u_int i_low14:14; /* varies */ 299 } i_op4; 300 301 /* 302 * Move fp register on condition codes. 303 */ 304 struct { 305 u_int :2; /* 10 */ 306 u_int i_rd:5; /* destination register */ 307 u_int i_op3:6; /* second-level decode */ 308 u_int :1; 309 u_int i_cond:4; /* condition */ 310 u_int i_opf_cc:3; /* condition code register */ 311 u_int i_opf_low:6; /* third level decode */ 312 u_int i_rs2:5; /* source register */ 313 } i_fmovcc; 314 315 /* 316 * Move fp register on integer register. 317 */ 318 struct { 319 u_int :2; /* 10 */ 320 u_int i_rd:5; /* destination register */ 321 u_int i_op3:6; /* second-level decode */ 322 u_int i_rs1:5; /* source register 1 */ 323 u_int :1; 324 u_int i_rcond:3; /* register condition */ 325 u_int i_opf_low:6; 326 u_int i_rs2:5; /* source register 2 */ 327 } i_fmovr; 328 329 }; 330 331 /* 332 * Internal macros for building instructions. These correspond 1-to-1 to 333 * the names above. Note that x << y | z == (x << y) | z. 334 */ 335 #define _I_ANY(op, b) ((op) << 30 | (b)) 336 337 #define _I_OP2(high, op2, low) \ 338 _I_ANY(IOP_OP2, (high) << 25 | (op2) << 22 | (low)) 339 #define _I_IMM22(rd, op2, imm) \ 340 _I_ANY(IOP_OP2, (rd) << 25 | (op2) << 22 | (imm)) 341 #define _I_BRANCH(a, c, op2, disp) \ 342 _I_ANY(IOP_OP2, (a) << 29 | (c) << 25 | (op2) << 22 | (disp)) 343 #define _I_FBFCC(a, cond, disp) \ 344 _I_BRANCH(a, cond, IOP2_FBfcc, disp) 345 #define _I_CBCCC(a, cond, disp) \ 346 _I_BRANCH(a, cond, IOP2_CBccc, disp) 347 348 #define _I_SIMM(simm) (1 << 13 | ((simm) & 0x1fff)) 349 350 #define _I_OP3_GEN(form, rd, op3, rs1, low14) \ 351 _I_ANY(form, (rd) << 25 | (op3) << 19 | (rs1) << 14 | (low14)) 352 #define _I_OP3_LS_RAR(rd, op3, rs1, asi, rs2) \ 353 _I_OP3_GEN(IOP_mem, rd, op3, rs1, (asi) << 5 | (rs2)) 354 #define _I_OP3_LS_RI(rd, op3, rs1, simm13) \ 355 _I_OP3_GEN(IOP_mem, rd, op3, rs1, _I_SIMM(simm13)) 356 #define _I_OP3_LS_RR(rd, op3, rs1, rs2) \ 357 _I_OP3_GEN(IOP_mem, rd, op3, rs1, rs2) 358 #define _I_OP3_R_RAR(rd, op3, rs1, asi, rs2) \ 359 _I_OP3_GEN(IOP_reg, rd, op3, rs1, (asi) << 5 | (rs2)) 360 #define _I_OP3_R_RI(rd, op3, rs1, simm13) \ 361 _I_OP3_GEN(IOP_reg, rd, op3, rs1, _I_SIMM(simm13)) 362 #define _I_OP3_R_RR(rd, op3, rs1, rs2) \ 363 _I_OP3_GEN(IOP_reg, rd, op3, rs1, rs2) 364 365 #define I_CALL(d) _I_ANY(IOP_CALL, d) 366 #define I_UNIMP(v) _I_IMM22(0, IOP2_UNIMP, v) 367 #define I_BN(a, d) _I_BRANCH(a, Icc_N, IOP2_Bicc, d) 368 #define I_BE(a, d) _I_BRANCH(a, Icc_E, IOP2_Bicc, d) 369 #define I_BZ(a, d) _I_BRANCH(a, Icc_E, IOP2_Bicc, d) 370 #define I_BLE(a, d) _I_BRANCH(a, Icc_LE, IOP2_Bicc, d) 371 #define I_BL(a, d) _I_BRANCH(a, Icc_L, IOP2_Bicc, d) 372 #define I_BLEU(a, d) _I_BRANCH(a, Icc_LEU, IOP2_Bicc, d) 373 #define I_BCS(a, d) _I_BRANCH(a, Icc_CS, IOP2_Bicc, d) 374 #define I_BLU(a, d) _I_BRANCH(a, Icc_CS, IOP2_Bicc, d) 375 #define I_BNEG(a, d) _I_BRANCH(a, Icc_NEG, IOP2_Bicc, d) 376 #define I_BVS(a, d) _I_BRANCH(a, Icc_VS, IOP2_Bicc, d) 377 #define I_BA(a, d) _I_BRANCH(a, Icc_A, IOP2_Bicc, d) 378 #define I_B(a, d) _I_BRANCH(a, Icc_A, IOP2_Bicc, d) 379 #define I_BNE(a, d) _I_BRANCH(a, Icc_NE, IOP2_Bicc, d) 380 #define I_BNZ(a, d) _I_BRANCH(a, Icc_NE, IOP2_Bicc, d) 381 #define I_BG(a, d) _I_BRANCH(a, Icc_G, IOP2_Bicc, d) 382 #define I_BGE(a, d) _I_BRANCH(a, Icc_GE, IOP2_Bicc, d) 383 #define I_BGU(a, d) _I_BRANCH(a, Icc_GU, IOP2_Bicc, d) 384 #define I_BCC(a, d) _I_BRANCH(a, Icc_CC, IOP2_Bicc, d) 385 #define I_BGEU(a, d) _I_BRANCH(a, Icc_CC, IOP2_Bicc, d) 386 #define I_BPOS(a, d) _I_BRANCH(a, Icc_POS, IOP2_Bicc, d) 387 #define I_BVC(a, d) _I_BRANCH(a, Icc_VC, IOP2_Bicc, d) 388 #define I_SETHI(r, v) _I_IMM22(r, 4, v) 389 390 #define I_ORri(rd, rs1, imm) _I_OP3_R_RI(rd, IOP3_OR, rs1, imm) 391 #define I_ORrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_OR, rs1, rs2) 392 393 #define I_MOVi(rd, imm) _I_OP3_R_RI(rd, IOP3_OR, I_G0, imm) 394 #define I_MOVr(rd, rs) _I_OP3_R_RR(rd, IOP3_OR, I_G0, rs) 395 396 #define I_RDPSR(rd) _I_OP3_R_RR(rd, IOP3_RDPSR, 0, 0) 397 398 #define I_JMPLri(rd, rs1, imm) _I_OP3_R_RI(rd, IOP3_JMPL, rs1, imm) 399 #define I_JMPLrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_JMPL, rs1, rs2) 400 401 /* 402 * FPop values. 403 */ 404 405 /* These are in FPop1 space */ 406 #define FMOVS 0x001 407 #define FMOVD 0x002 408 #define FMOVQ 0x003 409 #define FNEGS 0x005 410 #define FNEGD 0x006 411 #define FNEGQ 0x007 412 #define FABSS 0x009 413 #define FABSD 0x00a 414 #define FABSQ 0x00b 415 #define FSQRTS 0x029 416 #define FSQRTD 0x02a 417 #define FSQRTQ 0x02b 418 #define FADDS 0x041 419 #define FADDD 0x042 420 #define FADDQ 0x043 421 #define FSUBS 0x045 422 #define FSUBD 0x046 423 #define FSUBQ 0x047 424 #define FMULS 0x049 425 #define FMULD 0x04a 426 #define FMULQ 0x04b 427 #define FDIVS 0x04d 428 #define FDIVD 0x04e 429 #define FDIVQ 0x04f 430 #define FSMULD 0x069 431 #define FDMULQ 0x06e 432 #define FSTOX 0x081 433 #define FDTOX 0x082 434 #define FQTOX 0x083 435 #define FXTOS 0x084 436 #define FXTOD 0x088 437 #define FXTOQ 0x08c 438 #define FITOS 0x0c4 439 #define FDTOS 0x0c6 440 #define FQTOS 0x0c7 441 #define FITOD 0x0c8 442 #define FSTOD 0x0c9 443 #define FQTOD 0x0cb 444 #define FITOQ 0x0cc 445 #define FSTOQ 0x0cd 446 #define FDTOQ 0x0ce 447 #define FSTOI 0x0d1 448 #define FDTOI 0x0d2 449 #define FQTOI 0x0d3 450 451 /* These are in FPop2 space */ 452 #define FMVFC0S 0x001 453 #define FMVFC0D 0x002 454 #define FMVFC0Q 0x003 455 #define FMOVZS 0x025 456 #define FMOVZD 0x026 457 #define FMOVZQ 0x027 458 #define FMVFC1S 0x041 459 #define FMVFC1D 0x042 460 #define FMVFC1Q 0x043 461 #define FMOVLEZS 0x045 462 #define FMOVLEZD 0x046 463 #define FMOVLEZQ 0x047 464 #define FCMPS 0x051 465 #define FCMPD 0x052 466 #define FCMPQ 0x053 467 #define FCMPES 0x055 468 #define FCMPED 0x056 469 #define FCMPEQ 0x057 470 #define FMOVLZS 0x065 471 #define FMOVLZD 0x066 472 #define FMOVLZQ 0x067 473 #define FMVFC2S 0x081 474 #define FMVFC2D 0x082 475 #define FMVFC2Q 0x083 476 #define FMOVNZS 0x0a5 477 #define FMOVNZD 0x0a6 478 #define FMOVNZQ 0x0a7 479 #define FMVFC3S 0x0c1 480 #define FMVFC3D 0x0c2 481 #define FMVFC3Q 0x0c3 482 #define FMOVGZS 0x0c5 483 #define FMOVGZD 0x0c6 484 #define FMOVGZQ 0x0c7 485 #define FMOVGEZS 0x0e5 486 #define FMOVGEZD 0x0e6 487 #define FMOVGEZQ 0x0e7 488 #define FMVICS 0x101 489 #define FMVICD 0x102 490 #define FMVICQ 0x103 491 #define FMVXCS 0x181 492 #define FMVXCD 0x182 493 #define FMVXCQ 0x183 494 495 /* 496 * FPU data types. 497 */ 498 #define FTYPE_LNG -1 /* data = 64-bit signed long integer */ 499 #define FTYPE_INT 0 /* data = 32-bit signed integer */ 500 #define FTYPE_SNG 1 /* data = 32-bit float */ 501 #define FTYPE_DBL 2 /* data = 64-bit double */ 502 #define FTYPE_EXT 3 /* data = 128-bit extended (quad-prec) */ 503