1 /* $OpenBSD: psl.h,v 1.27 2010/05/31 21:39:56 deraadt Exp $ */ 2 /* $NetBSD: psl.h,v 1.20 2001/04/13 23:30:05 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)psl.h 8.1 (Berkeley) 6/11/93 42 */ 43 44 #ifndef _SPARC64_PSL_ 45 #define _SPARC64_PSL_ 46 47 /* Interesting spl()s */ 48 #define PIL_SCSI 3 49 #define PIL_FDSOFT 4 50 #define PIL_AUSOFT 4 51 #define PIL_BIO 5 52 #define PIL_VIDEO 5 53 #define PIL_TTY 6 54 #define PIL_NET 6 55 #define PIL_VM 7 56 #define PIL_AUD 8 57 #define PIL_CLOCK 10 58 #define PIL_FD 11 59 #define PIL_SER 12 60 #define PIL_STATCLOCK 14 61 #define PIL_HIGH 15 62 #define PIL_SCHED PIL_STATCLOCK 63 #define PIL_LOCK PIL_HIGH 64 65 /* 66 * SPARC V9 CCR register 67 */ 68 69 #define ICC_C 0x01L 70 #define ICC_V 0x02L 71 #define ICC_Z 0x04L 72 #define ICC_N 0x08L 73 #define XCC_SHIFT 4 74 #define XCC_C (ICC_C<<XCC_SHIFT) 75 #define XCC_V (ICC_V<<XCC_SHIFT) 76 #define XCC_Z (ICC_Z<<XCC_SHIFT) 77 #define XCC_N (ICC_N<<XCC_SHIFT) 78 79 80 /* 81 * SPARC V9 PSTATE register (what replaces the PSR in V9) 82 * 83 * Here's the layout: 84 * 85 * 11 10 9 8 7 6 5 4 3 2 1 0 86 * +------------------------------------------------------------+ 87 * | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG | 88 * +------------------------------------------------------------+ 89 */ 90 91 #define PSTATE_IG 0x800 /* enable spitfire interrupt globals */ 92 #define PSTATE_MG 0x400 /* enable spitfire MMU globals */ 93 #define PSTATE_CLE 0x200 /* current little endian */ 94 #define PSTATE_TLE 0x100 /* traps little endian */ 95 #define PSTATE_MM 0x0c0 /* memory model */ 96 #define PSTATE_MM_TSO 0x000 /* total store order */ 97 #define PSTATE_MM_PSO 0x040 /* partial store order */ 98 #define PSTATE_MM_RMO 0x080 /* Relaxed memory order */ 99 #define PSTATE_RED 0x020 /* RED state */ 100 #define PSTATE_PEF 0x010 /* enable floating point */ 101 #define PSTATE_AM 0x008 /* 32-bit address masking */ 102 #define PSTATE_PRIV 0x004 /* privileged mode */ 103 #define PSTATE_IE 0x002 /* interrupt enable */ 104 #define PSTATE_AG 0x001 /* enable alternate globals */ 105 106 #define PSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 107 108 109 /* 110 * 32-bit code requires TSO or at best PSO since that's what's supported on 111 * SPARC V8 and earlier machines. 112 * 113 * 64-bit code sets the memory model in the ELF header. 114 * 115 * We're running kernel code in TSO for the moment so we don't need to worry 116 * about possible memory barrier bugs. 117 */ 118 119 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 120 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_PRIV|PSTATE_AG) 121 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_PRIV) 122 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 123 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 124 #define PSTATE_USER (PSTATE_MM_RMO|PSTATE_IE) 125 126 127 /* 128 * SPARC V9 TSTATE register 129 * 130 * 39 32 31 24 23 18 17 8 7 5 4 0 131 * +-----+-----+-----+--------+---+-----+ 132 * | CCR | ASI | - | PSTATE | - | CWP | 133 * +-----+-----+-----+--------+---+-----+ 134 */ 135 136 #define TSTATE_CWP 0x01f 137 #define TSTATE_PSTATE 0x6ff00 138 #define TSTATE_PSTATE_SHIFT 8 139 #define TSTATE_ASI 0xff000000LL 140 #define TSTATE_ASI_SHIFT 24 141 #define TSTATE_CCR 0xff00000000LL 142 #define TSTATE_CCR_SHIFT 32 143 144 /* Leftover SPARC V8 PSTATE stuff */ 145 #define PSR_ICC 0x00f00000 146 #define PSRCC_TO_TSTATE(x) (((int64_t)(x)&PSR_ICC)<<(TSTATE_CCR_SHIFT-19)) 147 #define TSTATECCR_TO_PSR(x) (((x)&TSTATE_CCR)>>(TSTATE_CCR_SHIFT-19)) 148 149 /* 150 * These are here to simplify life. 151 */ 152 #define TSTATE_IG (PSTATE_IG<<TSTATE_PSTATE_SHIFT) 153 #define TSTATE_MG (PSTATE_MG<<TSTATE_PSTATE_SHIFT) 154 #define TSTATE_CLE (PSTATE_CLE<<TSTATE_PSTATE_SHIFT) 155 #define TSTATE_TLE (PSTATE_TLE<<TSTATE_PSTATE_SHIFT) 156 #define TSTATE_MM (PSTATE_MM<<TSTATE_PSTATE_SHIFT) 157 #define TSTATE_MM_TSO (PSTATE_MM_TSO<<TSTATE_PSTATE_SHIFT) 158 #define TSTATE_MM_PSO (PSTATE_MM_PSO<<TSTATE_PSTATE_SHIFT) 159 #define TSTATE_MM_RMO (PSTATE_MM_RMO<<TSTATE_PSTATE_SHIFT) 160 #define TSTATE_RED (PSTATE_RED<<TSTATE_PSTATE_SHIFT) 161 #define TSTATE_PEF (PSTATE_PEF<<TSTATE_PSTATE_SHIFT) 162 #define TSTATE_AM (PSTATE_AM<<TSTATE_PSTATE_SHIFT) 163 #define TSTATE_PRIV (PSTATE_PRIV<<TSTATE_PSTATE_SHIFT) 164 #define TSTATE_IE (PSTATE_IE<<TSTATE_PSTATE_SHIFT) 165 #define TSTATE_AG (PSTATE_AG<<TSTATE_PSTATE_SHIFT) 166 167 #define TSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 168 169 #define TSTATE_KERN ((PSTATE_KERN)<<TSTATE_PSTATE_SHIFT) 170 #define TSTATE_USER ((PSTATE_USER)<<TSTATE_PSTATE_SHIFT) 171 /* 172 * SPARC V9 VER version register. 173 * 174 * 63 48 47 32 31 24 23 16 15 8 7 5 4 0 175 * +-------+------+------+-----+-------+---+--------+ 176 * | manuf | impl | mask | - | maxtl | - | maxwin | 177 * +-------+------+------+-----+-------+---+--------+ 178 * 179 */ 180 181 #define VER_MANUF 0xffff000000000000ULL 182 #define VER_MANUF_SHIFT 48 183 #define VER_IMPL 0x0000ffff00000000ULL 184 #define VER_IMPL_SHIFT 32 185 #define VER_MASK 0x00000000ff000000ULL 186 #define VER_MASK_SHIFT 24 187 #define VER_MAXTL 0x000000000000ff00ULL 188 #define VER_MAXTL_SHIFT 8 189 #define VER_MAXWIN 0x000000000000001fULL 190 191 #define IMPL_SPARC64 0x01 /* SPARC64 */ 192 #define IMPL_SPARC64_II 0x02 /* SPARC64-II */ 193 #define IMPL_SPARC64_III 0x03 /* SPARC64-III */ 194 #define IMPL_SPARC64_IV 0x04 /* SPARC64-IV */ 195 #define IMPL_ZEUS 0x05 /* SPARC64-V */ 196 #define IMPL_OLYMPUS_C 0x06 /* SPARC64-VI */ 197 #define IMPL_JUPITER 0x07 /* SPARC64-VII */ 198 #define IMPL_SPITFIRE 0x10 /* UltraSPARC */ 199 #define IMPL_BLACKBIRD 0x11 /* UltraSPARC-II */ 200 #define IMPL_SABRE 0x12 /* UltraSPARC-IIi */ 201 #define IMPL_HUMMINGBIRD 0x13 /* UltraSPARC-IIe */ 202 #define IMPL_CHEETAH 0x14 /* UltraSPARC-III */ 203 #define IMPL_CHEETAH_PLUS 0x15 /* UltraSPARC-III+ */ 204 #define IMPL_JALAPENO 0x16 /* UltraSPARC-IIIi */ 205 #define IMPL_JAGUAR 0x18 /* UltraSPARC-IV */ 206 #define IMPL_PANTHER 0x19 /* UltraSPARC-IV+ */ 207 #define IMPL_SERRANO 0x22 /* UltraSPARC-IIIi+ */ 208 209 /* 210 * Here are a few things to help us transition between user and kernel mode: 211 */ 212 213 /* Memory models */ 214 #define KERN_MM PSTATE_MM_TSO 215 #define USER_MM PSTATE_MM_RMO 216 217 /* 218 * Register window handlers. These point to generic routines that check the 219 * stack pointer and then vector to the real handler. We could optimize this 220 * if we could guarantee only 32-bit or 64-bit stacks. 221 */ 222 #define WSTATE_KERN 027 223 #define WSTATE_USER 022 224 225 #define CWP 0x01f 226 227 /* 64-byte alignment -- this seems the best place to put this. */ 228 #define BLOCK_SIZE 64 229 #define BLOCK_ALIGN 0x3f 230 231 #if defined(_KERNEL) && !defined(_LOCORE) 232 233 extern u_int64_t ver; /* Copy of v9 version register. We need to read this only once, in locore.s. */ 234 #ifndef SPLDEBUG 235 extern __inline void splx(int); 236 #endif 237 238 #ifdef DIAGNOSTIC 239 /* 240 * Although this function is implemented in MI code, it must be in this MD 241 * header because we don't want this header to include MI includes. 242 */ 243 void splassert_fail(int, int, const char *); 244 extern int splassert_ctl; 245 void splassert_check(int, const char *); 246 #define splassert(__wantipl) do { \ 247 if (splassert_ctl > 0) { \ 248 splassert_check(__wantipl, __func__); \ 249 } \ 250 } while (0) 251 #define splsoftassert(wantipl) splassert(wantipl) 252 #else 253 #define splassert(wantipl) do { /* nada */ } while (0) 254 #define splsoftassert(wantipl) do { /* nada */ } while (0) 255 #endif 256 257 /* 258 * GCC pseudo-functions for manipulating privileged registers 259 */ 260 extern __inline u_int64_t getpstate(void); 261 extern __inline 262 u_int64_t getpstate() 263 { 264 return (sparc_rdpr(pstate)); 265 } 266 267 extern __inline void setpstate(u_int64_t); 268 extern __inline void setpstate(u_int64_t newpstate) 269 { 270 sparc_wrpr(pstate, newpstate, 0); 271 } 272 273 extern __inline int getcwp(void); 274 extern __inline 275 int getcwp() 276 { 277 return (sparc_rdpr(cwp)); 278 } 279 280 extern __inline void setcwp(u_int64_t); 281 extern __inline void 282 setcwp(u_int64_t newcwp) 283 { 284 sparc_wrpr(cwp, newcwp, 0); 285 } 286 287 extern __inline u_int64_t getver(void); 288 extern __inline 289 u_int64_t getver() 290 { 291 return (sparc_rdpr(ver)); 292 } 293 294 extern __inline u_int64_t intr_disable(void); 295 extern __inline u_int64_t 296 intr_disable() 297 { 298 u_int64_t s; 299 300 s = sparc_rdpr(pstate); 301 sparc_wrpr(pstate, s & ~PSTATE_IE, 0); 302 return (s); 303 } 304 305 extern __inline void intr_restore(u_int64_t); 306 extern __inline void 307 intr_restore(u_int64_t s) 308 { 309 sparc_wrpr(pstate, s, 0); 310 } 311 312 extern __inline void stxa_sync(u_int64_t, u_int64_t, u_int64_t); 313 extern __inline void 314 stxa_sync(u_int64_t va, u_int64_t asi, u_int64_t val) 315 { 316 u_int64_t s = intr_disable(); 317 stxa_nc(va, asi, val); 318 membar(Sync); 319 intr_restore(s); 320 } 321 322 /* 323 * GCC pseudo-functions for manipulating PIL 324 */ 325 326 #ifdef SPLDEBUG 327 void prom_printf(const char *fmt, ...); 328 extern int printspl; 329 #define SPLPRINT(x) if(printspl) { int i=10000000; prom_printf x ; while(i--); } 330 #define SPL(name, newpil) \ 331 extern __inline int name##X(const char *, int); \ 332 extern __inline int name##X(const char *file, int line) \ 333 { \ 334 u_int64_t oldpil = sparc_rdpr(pil); \ 335 SPLPRINT(("{%s:%d %d=>%d}", file, line, oldpil, newpil)); \ 336 sparc_wrpr(pil, newpil, 0); \ 337 return (oldpil); \ 338 } 339 /* A non-priority-decreasing version of SPL */ 340 #define SPLHOLD(name, newpil) \ 341 extern __inline int name##X(const char *, int); \ 342 extern __inline int name##X(const char * file, int line) \ 343 { \ 344 int oldpil = sparc_rdpr(pil); \ 345 if (__predict_false((u_int64_t)newpil <= oldpil)) \ 346 return (oldpil); \ 347 SPLPRINT(("{%s:%d %d->!d}", file, line, oldpil, newpil)); \ 348 sparc_wrpr(pil, newpil, 0); \ 349 return (oldpil); \ 350 } 351 352 #else 353 #define SPLPRINT(x) 354 #define SPL(name, newpil) \ 355 extern __inline int name(void); \ 356 extern __inline int name() \ 357 { \ 358 int oldpil; \ 359 __asm __volatile(" rdpr %%pil, %0 \n" \ 360 " wrpr %%g0, %1, %%pil \n" \ 361 : "=&r" (oldpil) \ 362 : "n" (newpil) \ 363 : "%g0"); \ 364 __asm __volatile("" : : : "memory"); \ 365 return (oldpil); \ 366 } 367 /* A non-priority-decreasing version of SPL */ 368 #define SPLHOLD(name, newpil) \ 369 extern __inline int name(void); \ 370 extern __inline int name() \ 371 { \ 372 int oldpil; \ 373 \ 374 if (newpil <= 1) { \ 375 __asm __volatile(" rdpr %%pil, %0 \n" \ 376 " brnz,pn %0, 1f \n" \ 377 " nop \n" \ 378 " wrpr %%g0, %1, %%pil \n" \ 379 "1: \n" \ 380 : "=&r" (oldpil) \ 381 : "I" (newpil) \ 382 : "%g0"); \ 383 } else { \ 384 __asm __volatile(" rdpr %%pil, %0 \n" \ 385 " cmp %0, %1 - 1 \n" \ 386 " bgu,pn %%xcc, 1f \n" \ 387 " nop \n" \ 388 " wrpr %%g0, %1, %%pil \n" \ 389 "1: \n" \ 390 : "=&r" (oldpil) \ 391 : "I" (newpil) \ 392 : "cc"); \ 393 } \ 394 __asm __volatile("" : : : "memory"); \ 395 return (oldpil); \ 396 } 397 #endif 398 399 SPL(spl0, 0) 400 401 SPLHOLD(splsoftint, 1) 402 #define splsoftclock splsoftint 403 #define splsoftnet splsoftint 404 405 /* audio software interrupts are at software level 4 */ 406 SPLHOLD(splausoft, PIL_AUSOFT) 407 408 /* floppy software interrupts are at software level 4 too */ 409 SPLHOLD(splfdsoft, PIL_FDSOFT) 410 411 /* Block devices */ 412 SPLHOLD(splbio, PIL_BIO) 413 414 /* network hardware interrupts are at level 6 */ 415 SPLHOLD(splnet, PIL_NET) 416 417 /* tty input runs at software level 6 */ 418 SPLHOLD(spltty, PIL_TTY) 419 420 /* 421 * Memory allocation (must be as high as highest network, tty, or disk device) 422 */ 423 SPLHOLD(splvm, PIL_VM) 424 425 SPLHOLD(splclock, PIL_CLOCK) 426 427 /* fd hardware interrupts are at level 11 */ 428 SPLHOLD(splfd, PIL_FD) 429 430 /* zs hardware interrupts are at level 12 */ 431 SPLHOLD(splzs, PIL_SER) 432 SPLHOLD(splserial, PIL_SER) 433 434 /* audio hardware interrupts are at level 13 */ 435 SPLHOLD(splaudio, PIL_AUD) 436 437 /* second sparc timer interrupts at level 14 */ 438 SPLHOLD(splstatclock, PIL_STATCLOCK) 439 440 SPLHOLD(splsched, PIL_SCHED) 441 SPLHOLD(spllock, PIL_LOCK) 442 443 SPLHOLD(splhigh, PIL_HIGH) 444 445 /* splx does not have a return value */ 446 #ifdef SPLDEBUG 447 448 #define spl0() spl0X(__FILE__, __LINE__) 449 #define splsoftint() splsoftintX(__FILE__, __LINE__) 450 #define splausoft() splausoftX(__FILE__, __LINE__) 451 #define splfdsoft() splfdsoftX(__FILE__, __LINE__) 452 #define splbio() splbioX(__FILE__, __LINE__) 453 #define splnet() splnetX(__FILE__, __LINE__) 454 #define spltty() splttyX(__FILE__, __LINE__) 455 #define splvm() splvmX(__FILE__, __LINE__) 456 #define splclock() splclockX(__FILE__, __LINE__) 457 #define splfd() splfdX(__FILE__, __LINE__) 458 #define splzs() splzsX(__FILE__, __LINE__) 459 #define splserial() splzerialX(__FILE__, __LINE__) 460 #define splaudio() splaudioX(__FILE__, __LINE__) 461 #define splstatclock() splstatclockX(__FILE__, __LINE__) 462 #define splsched() splschedX(__FILE__, __LINE__) 463 #define spllock() spllockX(__FILE__, __LINE__) 464 #define splhigh() splhighX(__FILE__, __LINE__) 465 #define splx(x) splxX((x),__FILE__, __LINE__) 466 467 extern __inline void splxX(u_int64_t, const char *, int); 468 extern __inline void 469 splxX(u_int64_t newpil, const char *file, int line) 470 #else 471 extern __inline void splx(int newpil) 472 #endif 473 { 474 #ifdef SPLDEBUG 475 u_int64_t oldpil = sparc_rdpr(pil); 476 SPLPRINT(("{%d->%d}", oldpil, newpil)); 477 #endif 478 sparc_wrpr(pil, newpil, 0); 479 } 480 #endif /* KERNEL && !_LOCORE */ 481 482 #endif /* _SPARC64_PSL_ */ 483