1 /* $OpenBSD: pte.h,v 1.4 2003/05/17 19:30:55 art Exp $ */ 2 /* $NetBSD: pte.h,v 1.7 2001/07/31 06:55:46 eeh Exp $ */ 3 4 /* 5 * Copyright (c) 1996-1999 Eduardo Horvath 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 */ 26 27 /* 28 * Address translation works as follows: 29 * 30 ** 31 * For sun4u: 32 * 33 * Take your pick; it's all S/W anyway. We'll start by emulating a sun4. 34 * Oh, here's the sun4u TTE for reference: 35 * 36 * struct sun4u_tte { 37 * u_int64 tag_g:1, (global flag) 38 * tag_ctxt:15, (context for mapping) 39 * tag_unassigned:6, 40 * tag_va:42; (virtual address bits<64:22>) 41 * u_int64 data_v:1, (valid bit) 42 * data_size:2, (page size [8K*8**<SIZE>]) 43 * data_nfo:1, (no-fault only) 44 * data_ie:1, (invert endianness [inefficient]) 45 * data_soft2:2, (reserved for S/W) 46 * data_pa:36, (physical address) 47 * data_soft:6, (reserved for S/W) 48 * data_lock:1, (lock into TLB) 49 * data_cacheable:2, (cacheability control) 50 * data_e:1, (explicit accesses only) 51 * data_priv:1, (privileged page) 52 * data_w:1, (writeable) 53 * data_g:1; (same as tag_g) 54 * }; 55 */ 56 57 /* virtual address to virtual page number */ 58 #define VA_SUN4U_VPG(va) (((int)(va) >> 13) & 31) 59 60 /* virtual address to offset within page */ 61 #define VA_SUN4U_OFF(va) (((int)(va)) & 0x1FFF) 62 63 /* When we go to 64-bit VAs we need to handle the hole */ 64 #define VA_VPG(va) VA_SUN4U_VPG(va) 65 #define VA_OFF(va) VA_SUN4U_OFF(va) 66 67 #define PG_SHIFT4U 13 68 #define MMU_PAGE_ALIGN 8192 69 70 /* If you know where a tte is in the tsb, how do you find its va? */ 71 #define TSBVA(i) ((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000)) 72 73 #ifndef _LOCORE 74 /* 75 * This is the spitfire TTE. 76 * 77 * We could use bitmasks and shifts to construct this if 78 * we had a 64-bit compiler w/64-bit longs. Otherwise it's 79 * a real pain to do this in C. 80 */ 81 #if 0 82 /* We don't use bitfeilds anyway. */ 83 struct sun4u_tag_fields { 84 u_int64_t tag_g:1, /* global flag */ 85 tag_ctxt:15, /* context for mapping */ 86 tag_unassigned:6, 87 tag_va:42; /* virtual address bits<64:22> */ 88 }; 89 union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; }; 90 struct sun4u_data_fields { 91 u_int64_t data_v:1, /* valid bit */ 92 data_size:2, /* page size [8K*8**<SIZE>] */ 93 data_nfo:1, /* no-fault only */ 94 data_ie:1, /* invert endianness [inefficient] */ 95 data_soft2:2, /* reserved for S/W */ 96 data_pa:36, /* physical address */ 97 data_accessed:1,/* S/W accessed bit */ 98 data_modified:1,/* S/W modified bit */ 99 data_realw:1, /* S/W real writable bit (to manage modified) */ 100 data_tsblock:1, /* S/W TSB locked entry */ 101 data_exec:1, /* S/W Executable */ 102 data_onlyexec:1,/* S/W Executable only */ 103 data_lock:1, /* lock into TLB */ 104 data_cacheable:2, /* cacheability control */ 105 data_e:1, /* explicit accesses only */ 106 data_priv:1, /* privileged page */ 107 data_w:1, /* writeable */ 108 data_g:1; /* same as tag_g */ 109 }; 110 union sun4u_data { struct sun4u_data_fields f; int64_t data; }; 111 struct sun4u_tte { 112 union sun4u_tag tag; 113 union sun4u_data data; 114 }; 115 #else 116 struct sun4u_tte { 117 int64_t tag; 118 int64_t data; 119 }; 120 #endif 121 typedef struct sun4u_tte pte_t; 122 123 /* Assembly routine to flush a mapping */ 124 extern void tlb_flush_pte(vaddr_t addr, int ctx); 125 extern void tlb_flush_ctx(int ctx); 126 127 #endif /* _LOCORE */ 128 129 /* TSB tag masks */ 130 #define CTX_MASK ((1<<13)-1) 131 #define TSB_TAG_CTX_SHIFT 48 132 #define TSB_TAG_VA_SHIFT 22 133 #define TSB_TAG_G 0x8000000000000000LL 134 135 #define TSB_TAG_CTX(t) ((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK) 136 #define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT)) 137 #define TSB_TAG(g,ctx,va) ((((u_int64_t)((g)!=0))<<63)|(((u_int64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((u_int64_t)va)>>TSB_TAG_VA_SHIFT)) 138 139 /* Page sizes */ 140 #define PGSZ_8K 0 141 #define PGSZ_64K 1 142 #define PGSZ_512K 2 143 #define PGSZ_4M 3 144 145 #define PGSZ_SHIFT 61 146 147 /* 148 * Why couldn't Sun pick better page sizes? 149 * 150 * Page sizes are 2**(12+(3*sz)), except for 8K which 151 * is 2**12+1 instead of 2**12. 152 */ 153 #define PG_SZ(s) (1<<(12+(s?(3*s):1))) 154 #define TLB_SZ(s) (((uint64_t)(s))<<PGSZ_SHIFT) 155 156 /* TLB data masks */ 157 #define TLB_V 0x8000000000000000LL 158 #define TLB_8K TLB_SZ(PGSZ_8K) 159 #define TLB_64K TLB_SZ(PGSZ_64K) 160 #define TLB_512K TLB_SZ(PGSZ_512K) 161 #define TLB_4M TLB_SZ(PGSZ_4M) 162 #define TLB_SZ_MASK 0x6000000000000000LL 163 #define TLB_NFO 0x1000000000000000LL 164 #define TLB_IE 0x0800000000000000LL 165 #define TLB_SOFT2_MASK 0x07fe000000000000LL 166 #define TLB_DIAG_MASK 0x0001fe0000000000LL 167 #define TLB_PA_MASK 0x000001ffffffe000LL 168 #define TLB_SOFT_MASK 0x0000000000001f80LL 169 /* S/W bits */ 170 /* Access & TSB locked bits are swapped so I can set access w/one insn */ 171 /* #define TLB_ACCESS 0x0000000000001000LL */ 172 #define TLB_ACCESS 0x0000000000000200LL 173 #define TLB_MODIFY 0x0000000000000800LL 174 #define TLB_REAL_W 0x0000000000000400LL 175 /* #define TLB_TSB_LOCK 0x0000000000000200LL */ 176 #define TLB_TSB_LOCK 0x0000000000001000LL 177 #define TLB_EXEC 0x0000000000000100LL 178 #define TLB_EXEC_ONLY 0x0000000000000080LL 179 /* H/W bits */ 180 #define TLB_L 0x0000000000000040LL 181 #define TLB_CACHE_MASK 0x0000000000000030LL 182 #define TLB_CP 0x0000000000000020LL 183 #define TLB_CV 0x0000000000000010LL 184 #define TLB_E 0x0000000000000008LL 185 #define TLB_P 0x0000000000000004LL 186 #define TLB_W 0x0000000000000002LL 187 #define TLB_G 0x0000000000000001LL 188 189 #define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \ 190 (((valid)?TLB_V:0LL)|TLB_SZ(sz)|(((u_int64_t)(pa))&TLB_PA_MASK)|\ 191 ((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\ 192 ((priv)?TLB_P:0LL)|((write)?TLB_W:0LL)|((g)?TLB_G:0LL)|((ie)?TLB_IE:0LL)) 193 194 #define MMU_CACHE_VIRT 0x3 195 #define MMU_CACHE_PHYS 0x2 196 #define MMU_CACHE_NONE 0x0 197 198 /* This needs to be updated for sun4u IOMMUs */ 199 /* 200 * IOMMU PTE bits. 201 */ 202 #define IOPTE_PPN_MASK 0x07ffff00 203 #define IOPTE_PPN_SHIFT 8 204 #define IOPTE_RSVD 0x000000f1 205 #define IOPTE_WRITE 0x00000004 206 #define IOPTE_VALID 0x00000002 207