1 /* $OpenBSD: pte.h,v 1.15 2013/03/31 17:07:03 deraadt Exp $ */ 2 /* $NetBSD: pte.h,v 1.7 2001/07/31 06:55:46 eeh Exp $ */ 3 4 /* 5 * Copyright (c) 1996-1999 Eduardo Horvath 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 */ 26 27 #ifndef _MACHINE_PTE_H_ 28 #define _MACHINE_PTE_H_ 29 30 /* 31 * Address translation works as follows: 32 * 33 ** 34 * For sun4u: 35 * 36 * Take your pick; it's all S/W anyway. We'll start by emulating a sun4. 37 * Oh, here's the sun4u TTE for reference: 38 * 39 * struct sun4u_tte { 40 * u_int64 tag_g:1, (global flag) 41 * tag_ctxt:15, (context for mapping) 42 * tag_unassigned:6, 43 * tag_va:42; (virtual address bits<63:22>) 44 * u_int64 data_v:1, (valid bit) 45 * data_size:2, (page size [8K*8**<SIZE>]) 46 * data_nfo:1, (no-fault only) 47 * data_ie:1, (invert endianness [inefficient]) 48 * data_soft2:2, (reserved for S/W) 49 * data_pa:36, (physical address) 50 * data_soft:6, (reserved for S/W) 51 * data_lock:1, (lock into TLB) 52 * data_cacheable:2, (cacheability control) 53 * data_e:1, (explicit accesses only) 54 * data_priv:1, (privileged page) 55 * data_w:1, (writeable) 56 * data_g:1; (same as tag_g) 57 * }; 58 */ 59 60 /* virtual address to virtual page number */ 61 #define VA_SUN4U_VPG(va) (((int)(va) >> 13) & 31) 62 63 /* virtual address to offset within page */ 64 #define VA_SUN4U_OFF(va) (((int)(va)) & 0x1FFF) 65 66 /* When we go to 64-bit VAs we need to handle the hole */ 67 #define VA_VPG(va) VA_SUN4U_VPG(va) 68 #define VA_OFF(va) VA_SUN4U_OFF(va) 69 70 #define PG_SHIFT4U 13 71 #define MMU_PAGE_ALIGN 8192 72 73 /* If you know where a tte is in the tsb, how do you find its va? */ 74 #define TSBVA(i) ((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000)) 75 76 #ifndef _LOCORE 77 /* 78 * This is the spitfire TTE. 79 * 80 * We could use bitmasks and shifts to construct this if 81 * we had a 64-bit compiler w/64-bit longs. Otherwise it's 82 * a real pain to do this in C. 83 */ 84 #if 0 85 /* We don't use bitfields anyway. */ 86 struct sun4u_tag_fields { 87 u_int64_t tag_g:1, /* global flag */ 88 tag_ctxt:15, /* context for mapping */ 89 tag_unassigned:6, 90 tag_va:42; /* virtual address bits<64:22> */ 91 }; 92 union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; }; 93 struct sun4u_data_fields { 94 u_int64_t data_v:1, /* valid bit */ 95 data_size:2, /* page size [8K*8**<SIZE>] */ 96 data_nfo:1, /* no-fault only */ 97 data_ie:1, /* invert endianness [inefficient] */ 98 data_soft2:2, /* reserved for S/W */ 99 data_pa:36, /* physical address */ 100 data_accessed:1,/* S/W accessed bit */ 101 data_modified:1,/* S/W modified bit */ 102 data_realw:1, /* S/W real writable bit (to manage modified) */ 103 data_tsblock:1, /* S/W TSB locked entry */ 104 data_exec:1, /* S/W Executable */ 105 data_onlyexec:1,/* S/W Executable only */ 106 data_lock:1, /* lock into TLB */ 107 data_cacheable:2, /* cacheability control */ 108 data_e:1, /* explicit accesses only */ 109 data_priv:1, /* privileged page */ 110 data_w:1, /* writeable */ 111 data_g:1; /* same as tag_g */ 112 }; 113 union sun4u_data { struct sun4u_data_fields f; int64_t data; }; 114 struct sun4u_tte { 115 union sun4u_tag tag; 116 union sun4u_data data; 117 }; 118 #else 119 struct sun4u_tte { 120 int64_t tag; 121 int64_t data; 122 }; 123 #endif 124 typedef struct sun4u_tte pte_t; 125 126 /* Assembly routine to flush a mapping */ 127 extern void sp_tlb_flush_pte(vaddr_t addr, int ctx); 128 extern void sp_tlb_flush_ctx(int ctx); 129 130 #if defined(MULTIPROCESSOR) 131 void smp_tlb_flush_pte(vaddr_t, int); 132 void smp_tlb_flush_ctx(int); 133 #define tlb_flush_pte(va,ctx) smp_tlb_flush_pte(va, ctx) 134 #define tlb_flush_ctx(ctx) smp_tlb_flush_ctx(ctx) 135 #else 136 #define tlb_flush_pte(va,ctx) sp_tlb_flush_pte(va, ctx) 137 #define tlb_flush_ctx(ctx) sp_tlb_flush_ctx(ctx) 138 #endif 139 140 #endif /* _LOCORE */ 141 142 /* TSB tag masks */ 143 #define CTX_MASK ((1<<13)-1) 144 #define TSB_TAG_CTX_SHIFT 48 145 #define TSB_TAG_VA_SHIFT 22 146 147 #define TSB_TAG_LOCKED 0x0000040000000000LL 148 149 #define TSB_TAG_G 0x8000000000000000LL 150 #define TSB_TAG_CTX(t) ((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK) 151 #define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT)) 152 #define TSB_TAG(g,ctx,va) ((((u_int64_t)((g)!=0))<<63)|(((u_int64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((u_int64_t)va)>>TSB_TAG_VA_SHIFT)) 153 154 /* Page sizes */ 155 #define PGSZ_8K 0 156 #define PGSZ_64K 1 157 #define PGSZ_512K 2 158 #define PGSZ_4M 3 159 160 #define SUN4U_PGSZ_SHIFT 61 161 #define SUN4U_TLB_SZ(s) (((uint64_t)(s)) << SUN4U_PGSZ_SHIFT) 162 163 /* TLB data masks */ 164 #define SUN4U_TLB_V 0x8000000000000000LL 165 #define SUN4U_TLB_8K SUN4U_TLB_SZ(PGSZ_8K) 166 #define SUN4U_TLB_64K SUN4U_TLB_SZ(PGSZ_64K) 167 #define SUN4U_TLB_512K SUN4U_TLB_SZ(PGSZ_512K) 168 #define SUN4U_TLB_4M SUN4U_TLB_SZ(PGSZ_4M) 169 #define SUN4U_TLB_SZ_MASK 0x6000000000000000LL 170 #define SUN4U_TLB_NFO 0x1000000000000000LL 171 #define SUN4U_TLB_IE 0x0800000000000000LL 172 #define SUN4U_TLB_SOFT2_MASK 0x07fc000000000000LL 173 #define SUN4U_TLB_RESERVED_MASK 0x0003800000000000LL 174 #define SUN4U_TLB_PA_MASK 0x00007fffffffe000LL 175 #define SUN4U_TLB_SOFT_MASK 0x0000000000001f80LL 176 /* S/W bits */ 177 #define SUN4U_TLB_ACCESS 0x0000000000000200LL 178 #define SUN4U_TLB_MODIFY 0x0000000000000800LL 179 #define SUN4U_TLB_REAL_W 0x0000000000000400LL 180 #define SUN4U_TLB_TSB_LOCK 0x0000000000001000LL 181 #define SUN4U_TLB_EXEC 0x0000000000000100LL 182 #define SUN4U_TLB_EXEC_ONLY 0x0000000000000080LL 183 /* H/W bits */ 184 #define SUN4U_TLB_L 0x0000000000000040LL 185 #define SUN4U_TLB_CACHE_MASK 0x0000000000000030LL 186 #define SUN4U_TLB_CP 0x0000000000000020LL 187 #define SUN4U_TLB_CV 0x0000000000000010LL 188 #define SUN4U_TLB_E 0x0000000000000008LL 189 #define SUN4U_TLB_P 0x0000000000000004LL 190 #define SUN4U_TLB_W 0x0000000000000002LL 191 #define SUN4U_TLB_G 0x0000000000000001LL 192 193 #define SUN4U_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \ 194 (((valid)?SUN4U_TLB_V:0LL)|SUN4U_TLB_SZ(sz)|\ 195 (((u_int64_t)(pa))&SUN4U_TLB_PA_MASK)|\ 196 ((cache)?((aliased)?SUN4U_TLB_CP:SUN4U_TLB_CACHE_MASK):SUN4U_TLB_E)|\ 197 ((priv)?SUN4U_TLB_P:0LL)|((write)?SUN4U_TLB_W:0LL)|((g)?SUN4U_TLB_G:0LL)|\ 198 ((ie)?SUN4U_TLB_IE:0LL)) 199 200 #define SUN4V_PGSZ_SHIFT 0 201 #define SUN4V_TLB_SZ(s) (((uint64_t)(s))<<SUN4V_PGSZ_SHIFT) 202 203 /* TLB data masks */ 204 #define SUN4V_TLB_V 0x8000000000000000LL 205 #define SUN4V_TLB_8K SUN4V_TLB_SZ(PGSZ_8K) 206 #define SUN4V_TLB_64K SUN4V_TLB_SZ(PGSZ_64K) 207 #define SUN4V_TLB_512K SUN4V_TLB_SZ(PGSZ_512K) 208 #define SUN4V_TLB_4M SUN4V_TLB_SZ(PGSZ_4M) 209 #define SUN4V_TLB_SZ_MASK 0x000000000000000fLL 210 #define SUN4V_TLB_NFO 0x4000000000000000LL 211 #define SUN4V_TLB_IE 0x0000000000001000LL 212 #define SUN4V_TLB_SOFT2_MASK 0x3f00000000000000LL 213 #define SUN4V_TLB_PA_MASK 0x00ffffffffffe000LL 214 #define SUN4V_TLB_SOFT_MASK 0x0000000000000030LL 215 /* S/W bits */ 216 #define SUN4V_TLB_ACCESS 0x0000000000000010LL 217 #define SUN4V_TLB_MODIFY 0x0000000000000020LL 218 #define SUN4V_TLB_REAL_W 0x2000000000000000LL 219 #define SUN4V_TLB_TSB_LOCK 0x1000000000000000LL 220 #define SUN4V_TLB_EXEC SUN4V_TLB_X 221 #define SUN4V_TLB_EXEC_ONLY 0x0200000000000000LL 222 /* H/W bits */ 223 #define SUN4V_TLB_CACHE_MASK 0x0000000000000600LL 224 #define SUN4V_TLB_CP 0x0000000000000400LL 225 #define SUN4V_TLB_CV 0x0000000000000200LL 226 #define SUN4V_TLB_E 0x0000000000000800LL 227 #define SUN4V_TLB_P 0x0000000000000100LL 228 #define SUN4V_TLB_X 0x0000000000000080LL 229 #define SUN4V_TLB_W 0x0000000000000040LL 230 #define SUN4V_TLB_G 0x0000000000000000LL 231 232 #define SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \ 233 (((valid)?SUN4V_TLB_V:0LL)|SUN4V_TLB_SZ(sz)|\ 234 (((u_int64_t)(pa))&SUN4V_TLB_PA_MASK)|\ 235 ((cache)?((aliased)?SUN4V_TLB_CP:SUN4V_TLB_CACHE_MASK):SUN4V_TLB_E)|\ 236 ((priv)?SUN4V_TLB_P:0LL)|((write)?SUN4V_TLB_W:0LL)|((g)?SUN4V_TLB_G:0LL)|\ 237 ((ie)?SUN4V_TLB_IE:0LL)) 238 239 240 #define MMU_CACHE_VIRT 0x3 241 #define MMU_CACHE_PHYS 0x2 242 #define MMU_CACHE_NONE 0x0 243 244 /* This needs to be updated for sun4u IOMMUs */ 245 /* 246 * IOMMU PTE bits. 247 */ 248 #define IOPTE_PPN_MASK 0x07ffff00 249 #define IOPTE_PPN_SHIFT 8 250 #define IOPTE_RSVD 0x000000f1 251 #define IOPTE_WRITE 0x00000004 252 #define IOPTE_VALID 0x00000002 253 254 #endif /* _MACHINE_PTE_H_ */ 255 256