1 /* $OpenBSD: acpireg.h,v 1.29 2013/11/06 10:40:36 mpi Exp $ */ 2 /* 3 * Copyright (c) 2005 Thorsten Lockert <tholo@sigmasoft.com> 4 * Copyright (c) 2005 Marco Peereboom <marco@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DEV_ACPI_ACPIREG_H_ 20 #define _DEV_ACPI_ACPIREG_H_ 21 22 /* Root System Descriptor Pointer */ 23 struct acpi_rsdp1 { 24 u_int8_t signature[8]; 25 #define RSDP_SIG "RSD PTR " 26 #define rsdp_signaturee rsdp1.signature 27 u_int8_t checksum; /* make sum == 0 */ 28 #define rsdp_checksum rsdp1.checksum 29 u_int8_t oemid[6]; 30 #define rsdp_oemid rsdp1.oemid 31 u_int8_t revision; /* 0 for 1, 2 for 2 */ 32 #define rsdp_revision rsdp1.revision 33 u_int32_t rsdt; /* physical */ 34 #define rsdp_rsdt rsdp1.rsdt 35 } __packed; 36 37 struct acpi_rsdp { 38 struct acpi_rsdp1 rsdp1; 39 /* 40 * The following values are only valid 41 * when rsdp_revision == 2 42 */ 43 u_int32_t rsdp_length; /* length of rsdp */ 44 u_int64_t rsdp_xsdt; /* physical */ 45 u_int8_t rsdp_extchecksum; /* entire table */ 46 u_int8_t rsdp_reserved[3]; /* must be zero */ 47 } __packed; 48 49 struct acpi_table_header { 50 u_int8_t signature[4]; 51 #define hdr_signature hdr.signature 52 u_int32_t length; 53 #define hdr_length hdr.length 54 u_int8_t revision; 55 #define hdr_revision hdr.revision 56 u_int8_t checksum; 57 #define hdr_checksum hdr.checksum 58 u_int8_t oemid[6]; 59 #define hdr_oemid hdr.oemid 60 u_int8_t oemtableid[8]; 61 #define hdr_oemtableid hdr.oemtableid 62 u_int32_t oemrevision; 63 #define hdr_oemrevision hdr.oemrevision 64 u_int8_t aslcompilerid[4]; 65 #define hdr_aslcompilerid hdr.aslcompilerid 66 u_int32_t aslcompilerrevision; 67 #define hdr_aslcompilerrevision hdr.aslcompilerrevision 68 } __packed; 69 70 struct acpi_rsdt { 71 struct acpi_table_header hdr; 72 #define RSDT_SIG "RSDT" 73 u_int32_t table_offsets[1]; 74 } __packed; 75 76 struct acpi_xsdt { 77 struct acpi_table_header hdr; 78 #define XSDT_SIG "XSDT" 79 u_int64_t table_offsets[1]; 80 } __packed; 81 82 struct acpi_gas { 83 u_int8_t address_space_id; 84 #define GAS_SYSTEM_MEMORY 0 85 #define GAS_SYSTEM_IOSPACE 1 86 #define GAS_PCI_CFG_SPACE 2 87 #define GAS_EMBEDDED 3 88 #define GAS_SMBUS 4 89 #define GAS_FUNCTIONAL_FIXED 127 90 u_int8_t register_bit_width; 91 u_int8_t register_bit_offset; 92 u_int8_t access_size; 93 #define GAS_ACCESS_UNDEFINED 0 94 #define GAS_ACCESS_BYTE 1 95 #define GAS_ACCESS_WORD 2 96 #define GAS_ACCESS_DWORD 3 97 #define GAS_ACCESS_QWORD 4 98 u_int64_t address; 99 } __packed; 100 101 struct acpi_fadt { 102 struct acpi_table_header hdr; 103 #define FADT_SIG "FACP" 104 u_int32_t firmware_ctl; /* phys addr FACS */ 105 u_int32_t dsdt; /* phys addr DSDT */ 106 u_int8_t int_model; /* interrupt model (hdr_revision < 3) */ 107 #define FADT_INT_DUAL_PIC 0 108 #define FADT_INT_MULTI_APIC 1 109 u_int8_t pm_profile; /* power mgmt profile */ 110 #define FADT_PM_UNSPEC 0 111 #define FADT_PM_DESKTOP 1 112 #define FADT_PM_MOBILE 2 113 #define FADT_PM_WORKSTATION 3 114 #define FADT_PM_ENT_SERVER 4 115 #define FADT_PM_SOHO_SERVER 5 116 #define FADT_PM_APPLIANCE 6 117 #define FADT_PM_PERF_SERVER 7 118 u_int16_t sci_int; /* SCI interrupt */ 119 u_int32_t smi_cmd; /* SMI command port */ 120 u_int8_t acpi_enable; /* value to enable */ 121 u_int8_t acpi_disable; /* value to disable */ 122 u_int8_t s4bios_req; /* value for S4 */ 123 u_int8_t pstate_cnt; /* value for performance (hdr_revision > 2) */ 124 u_int32_t pm1a_evt_blk; /* power management 1a */ 125 u_int32_t pm1b_evt_blk; /* power mangement 1b */ 126 u_int32_t pm1a_cnt_blk; /* pm control 1a */ 127 u_int32_t pm1b_cnt_blk; /* pm control 1b */ 128 u_int32_t pm2_cnt_blk; /* pm control 2 */ 129 u_int32_t pm_tmr_blk; 130 u_int32_t gpe0_blk; 131 u_int32_t gpe1_blk; 132 u_int8_t pm1_evt_len; 133 u_int8_t pm1_cnt_len; 134 u_int8_t pm2_cnt_len; 135 u_int8_t pm_tmr_len; 136 u_int8_t gpe0_blk_len; 137 u_int8_t gpe1_blk_len; 138 u_int8_t gpe1_base; 139 u_int8_t cst_cnt; /* (hdr_revision > 2) */ 140 u_int16_t p_lvl2_lat; 141 u_int16_t p_lvl3_lat; 142 u_int16_t flush_size; 143 u_int16_t flush_stride; 144 u_int8_t duty_offset; 145 u_int8_t duty_width; 146 u_int8_t day_alrm; 147 u_int8_t mon_alrm; 148 u_int8_t century; 149 u_int16_t iapc_boot_arch; /* (hdr_revision > 2) */ 150 #define FADT_LEGACY_DEVICES 0x0001 /* Legacy devices supported */ 151 #define FADT_i8042 0x0002 /* Keyboard controller present */ 152 #define FADT_NO_VGA 0x0004 /* Do not probe VGA */ 153 u_int8_t reserved1; 154 u_int32_t flags; 155 #define FADT_WBINVD 0x00000001 156 #define FADT_WBINVD_FLUSH 0x00000002 157 #define FADT_PROC_C1 0x00000004 158 #define FADT_P_LVL2_UP 0x00000008 159 #define FADT_PWR_BUTTON 0x00000010 160 #define FADT_SLP_BUTTON 0x00000020 161 #define FADT_FIX_RTC 0x00000040 162 #define FADT_RTC_S4 0x00000080 163 #define FADT_TMR_VAL_EXT 0x00000100 164 #define FADT_DCK_CAP 0x00000200 165 #define FADT_RESET_REG_SUP 0x00000400 166 #define FADT_SEALED_CASE 0x00000800 167 #define FADT_HEADLESS 0x00001000 168 #define FADT_CPU_SW_SLP 0x00002000 169 #define FADT_PCI_EXP_WAK 0x00004000 170 #define FADT_USE_PLATFORM_CLOCK 0x00008000 171 #define FADT_S4_RTC_STS_VALID 0x00010000 172 #define FADT_REMOTE_POWER_ON_CAPABLE 0x00020000 173 #define FADT_FORCE_APIC_CLUSTER_MODEL 0x00040000 174 #define FADT_FORCE_APIC_PHYS_DEST_MODE 0x00080000 175 /* 176 * Following values only exist when rev > 1 177 * If the extended addresses exists, they 178 * must be used in preferense to the non- 179 * extended values above 180 */ 181 struct acpi_gas reset_reg; 182 u_int8_t reset_value; 183 u_int8_t reserved2a; 184 u_int8_t reserved2b; 185 u_int8_t reserved2c; 186 u_int64_t x_firmware_ctl; 187 u_int64_t x_dsdt; 188 struct acpi_gas x_pm1a_evt_blk; 189 struct acpi_gas x_pm1b_evt_blk; 190 struct acpi_gas x_pm1a_cnt_blk; 191 struct acpi_gas x_pm1b_cnt_blk; 192 struct acpi_gas x_pm2_cnt_blk; 193 struct acpi_gas x_pm_tmr_blk; 194 struct acpi_gas x_gpe0_blk; 195 struct acpi_gas x_gpe1_blk; 196 } __packed; 197 198 struct acpi_dsdt { 199 struct acpi_table_header hdr; 200 #define DSDT_SIG "DSDT" 201 u_int8_t aml[1]; 202 } __packed; 203 204 struct acpi_ssdt { 205 struct acpi_table_header hdr; 206 #define SSDT_SIG "SSDT" 207 u_int8_t aml[1]; 208 } __packed; 209 210 /* 211 * Table deprecated by ACPI 2.0 212 */ 213 struct acpi_psdt { 214 struct acpi_table_header hdr; 215 #define PSDT_SIG "PSDT" 216 } __packed; 217 218 struct acpi_madt { 219 struct acpi_table_header hdr; 220 #define MADT_SIG "APIC" 221 u_int32_t local_apic_address; 222 u_int32_t flags; 223 #define ACPI_APIC_PCAT_COMPAT 0x00000001 224 } __packed; 225 226 struct acpi_madt_lapic { 227 u_int8_t apic_type; 228 #define ACPI_MADT_LAPIC 0 229 u_int8_t length; 230 u_int8_t acpi_proc_id; 231 u_int8_t apic_id; 232 u_int32_t flags; 233 #define ACPI_PROC_ENABLE 0x00000001 234 } __packed; 235 236 struct acpi_madt_ioapic { 237 u_int8_t apic_type; 238 #define ACPI_MADT_IOAPIC 1 239 u_int8_t length; 240 u_int8_t acpi_ioapic_id; 241 u_int8_t reserved; 242 u_int32_t address; 243 u_int32_t global_int_base; 244 } __packed; 245 246 struct acpi_madt_override { 247 u_int8_t apic_type; 248 #define ACPI_MADT_OVERRIDE 2 249 u_int8_t length; 250 u_int8_t bus; 251 #define ACPI_OVERRIDE_BUS_ISA 0 252 u_int8_t source; 253 u_int32_t global_int; 254 u_int16_t flags; 255 #define ACPI_OVERRIDE_POLARITY_BITS 0x3 256 #define ACPI_OVERRIDE_POLARITY_BUS 0x0 257 #define ACPI_OVERRIDE_POLARITY_HIGH 0x1 258 #define ACPI_OVERRIDE_POLARITY_LOW 0x3 259 #define ACPI_OVERRIDE_TRIGGER_BITS 0xc 260 #define ACPI_OVERRIDE_TRIGGER_BUS 0x0 261 #define ACPI_OVERRIDE_TRIGGER_EDGE 0x4 262 #define ACPI_OVERRIDE_TRIGGER_LEVEL 0xc 263 } __packed; 264 265 struct acpi_madt_nmi { 266 u_int8_t apic_type; 267 #define ACPI_MADT_NMI 3 268 u_int8_t length; 269 u_int16_t flags; /* Same flags as acpi_madt_override */ 270 u_int32_t global_int; 271 } __packed; 272 273 struct acpi_madt_lapic_nmi { 274 u_int8_t apic_type; 275 #define ACPI_MADT_LAPIC_NMI 4 276 u_int8_t length; 277 u_int8_t acpi_proc_id; 278 u_int16_t flags; /* Same flags as acpi_madt_override */ 279 u_int8_t local_apic_lint; 280 } __packed; 281 282 struct acpi_madt_lapic_override { 283 u_int8_t apic_type; 284 #define ACPI_MADT_LAPIC_OVERRIDE 5 285 u_int8_t length; 286 u_int16_t reserved; 287 u_int64_t lapic_address; 288 } __packed; 289 290 struct acpi_madt_io_sapic { 291 u_int8_t apic_type; 292 #define ACPI_MADT_IO_SAPIC 6 293 u_int8_t length; 294 u_int8_t iosapic_id; 295 u_int8_t reserved; 296 u_int32_t global_int_base; 297 u_int64_t iosapic_address; 298 } __packed; 299 300 struct acpi_madt_local_sapic { 301 u_int8_t apic_type; 302 #define ACPI_MADT_LOCAL_SAPIC 7 303 u_int8_t length; 304 u_int8_t acpi_proc_id; 305 u_int8_t local_sapic_id; 306 u_int8_t local_sapic_eid; 307 u_int8_t reserved[3]; 308 u_int32_t flags; /* Same flags as acpi_madt_lapic */ 309 u_int32_t acpi_proc_uid; 310 u_int8_t acpi_proc_uid_string[1]; 311 } __packed; 312 313 struct acpi_madt_platform_int { 314 u_int8_t apic_type; 315 #define ACPI_MADT_PLATFORM_INT 8 316 u_int8_t length; 317 u_int16_t flags; /* Same flags as acpi_madt_override */ 318 u_int8_t int_type; 319 #define ACPI_MADT_PLATFORM_PMI 1 320 #define ACPI_MADT_PLATFORM_INIT 2 321 #define ACPI_MADT_PLATFORM_CORR_ERROR 3 322 u_int8_t proc_id; 323 u_int8_t proc_eid; 324 u_int8_t io_sapic_vec; 325 u_int32_t global_int; 326 u_int32_t platform_int_flags; 327 #define ACPI_MADT_PLATFORM_CPEI 0x00000001 328 } __packed; 329 330 struct acpi_madt_x2apic { 331 u_int8_t apic_type; 332 #define ACPI_MADT_X2APIC 9 333 u_int8_t length; 334 u_int8_t reserved[2]; 335 u_int32_t apic_id; 336 u_int32_t flags; /* Same flags as acpi_madt_lapic */ 337 u_int32_t apic_proc_uid; 338 } __packed; 339 340 struct acpi_madt_x2apic_nmi { 341 u_int8_t apic_type; 342 #define ACPI_MADT_X2APIC_NMI 10 343 u_int8_t length; 344 u_int16_t flags; /* Same flags as acpi_madt_override */ 345 u_int32_t apic_proc_uid; 346 u_int8_t local_x2apic_lint; 347 u_int8_t reserved[3]; 348 } __packed; 349 350 union acpi_madt_entry { 351 struct acpi_madt_lapic madt_lapic; 352 struct acpi_madt_ioapic madt_ioapic; 353 struct acpi_madt_override madt_override; 354 struct acpi_madt_nmi madt_nmi; 355 struct acpi_madt_lapic_nmi madt_lapic_nmi; 356 struct acpi_madt_lapic_override madt_lapic_override; 357 struct acpi_madt_io_sapic madt_io_sapic; 358 struct acpi_madt_local_sapic madt_local_sapic; 359 struct acpi_madt_platform_int madt_platform_int; 360 struct acpi_madt_x2apic madt_x2apic; 361 struct acpi_madt_x2apic_nmi madt_x2apic_nmi; 362 } __packed; 363 364 struct acpi_sbst { 365 struct acpi_table_header hdr; 366 #define SBST_SIG "SBST" 367 u_int32_t warning_energy_level; 368 u_int32_t low_energy_level; 369 u_int32_t critical_energy_level; 370 } __packed; 371 372 struct acpi_ecdt { 373 struct acpi_table_header hdr; 374 #define ECDT_SIG "ECDT" 375 struct acpi_gas ec_control; 376 struct acpi_gas ec_data; 377 u_int32_t uid; 378 u_int8_t gpe_bit; 379 u_int8_t ec_id[1]; 380 } __packed; 381 382 struct acpi_srat { 383 struct acpi_table_header hdr; 384 #define SRAT_SIG "SRAT" 385 u_int32_t reserved1; 386 u_int64_t reserved2; 387 } __packed; 388 389 struct acpi_slit { 390 struct acpi_table_header hdr; 391 #define SLIT_SIG "SLIT" 392 u_int64_t number_of_localities; 393 } __packed; 394 395 struct acpi_hpet { 396 struct acpi_table_header hdr; 397 #define HPET_SIG "HPET" 398 u_int32_t event_timer_block_id; 399 struct acpi_gas base_address; 400 u_int8_t hpet_number; 401 u_int16_t main_counter_min_clock_tick; 402 u_int8_t page_protection; 403 } __packed; 404 405 struct acpi_mcfg { 406 struct acpi_table_header hdr; 407 #define MCFG_SIG "MCFG" 408 u_int8_t reserved[8]; 409 u_int64_t base_address; 410 u_int16_t segment; 411 u_int8_t min_bus_number; 412 u_int8_t max_bus_number; 413 u_int32_t reserved1; 414 } __packed; 415 416 struct acpi_facs { 417 u_int8_t signature[4]; 418 #define FACS_SIG "FACS" 419 u_int32_t length; 420 u_int32_t hardware_signature; 421 u_int32_t wakeup_vector; 422 u_int32_t global_lock; 423 #define FACS_LOCK_PENDING 0x00000001 424 #define FACS_LOCK_OWNED 0x00000002 425 u_int32_t flags; 426 #define FACS_S4BIOS_F 0x00000001 /* S4BIOS_REQ supported */ 427 uint64_t x_wakeup_vector; 428 u_int8_t version; 429 u_int8_t reserved[31]; 430 } __packed; 431 432 /* 433 * Intel ACPI DMA Remapping Entries 434 */ 435 struct acpidmar_devpath { 436 uint8_t device; 437 uint8_t function; 438 } __packed; 439 440 struct acpidmar_devscope { 441 uint8_t type; 442 #define DMAR_ENDPOINT 0x1 443 #define DMAR_BRIDGE 0x2 444 #define DMAR_IOAPIC 0x3 445 #define DMAR_HPET 0x4 446 uint8_t length; 447 uint16_t reserved; 448 uint8_t enumid; 449 uint8_t bus; 450 } __packed; 451 452 /* DMA Remapping Hardware Unit */ 453 struct acpidmar_drhd { 454 uint16_t type; 455 uint16_t length; 456 457 uint8_t flags; 458 uint8_t reserved; 459 uint16_t segment; 460 uint64_t address; 461 /* struct acpidmar_devscope[]; */ 462 } __packed; 463 464 /* Reserved Memory Region Reporting */ 465 struct acpidmar_rmrr { 466 uint16_t type; 467 uint16_t length; 468 469 uint16_t reserved; 470 uint16_t segment; 471 uint64_t base; 472 uint64_t limit; 473 /* struct acpidmar_devscope[]; */ 474 } __packed; 475 476 /* Root Port ATS Capability Reporting */ 477 struct acpidmar_atsr { 478 uint16_t type; 479 uint16_t length; 480 481 uint8_t flags; 482 uint8_t reserved; 483 uint16_t segment; 484 /* struct acpidmar_devscope[]; */ 485 } __packed; 486 487 union acpidmar_entry { 488 struct { 489 uint16_t type; 490 #define DMAR_DRHD 0x0 491 #define DMAR_RMRR 0x1 492 #define DMAR_ATSR 0x2 493 #define DMAR_RHSA 0x3 494 uint16_t length; 495 } __packed; 496 struct acpidmar_drhd drhd; 497 struct acpidmar_rmrr rmrr; 498 struct acpidmar_atsr atsr; 499 } __packed; 500 501 struct acpi_dmar { 502 struct acpi_table_header hdr; 503 #define DMAR_SIG "DMAR" 504 uint8_t haw; 505 uint8_t flags; 506 uint8_t reserved[10]; 507 /* struct acpidmar_entry[]; */ 508 } __packed; 509 510 /* 511 * AMD I/O Virtualization Remapping Entries 512 */ 513 union acpi_ivhd_entry { 514 uint8_t type; 515 #define IVHD_ALL 1 516 #define IVHD_SEL 2 517 #define IVHD_SOR 3 518 #define IVHD_EOR 4 519 #define IVHD_ALIAS_SEL 66 520 #define IVHD_ALIAS_SOR 67 521 #define IVHD_EXT_SEL 70 522 #define IVHD_EXT_SOR 71 523 #define IVHD_SPECIAL 72 524 struct { 525 uint8_t type; 526 uint16_t resvd; 527 uint8_t data; 528 } __packed all; 529 struct { 530 uint8_t type; 531 uint16_t devid; 532 uint8_t data; 533 } __packed sel; 534 struct { 535 uint8_t type; 536 uint16_t devid; 537 uint8_t data; 538 } __packed sor; 539 struct { 540 uint8_t type; 541 uint16_t devid; 542 uint8_t resvd; 543 } __packed eor; 544 struct { 545 uint8_t type; 546 uint16_t devid; 547 uint8_t data; 548 uint8_t resvd1; 549 uint16_t srcid; 550 uint8_t resvd2; 551 } __packed alias; 552 struct { 553 uint8_t type; 554 uint16_t devid; 555 uint8_t data; 556 uint32_t extdata; 557 #define IVHD_ATS_DIS (1L << 31) 558 } __packed ext; 559 struct { 560 uint8_t type; 561 uint16_t resvd; 562 uint8_t data; 563 uint8_t handle; 564 uint16_t devid; 565 uint8_t variety; 566 #define IVHD_IOAPIC 0x01 567 #define IVHD_HPET 0x02 568 } __packed special; 569 } __packed; 570 571 struct acpi_ivmd { 572 uint8_t type; 573 uint8_t flags; 574 #define IVMD_EXCLRANGE (1L << 3) 575 #define IVMD_IW (1L << 2) 576 #define IVMD_IR (1L << 1) 577 #define IVMD_UNITY (1L << 0) 578 uint16_t length; 579 uint16_t devid; 580 uint16_t auxdata; 581 uint8_t reserved[8]; 582 uint64_t base; 583 uint64_t limit; 584 } __packed; 585 586 struct acpi_ivhd { 587 uint8_t type; 588 uint8_t flags; 589 #define IVHD_IOTLB (1L << 4) 590 #define IVHD_ISOC (1L << 3) 591 #define IVHD_RESPASSPW (1L << 2) 592 #define IVHD_PASSPW (1L << 1) 593 #define IVHD_HTTUNEN (1L << 0) 594 uint16_t length; 595 uint16_t devid; 596 uint16_t cap; 597 uint64_t address; 598 uint16_t segment; 599 uint16_t info; 600 #define IVHD_UNITID_SHIFT 8 601 #define IVHD_UNITID_MASK 0x1F 602 #define IVHD_MSINUM_SHIFT 0 603 #define IVHD_MSINUM_MASK 0x1F 604 uint32_t reserved; 605 } __packed; 606 607 union acpi_ivrs_entry { 608 struct { 609 uint8_t type; 610 #define IVRS_IVHD 0x10 611 #define IVRS_IVMD_ALL 0x20 612 #define IVRS_IVMD_SPECIFIED 0x21 613 #define IVRS_IVMD_RANGE 0x22 614 uint8_t flags; 615 uint16_t length; 616 } __packed; 617 struct acpi_ivhd ivhd; 618 struct acpi_ivmd ivmd; 619 } __packed; 620 621 struct acpi_ivrs { 622 struct acpi_table_header hdr; 623 #define IVRS_SIG "IVRS" 624 uint32_t ivinfo; 625 #define IVRS_ATSRNG (1L << 22) 626 #define IVRS_VASIZE_SHIFT 15 627 #define IVRS_VASIZE_MASK 0x7F 628 #define IVRS_PASIZE_SHIFT 8 629 #define IVRS_PASIZE_MASK 0x7F 630 uint8_t reserved[8]; 631 } __packed; 632 633 634 #define ACPI_FREQUENCY 3579545 /* Per ACPI spec */ 635 636 /* 637 * PCI Configuration space 638 */ 639 #define ACPI_ADR_PCIDEV(addr) (u_int16_t)(addr >> 16) 640 #define ACPI_ADR_PCIFUN(addr) (u_int16_t)(addr & 0xFFFF) 641 #define ACPI_PCI_BUS(addr) (u_int16_t)((addr) >> 48) 642 #define ACPI_PCI_DEV(addr) (u_int16_t)((addr) >> 32) 643 #define ACPI_PCI_FN(addr) (u_int16_t)((addr) >> 16) 644 #define ACPI_PCI_REG(addr) (u_int16_t)(addr) 645 #define ACPI_PCI_ADDR(b,d,f,r) ((u_int64_t)(b)<<48LL | (u_int64_t)(d)<<32LL | (f)<<16LL | (r)) 646 647 /* 648 * PM1 Status Registers Fixed Hardware Feature Status Bits 649 */ 650 #define ACPI_PM1_STATUS 0x00 651 #define ACPI_PM1_TMR_STS 0x0001 652 #define ACPI_PM1_BM_STS 0x0010 653 #define ACPI_PM1_GBL_STS 0x0020 654 #define ACPI_PM1_PWRBTN_STS 0x0100 655 #define ACPI_PM1_SLPBTN_STS 0x0200 656 #define ACPI_PM1_RTC_STS 0x0400 657 #define ACPI_PM1_PCIEXP_WAKE_STS 0x4000 658 #define ACPI_PM1_WAK_STS 0x8000 659 660 #define ACPI_PM1_ALL_STS (ACPI_PM1_TMR_STS | ACPI_PM1_BM_STS | \ 661 ACPI_PM1_GBL_STS | ACPI_PM1_PWRBTN_STS | \ 662 ACPI_PM1_SLPBTN_STS | ACPI_PM1_RTC_STS | \ 663 ACPI_PM1_PCIEXP_WAKE_STS | ACPI_PM1_WAK_STS ) 664 665 /* 666 * PM1 Enable Registers 667 */ 668 #define ACPI_PM1_ENABLE 0x02 669 #define ACPI_PM1_TMR_EN 0x0001 670 #define ACPI_PM1_GBL_EN 0x0020 671 #define ACPI_PM1_PWRBTN_EN 0x0100 672 #define ACPI_PM1_SLPBTN_EN 0x0200 673 #define ACPI_PM1_RTC_EN 0x0400 674 #define ACPI_PM1_PCIEXP_WAKE_DIS 0x4000 675 676 /* 677 * PM1 Control Registers 678 */ 679 #define ACPI_PM1_CONTROL 0x00 680 #define ACPI_PM1_SCI_EN 0x0001 681 #define ACPI_PM1_BM_RLD 0x0002 682 #define ACPI_PM1_GBL_RLS 0x0004 683 #define ACPI_PM1_SLP_TYPX(x) ((x) << 10) 684 #define ACPI_PM1_SLP_TYPX_MASK 0x1c00 685 #define ACPI_PM1_SLP_EN 0x2000 686 687 /* 688 * PM2 Control Registers 689 */ 690 #define ACPI_PM2_CONTROL 0x06 691 #define ACPI_PM2_ARB_DIS 0x0001 692 693 694 /* 695 * Sleeping States 696 */ 697 #define ACPI_STATE_S0 0 698 #define ACPI_STATE_S1 1 699 #define ACPI_STATE_S2 2 700 #define ACPI_STATE_S3 3 701 #define ACPI_STATE_S4 4 702 #define ACPI_STATE_S5 5 703 704 /* 705 * Device Power States 706 */ 707 #define ACPI_STATE_D0 0 708 #define ACPI_STATE_D1 1 709 #define ACPI_STATE_D2 2 710 #define ACPI_STATE_D3 3 711 712 /* 713 * ACPI Device IDs 714 */ 715 #define ACPI_DEV_TIM "PNP0100" /* System timer */ 716 #define ACPI_DEV_ACPI "PNP0C08" /* ACPI device */ 717 #define ACPI_DEV_PCIB "PNP0A03" /* PCI bus */ 718 #define ACPI_DEV_GISAB "PNP0A05" /* Generic ISA Bus */ 719 #define ACPI_DEV_EIOB "PNP0A06" /* Extended I/O Bus */ 720 #define ACPI_DEV_PCIEB "PNP0A08" /* PCIe bus */ 721 #define ACPI_DEV_MR "PNP0C02" /* Motherboard resources */ 722 #define ACPI_DEV_NPROC "PNP0C04" /* Numeric data processor */ 723 #define ACPI_DEV_CS "PNP0C08" /* ACPI-Compliant System */ 724 #define ACPI_DEV_ECD "PNP0C09" /* Embedded Controller Device */ 725 #define ACPI_DEV_CMB "PNP0C0A" /* Control Method Battery */ 726 #define ACPI_DEV_FAN "PNP0C0B" /* Fan Device */ 727 #define ACPI_DEV_PBD "PNP0C0C" /* Power Button Device */ 728 #define ACPI_DEV_LD "PNP0C0D" /* Lid Device */ 729 #define ACPI_DEV_SBD "PNP0C0E" /* Sleep Button Device */ 730 #define ACPI_DEV_PILD "PNP0C0F" /* PCI Interrupt Link Device */ 731 #define ACPI_DEV_MEMD "PNP0C80" /* Memory Device */ 732 #define ACPI_DEV_SHC "ACPI0001" /* SMBus 1.0 Host Controller */ 733 #define ACPI_DEV_SMS1 "ACPI0002" /* Smart Battery Subsystem */ 734 #define ACPI_DEV_AC "ACPI0003" /* AC Device */ 735 #define ACPI_DEV_MD "ACPI0004" /* Module Device */ 736 #define ACPI_DEV_SMS2 "ACPI0005" /* SMBus 2.0 Host Controller */ 737 #define ACPI_DEV_GBD "ACPI0006" /* GPE Block Device */ 738 #define ACPI_DEV_PD "ACPI0007" /* Processor Device */ 739 #define ACPI_DEV_ALSD "ACPI0008" /* Ambient Light Sensor Device */ 740 #define ACPI_DEV_IOXA "ACPI0009" /* IO x APIC Device */ 741 #define ACPI_DEV_IOA "ACPI000A" /* IO APIC Device */ 742 #define ACPI_DEV_IOSA "ACPI000B" /* IO SAPIC Device */ 743 #define ACPI_DEV_THZ "THERMALZONE" /* Thermal Zone */ 744 #define ACPI_DEV_FFB "FIXEDBUTTON" /* Fixed Feature Button */ 745 #define ACPI_DEV_ASUS "ASUS010" /* ASUS Hotkeys */ 746 #define ACPI_DEV_ASUS1 "ATK0100" /* ASUS Special Device */ 747 #define ACPI_DEV_IBM "IBM0068" /* IBM ThinkPad support */ 748 #define ACPI_DEV_LENOVO "LEN0068" /* Lenovo ThinkPad support */ 749 #define ACPI_DEV_ASUSAIBOOSTER "ATK0110" /* ASUSTeK AI Booster */ 750 #define ACPI_DEV_TOSHIBA_LIBRETTO "TOS6200" /* Toshiba Libretto support */ 751 #define ACPI_DEV_TOSHIBA_DYNABOOK "TOS6207" /* Toshiba Dynabook support */ 752 #define ACPI_DEV_TOSHIBA_SPA40 "TOS6208" /* Toshiba SPA40 support */ 753 754 #endif /* !_DEV_ACPI_ACPIREG_H_ */ 755