1 /* $OpenBSD: if_ath_cardbus.c,v 1.15 2010/03/27 21:40:13 jsg Exp $ */ 2 /* $NetBSD: if_ath_cardbus.c,v 1.4 2004/08/02 19:14:28 mycroft Exp $ */ 3 4 /* 5 * Copyright (c) 2003 6 * Ichiro FUKUHARA <ichiro@ichiro.org>. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Ichiro FUKUHARA. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 /* 38 * CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 #include <sys/gpio.h> 51 52 #include <machine/endian.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #ifdef INET 59 #include <netinet/in.h> 60 #include <netinet/if_ether.h> 61 #endif 62 63 #include <net80211/ieee80211_var.h> 64 #include <net80211/ieee80211_rssadapt.h> 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/gpio/gpiovar.h> 70 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcidevs.h> 74 75 #include <dev/cardbus/cardbusvar.h> 76 77 #include <dev/ic/athvar.h> 78 79 /* 80 * PCI configuration space registers 81 */ 82 #define ATH_PCI_MMBA 0x10 /* memory mapped base */ 83 84 struct ath_cardbus_softc { 85 struct ath_softc sc_ath; 86 87 /* CardBus-specific goo. */ 88 void *sc_ih; /* interrupt handle */ 89 cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */ 90 pcitag_t sc_tag; /* our CardBus tag */ 91 92 pcireg_t sc_bar_val; /* value of the BAR */ 93 94 int sc_intrline; /* interrupt line */ 95 pci_chipset_tag_t sc_pc; 96 }; 97 98 int ath_cardbus_match(struct device *, void *, void *); 99 void ath_cardbus_attach(struct device *, struct device *, void *); 100 int ath_cardbus_detach(struct device *, int); 101 102 struct cfattach ath_cardbus_ca = { 103 sizeof(struct ath_cardbus_softc), 104 ath_cardbus_match, 105 ath_cardbus_attach, 106 ath_cardbus_detach 107 }; 108 109 110 void ath_cardbus_setup(struct ath_cardbus_softc *); 111 112 int ath_cardbus_enable(struct ath_softc *); 113 void ath_cardbus_disable(struct ath_softc *); 114 void ath_cardbus_power(struct ath_softc *, int); 115 116 int 117 ath_cardbus_match(struct device *parent, void *match, void *aux) 118 { 119 struct cardbus_attach_args *ca = aux; 120 const char* devname; 121 122 devname = ath_hal_probe(PCI_VENDOR(ca->ca_id), 123 PCI_PRODUCT(ca->ca_id)); 124 125 if (devname) 126 return (1); 127 128 return (0); 129 } 130 131 void 132 ath_cardbus_attach(struct device *parent, struct device *self, void *aux) 133 { 134 struct ath_cardbus_softc *csc = (void *)self; 135 struct ath_softc *sc = &csc->sc_ath; 136 struct cardbus_attach_args *ca = aux; 137 cardbus_devfunc_t ct = ca->ca_ct; 138 bus_addr_t adr; 139 140 sc->sc_dmat = ca->ca_dmat; 141 csc->sc_ct = ct; 142 csc->sc_tag = ca->ca_tag; 143 csc->sc_pc = ca->ca_pc; 144 145 /* 146 * Power management hooks. 147 */ 148 sc->sc_enable = ath_cardbus_enable; 149 sc->sc_disable = ath_cardbus_disable; 150 sc->sc_power = ath_cardbus_power; 151 152 /* 153 * Map the device. 154 */ 155 if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0, 156 &sc->sc_st, &sc->sc_sh, &adr, &sc->sc_ss) == 0) { 157 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM; 158 } 159 160 else { 161 printf(": unable to map device registers\n"); 162 return; 163 } 164 165 /* 166 * Set up the PCI configuration registers. 167 */ 168 ath_cardbus_setup(csc); 169 170 /* Remember which interrupt line. */ 171 csc->sc_intrline = ca->ca_intrline; 172 173 printf(": irq %d\n", csc->sc_intrline); 174 175 /* 176 * Finish off the attach. 177 */ 178 ath_attach(PCI_PRODUCT(ca->ca_id), sc); 179 180 /* 181 * Power down the socket. 182 */ 183 Cardbus_function_disable(csc->sc_ct); 184 } 185 186 int 187 ath_cardbus_detach(struct device *self, int flags) 188 { 189 struct ath_cardbus_softc *csc = (void *)self; 190 struct ath_softc *sc = &csc->sc_ath; 191 struct cardbus_devfunc *ct = csc->sc_ct; 192 int rv; 193 194 #if defined(DIAGNOSTIC) 195 if (ct == NULL) 196 panic("%s: data structure lacks", sc->sc_dev.dv_xname); 197 #endif 198 199 rv = ath_detach(sc, flags); 200 if (rv) 201 return (rv); 202 203 /* 204 * Unhook the interrupt handler. 205 */ 206 if (csc->sc_ih != NULL) { 207 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih); 208 csc->sc_ih = NULL; 209 } 210 211 /* 212 * Release bus space and close window. 213 */ 214 Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA, 215 sc->sc_st, sc->sc_sh, sc->sc_ss); 216 217 return (0); 218 } 219 220 int 221 ath_cardbus_enable(struct ath_softc *sc) 222 { 223 struct ath_cardbus_softc *csc = (void *) sc; 224 cardbus_devfunc_t ct = csc->sc_ct; 225 cardbus_chipset_tag_t cc = ct->ct_cc; 226 cardbus_function_tag_t cf = ct->ct_cf; 227 228 /* 229 * Power on the socket. 230 */ 231 Cardbus_function_enable(ct); 232 233 /* 234 * Set up the PCI configuration registers. 235 */ 236 ath_cardbus_setup(csc); 237 238 /* 239 * Map and establish the interrupt. 240 */ 241 csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET, 242 ath_intr, sc, sc->sc_dev.dv_xname); 243 if (csc->sc_ih == NULL) { 244 printf(": unable to establish irq %d\n", 245 csc->sc_intrline); 246 Cardbus_function_disable(csc->sc_ct); 247 return (1); 248 } 249 return (0); 250 } 251 252 void 253 ath_cardbus_disable(struct ath_softc *sc) 254 { 255 struct ath_cardbus_softc *csc = (void *) sc; 256 cardbus_devfunc_t ct = csc->sc_ct; 257 cardbus_chipset_tag_t cc = ct->ct_cc; 258 cardbus_function_tag_t cf = ct->ct_cf; 259 260 /* Unhook the interrupt handler. */ 261 cardbus_intr_disestablish(cc, cf, csc->sc_ih); 262 csc->sc_ih = NULL; 263 264 /* Power down the socket. */ 265 Cardbus_function_disable(ct); 266 } 267 268 void 269 ath_cardbus_power(struct ath_softc *sc, int why) 270 { 271 if (why == PWR_RESUME) 272 ath_enable(sc); 273 } 274 275 void 276 ath_cardbus_setup(struct ath_cardbus_softc *csc) 277 { 278 cardbus_devfunc_t ct = csc->sc_ct; 279 cardbus_chipset_tag_t cc = ct->ct_cc; 280 pci_chipset_tag_t pc = csc->sc_pc; 281 pcireg_t reg; 282 283 #ifdef notyet 284 (void)cardbus_setpowerstate(sc->sc_dev.dv_xname, ct, csc->sc_tag, 285 PCI_PWR_D0); 286 #endif 287 288 /* Program the BAR. */ 289 pci_conf_write(pc, csc->sc_tag, ATH_PCI_MMBA, 290 csc->sc_bar_val); 291 292 /* Make sure the right access type is on the CardBus bridge. */ 293 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE); 294 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); 295 296 /* Enable the appropriate bits in the PCI CSR. */ 297 reg = pci_conf_read(pc, csc->sc_tag, 298 PCI_COMMAND_STATUS_REG); 299 reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 300 pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG, 301 reg); 302 303 /* 304 * Make sure the latency timer is set to some reasonable 305 * value. 306 */ 307 reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG); 308 if (PCI_LATTIMER(reg) < 0x20) { 309 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 310 reg |= (0x20 << PCI_LATTIMER_SHIFT); 311 pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg); 312 } 313 } 314