xref: /openbsd/sys/dev/cardbus/if_dc_cardbus.c (revision 8932bfb7)
1 /*	$OpenBSD: if_dc_cardbus.c,v 1.35 2011/04/02 17:47:04 jasper Exp $	*/
2 
3 /*
4  * Copyright (c) 1997, 1998, 1999
5  *	Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *      This product includes software developed by Bill Paul.
18  * 4. Neither the name of the author nor the names of any co-contributors
19  *    may be used to endorse or promote products derived from this software
20  *    without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32  * THE POSSIBILITY OF SUCH DAMAGE.
33  *
34  * $FreeBSD: src/sys/pci/if_dc.c,v 1.5 2000/01/12 22:24:05 wpaul Exp $
35  */
36 
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/mbuf.h>
40 #include <sys/socket.h>
41 #include <sys/ioctl.h>
42 #include <sys/errno.h>
43 #include <sys/malloc.h>
44 #include <sys/kernel.h>
45 #include <sys/proc.h>
46 #include <sys/device.h>
47 
48 #include <net/if.h>
49 #include <net/if_dl.h>
50 #include <net/if_types.h>
51 #include <net/if_media.h>
52 
53 #include <netinet/in.h>
54 #include <netinet/if_ether.h>
55 
56 #include <dev/mii/mii.h>
57 #include <dev/mii/miivar.h>
58 
59 #include <machine/bus.h>
60 
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcidevs.h>
64 
65 #include <dev/cardbus/cardbusvar.h>
66 
67 #include <dev/ic/dcreg.h>
68 
69 /* PCI configuration regs */
70 #define	PCI_CBIO	0x10
71 #define	PCI_CBMEM	0x14
72 #define	PCI_CFDA	0x40
73 
74 #define	DC_CFDA_SUSPEND	0x80000000
75 #define	DC_CFDA_STANDBY	0x40000000
76 
77 struct dc_cardbus_softc {
78 	struct dc_softc		sc_dc;
79 	int			sc_intrline;
80 
81 	cardbus_devfunc_t	sc_ct;
82 	pci_chipset_tag_t	sc_pc;
83 	pcitag_t		sc_tag;
84 	bus_size_t		sc_mapsize;
85 	int			sc_actype;
86 };
87 
88 int dc_cardbus_match(struct device *, void *, void *);
89 void dc_cardbus_attach(struct device *, struct device *,void *);
90 int dc_cardbus_detach(struct device *, int);
91 
92 void dc_cardbus_setup(struct dc_cardbus_softc *csc);
93 
94 struct cfattach dc_cardbus_ca = {
95 	sizeof(struct dc_cardbus_softc), dc_cardbus_match, dc_cardbus_attach,
96 	dc_cardbus_detach, dc_activate
97 };
98 
99 const struct pci_matchid dc_cardbus_devices[] = {
100 	{ PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21142 },
101 	{ PCI_VENDOR_XIRCOM, PCI_PRODUCT_XIRCOM_X3201_3_21143 },
102 	{ PCI_VENDOR_ADMTEK, PCI_PRODUCT_ADMTEK_AN985 },
103 	{ PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_EN2242 },
104 	{ PCI_VENDOR_ABOCOM, PCI_PRODUCT_ABOCOM_FE2500 },
105 	{ PCI_VENDOR_ABOCOM, PCI_PRODUCT_ABOCOM_FE2500MX },
106 	{ PCI_VENDOR_ABOCOM, PCI_PRODUCT_ABOCOM_PCM200 },
107 	{ PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DRP32TXD },
108 	{ PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_PCMPC200 },
109 	{ PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_PCM200 },
110 	{ PCI_VENDOR_HAWKING, PCI_PRODUCT_HAWKING_PN672TX },
111 	{ PCI_VENDOR_MICROSOFT, PCI_PRODUCT_MICROSOFT_MN120 },
112 };
113 
114 int
115 dc_cardbus_match(struct device *parent, void *match, void *aux)
116 {
117 	return (cardbus_matchbyid((struct cardbus_attach_args *)aux,
118 	    dc_cardbus_devices, nitems(dc_cardbus_devices)));
119 }
120 
121 void
122 dc_cardbus_attach(struct device *parent, struct device *self, void *aux)
123 {
124 	struct dc_cardbus_softc *csc = (struct dc_cardbus_softc *)self;
125 	struct dc_softc *sc = &csc->sc_dc;
126 	struct cardbus_attach_args *ca = aux;
127 	struct cardbus_devfunc *ct = ca->ca_ct;
128 	cardbus_chipset_tag_t cc = ct->ct_cc;
129 	pci_chipset_tag_t pc = ca->ca_pc;
130 	cardbus_function_tag_t cf = ct->ct_cf;
131 	pcireg_t reg;
132 	bus_addr_t addr;
133 
134 	sc->sc_dmat = ca->ca_dmat;
135 	csc->sc_ct = ct;
136 	csc->sc_tag = ca->ca_tag;
137 	csc->sc_pc = ca->ca_pc;
138 
139 	Cardbus_function_enable(ct);
140 
141 	if (Cardbus_mapreg_map(ct, PCI_CBIO,
142 	    PCI_MAPREG_TYPE_IO, 0, &sc->dc_btag, &sc->dc_bhandle, &addr,
143 	    &csc->sc_mapsize) == 0) {
144 
145 		csc->sc_actype = CARDBUS_IO_ENABLE;
146 	} else if (Cardbus_mapreg_map(ct, PCI_CBMEM,
147 	    PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
148 	    &sc->dc_btag, &sc->dc_bhandle, &addr, &csc->sc_mapsize) == 0) {
149 		csc->sc_actype = CARDBUS_MEM_ENABLE;
150 	} else {
151 		printf(": can't map device registers\n");
152 		return;
153 	}
154 
155 	csc->sc_intrline = ca->ca_intrline;
156 
157 	sc->dc_cachesize = pci_conf_read(csc->sc_pc, ca->ca_tag, DC_PCI_CFLT)
158 	    & 0xFF;
159 
160 	dc_cardbus_setup(csc);
161 
162 	/* Get the eeprom width */
163 	if ((PCI_VENDOR(ca->ca_id) == PCI_VENDOR_XIRCOM &&
164 	      PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_XIRCOM_X3201_3_21143))
165 		;	/* XIRCOM has non-standard eeprom */
166 	else
167 		dc_eeprom_width(sc);
168 
169 	switch (PCI_VENDOR(ca->ca_id)) {
170 	case PCI_VENDOR_DEC:
171 		if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21142) {
172 			sc->dc_type = DC_TYPE_21143;
173 			sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
174 			sc->dc_flags |= DC_REDUCED_MII_POLL;
175 			dc_read_srom(sc, sc->dc_romwidth);
176 			dc_parse_21143_srom(sc);
177 		}
178 		break;
179 	case PCI_VENDOR_XIRCOM:
180 		if (PCI_PRODUCT(ca->ca_id) ==
181 		    PCI_PRODUCT_XIRCOM_X3201_3_21143) {
182 			sc->dc_type = DC_TYPE_XIRCOM;
183 			sc->dc_flags |= DC_TX_INTR_ALWAYS|DC_TX_COALESCE |
184 					DC_TX_ALIGN;
185 			sc->dc_pmode = DC_PMODE_MII;
186 		}
187 		break;
188 	case PCI_VENDOR_ADMTEK:
189 	case PCI_VENDOR_ACCTON:
190 	case PCI_VENDOR_ABOCOM:
191 	case PCI_VENDOR_DLINK:
192 	case PCI_VENDOR_LINKSYS:
193 	case PCI_VENDOR_HAWKING:
194 	case PCI_VENDOR_MICROSOFT:
195 		if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ADMTEK_AN985 ||
196 		    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ACCTON_EN2242 ||
197 		    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_FE2500 ||
198 		    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_FE2500MX ||
199 		    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_PCM200 ||
200 		    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DLINK_DRP32TXD ||
201 		    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_LINKSYS_PCMPC200 ||
202 		    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_LINKSYS_PCM200 ||
203 		    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_HAWKING_PN672TX ||
204 		    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_MICROSOFT_MN120) {
205 			sc->dc_type = DC_TYPE_AN983;
206 			sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_ADMTEK_WAR |
207 					DC_64BIT_HASH;
208 			sc->dc_pmode = DC_PMODE_MII;
209 			/* Don't read SROM for - auto-loaded on reset */
210 		}
211 		break;
212 	default:
213 		printf(": unknown device\n");
214 		return;
215 	}
216 
217  	/*
218 	 * set latency timer, do we really need this?
219 	 */
220 	reg = pci_conf_read(pc, ca->ca_tag, PCI_BHLC_REG);
221 	if (PCI_LATTIMER(reg) < 0x20) {
222 		reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
223 		reg |= (0x20 << PCI_LATTIMER_SHIFT);
224 		pci_conf_write(pc, ca->ca_tag, PCI_BHLC_REG, reg);
225 	}
226 
227 	sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_NET,
228 	    dc_intr, csc, sc->sc_dev.dv_xname);
229 	if (sc->sc_ih == NULL) {
230 		printf(": can't establish interrupt at %d\n",
231 		    ca->ca_intrline);
232 		return;
233 	}
234 	printf(": irq %d", ca->ca_intrline);
235 
236 	dc_reset(sc);
237 
238 	sc->dc_revision = PCI_REVISION(ca->ca_class);
239 	dc_attach(sc);
240 }
241 
242 int
243 dc_cardbus_detach(struct device *self, int flags)
244 {
245 	struct dc_cardbus_softc *csc = (struct dc_cardbus_softc *)self;
246 	struct dc_softc *sc = &csc->sc_dc;
247 	struct cardbus_devfunc *ct = csc->sc_ct;
248 
249 	cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih);
250 	dc_detach(sc);
251 
252 	/* unmap cardbus resources */
253 	Cardbus_mapreg_unmap(ct,
254 	    csc->sc_actype == CARDBUS_IO_ENABLE ? PCI_CBIO : PCI_CBMEM,
255 	    sc->dc_btag, sc->dc_bhandle, csc->sc_mapsize);
256 
257 	return (0);
258 }
259 
260 void
261 dc_cardbus_setup(struct dc_cardbus_softc *csc)
262 {
263 	cardbus_devfunc_t ct = csc->sc_ct;
264 	cardbus_chipset_tag_t cc = ct->ct_cc;
265 	pci_chipset_tag_t pc = csc->sc_pc;
266 	pcireg_t reg;
267 	int r;
268 
269 	/* wakeup the card if needed */
270 	reg = pci_conf_read(pc, csc->sc_tag, PCI_CFDA);
271 	if (reg | (DC_CFDA_SUSPEND|DC_CFDA_STANDBY)) {
272 		pci_conf_write(pc, csc->sc_tag, PCI_CFDA,
273 		    reg & ~(DC_CFDA_SUSPEND|DC_CFDA_STANDBY));
274 	}
275 
276 	if (pci_get_capability(csc->sc_pc, csc->sc_tag, PCI_CAP_PWRMGMT, &r,
277 	    0)) {
278 		r = pci_conf_read(csc->sc_pc, csc->sc_tag, r + 4) & 3;
279 		if (r) {
280 			printf("%s: awakening from state D%d\n",
281 			    csc->sc_dc.sc_dev.dv_xname, r);
282 			pci_conf_write(csc->sc_pc, csc->sc_tag, r + 4, 0);
283 		}
284 	}
285 
286 	(*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_actype);
287 	(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
288 
289 	reg = pci_conf_read(csc->sc_pc, csc->sc_tag, PCI_COMMAND_STATUS_REG);
290 	reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
291 	    PCI_COMMAND_MASTER_ENABLE;
292 	pci_conf_write(csc->sc_pc, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
293 	reg = pci_conf_read(csc->sc_pc, csc->sc_tag, PCI_COMMAND_STATUS_REG);
294 }
295