1 /* $OpenBSD: amlpciephy.c,v 1.2 2020/03/26 12:58:18 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2019 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/systm.h> 20 #include <sys/device.h> 21 22 #include <machine/intr.h> 23 #include <machine/bus.h> 24 #include <machine/fdt.h> 25 26 #include <dev/ofw/openfirm.h> 27 #include <dev/ofw/ofw_clock.h> 28 #include <dev/ofw/ofw_misc.h> 29 #include <dev/ofw/fdt.h> 30 31 #define PHY_R0 0x00 32 #define PHY_R0_MODE_MASK (0x3 << 5) 33 #define PHY_R0_MODE_USB3 (0x3 << 5) 34 #define PHY_R4 0x10 35 #define PHY_R4_PHY_CR_WRITE (1 << 0) 36 #define PHY_R4_PHY_CR_READ (1 << 1) 37 #define PHY_R4_PHY_CR_CAP_DATA (1 << 18) 38 #define PHY_R4_PHY_CR_CAP_ADDR (1 << 19) 39 #define PHY_R5 0x14 40 #define PHY_R5_PHY_CR_ACK (1 << 16) 41 42 #define HREAD4(sc, reg) \ 43 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 44 #define HWRITE4(sc, reg, val) \ 45 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 46 #define HSET4(sc, reg, bits) \ 47 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 48 #define HCLR4(sc, reg, bits) \ 49 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 50 51 struct amlpciephy_softc { 52 struct device sc_dev; 53 bus_space_tag_t sc_iot; 54 bus_space_handle_t sc_ioh; 55 56 struct phy_device sc_pd; 57 }; 58 59 int amlpciephy_match(struct device *, void *, void *); 60 void amlpciephy_attach(struct device *, struct device *, void *); 61 62 struct cfattach amlpciephy_ca = { 63 sizeof (struct amlpciephy_softc), amlpciephy_match, amlpciephy_attach 64 }; 65 66 struct cfdriver amlpciephy_cd = { 67 NULL, "amlpciephy", DV_DULL 68 }; 69 70 int amlpciephy_enable(void *, uint32_t *); 71 uint16_t amlpciephy_read(struct amlpciephy_softc *, bus_addr_t); 72 void amlpciephy_write(struct amlpciephy_softc *, bus_addr_t, uint16_t); 73 74 int 75 amlpciephy_match(struct device *parent, void *match, void *aux) 76 { 77 struct fdt_attach_args *faa = aux; 78 79 return OF_is_compatible(faa->fa_node, "amlogic,g12a-usb3-pcie-phy"); 80 } 81 82 void 83 amlpciephy_attach(struct device *parent, struct device *self, void *aux) 84 { 85 struct amlpciephy_softc *sc = (struct amlpciephy_softc *)self; 86 struct fdt_attach_args *faa = aux; 87 88 if (faa->fa_nreg < 1) { 89 printf(": no registers\n"); 90 return; 91 } 92 93 sc->sc_iot = faa->fa_iot; 94 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 95 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 96 printf(": can't map registers\n"); 97 return; 98 } 99 100 printf("\n"); 101 102 sc->sc_pd.pd_node = faa->fa_node; 103 sc->sc_pd.pd_cookie = sc; 104 sc->sc_pd.pd_enable = amlpciephy_enable; 105 phy_register(&sc->sc_pd); 106 } 107 108 int 109 amlpciephy_enable(void *cookie, uint32_t *cells) 110 { 111 struct amlpciephy_softc *sc = cookie; 112 int node = sc->sc_pd.pd_node; 113 uint32_t type = cells[0]; 114 uint32_t reg; 115 116 /* 117 * Hardware can be switched between PCIe 2.0 and USB 3.0 mode, 118 * but we only support USB for now. 119 */ 120 if (type != PHY_TYPE_USB3) 121 return -1; 122 123 clock_set_assigned(node); 124 clock_enable_all(node); 125 reset_assert_all(node); 126 delay(10); 127 reset_deassert_all(node); 128 129 /* Switch to USB 3.0 mode. */ 130 reg = HREAD4(sc, PHY_R0); 131 reg &= ~PHY_R0_MODE_MASK; 132 reg |= PHY_R0_MODE_USB3; 133 HWRITE4(sc, PHY_R0, reg); 134 135 /* Workaround for SuperSpeed PHY suspend bug. */ 136 reg = amlpciephy_read(sc, 0x102d); 137 reg |= (1 << 7); 138 amlpciephy_write(sc, 0x102d, reg); 139 140 reg = amlpciephy_read(sc, 0x1010); 141 reg &= ~0xff0; 142 reg |= 0x10; 143 amlpciephy_write(sc, 0x1010, reg); 144 145 /* Rx equalization magic. */ 146 reg = amlpciephy_read(sc, 0x1006); 147 reg &= (1 << 6); 148 reg |= (1 << 7); 149 reg &= ~(0x7 << 8); 150 reg |= (0x3 << 8); 151 reg |= (1 << 11); 152 amlpciephy_write(sc, 0x1006, reg); 153 154 /* Tx equalization magic. */ 155 reg = amlpciephy_read(sc, 0x1002); 156 reg &= ~0x3f80; 157 reg |= (0x16 << 7); 158 reg &= ~0x7f; 159 reg |= (0x7f | (1 << 14)); 160 amlpciephy_write(sc, 0x1002, reg); 161 162 /* MPLL loop magic. */ 163 reg = amlpciephy_read(sc, 0x30); 164 reg &= ~(0xf << 4); 165 reg |= (8 << 4); 166 amlpciephy_write(sc, 0x30, reg); 167 168 return 0; 169 } 170 171 void 172 amlpciephy_addr(struct amlpciephy_softc *sc, bus_addr_t addr) 173 { 174 int timo; 175 176 HWRITE4(sc, PHY_R4, addr << 2); 177 HWRITE4(sc, PHY_R4, addr << 2); 178 HWRITE4(sc, PHY_R4, (addr << 2) | PHY_R4_PHY_CR_CAP_ADDR); 179 for (timo = 200; timo > 0; timo--) { 180 if (HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) 181 break; 182 delay(5); 183 } 184 if (timo == 0) { 185 printf("%s: timeout\n", __func__); 186 return; 187 } 188 HWRITE4(sc, PHY_R4, addr << 2); 189 for (timo = 200; timo > 0; timo--) { 190 if ((HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) == 0) 191 break; 192 delay(5); 193 } 194 if (timo == 0) { 195 printf("%s: timeout\n", __func__); 196 return; 197 } 198 } 199 200 uint16_t 201 amlpciephy_read(struct amlpciephy_softc *sc, bus_addr_t addr) 202 { 203 uint32_t reg; 204 int timo; 205 206 amlpciephy_addr(sc, addr); 207 HWRITE4(sc, PHY_R4, 0); 208 HWRITE4(sc, PHY_R4, PHY_R4_PHY_CR_READ); 209 for (timo = 200; timo > 0; timo--) { 210 if (HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) 211 break; 212 delay(5); 213 } 214 if (timo == 0) { 215 printf("%s: timeout\n", __func__); 216 return 0; 217 } 218 reg = HREAD4(sc, PHY_R5); 219 HWRITE4(sc, PHY_R4, 0); 220 for (timo = 200; timo > 0; timo--) { 221 if ((HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) == 0) 222 break; 223 delay(5); 224 } 225 if (timo == 0) { 226 printf("%s: timeout\n", __func__); 227 return 0; 228 } 229 return reg; 230 } 231 232 void 233 amlpciephy_write(struct amlpciephy_softc *sc, bus_addr_t addr, uint16_t data) 234 { 235 int timo; 236 237 amlpciephy_addr(sc, addr); 238 HWRITE4(sc, PHY_R4, data << 2); 239 HWRITE4(sc, PHY_R4, data << 2); 240 HWRITE4(sc, PHY_R4, data << 2 | PHY_R4_PHY_CR_CAP_DATA); 241 for (timo = 200; timo > 0; timo--) { 242 if (HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) 243 break; 244 delay(5); 245 } 246 if (timo == 0) { 247 printf("%s: timeout\n", __func__); 248 return; 249 } 250 HWRITE4(sc, PHY_R4, data << 2); 251 for (timo = 200; timo > 0; timo--) { 252 if ((HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) == 0) 253 break; 254 delay(5); 255 } 256 if (timo == 0) { 257 printf("%s: timeout\n", __func__); 258 return; 259 } 260 261 HWRITE4(sc, PHY_R4, data << 2); 262 HWRITE4(sc, PHY_R4, data << 2 | PHY_R4_PHY_CR_WRITE); 263 for (timo = 200; timo > 0; timo--) { 264 if (HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) 265 break; 266 delay(5); 267 } 268 if (timo == 0) { 269 printf("%s: timeout\n", __func__); 270 return; 271 } 272 HWRITE4(sc, PHY_R4, data << 2); 273 for (timo = 200; timo > 0; timo--) { 274 if ((HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) == 0) 275 break; 276 delay(5); 277 } 278 if (timo == 0) { 279 printf("%s: timeout\n", __func__); 280 return; 281 } 282 } 283