1 /* $OpenBSD: amlpwm.c,v 1.1 2019/09/30 20:42:45 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2019 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/systm.h> 20 #include <sys/device.h> 21 22 #include <machine/intr.h> 23 #include <machine/bus.h> 24 #include <machine/fdt.h> 25 26 #include <dev/ofw/openfirm.h> 27 #include <dev/ofw/ofw_clock.h> 28 #include <dev/ofw/ofw_misc.h> 29 #include <dev/ofw/fdt.h> 30 31 #define PWM_PWM_A 0x00 32 #define PWM_PWM_B 0x01 33 #define PWM_PWM_HIGH(x) ((x) >> 16) 34 #define PWM_PWM_HIGH_SHIFT 16 35 #define PWM_PWM_LOW(x) ((x) & 0xffff) 36 #define PWM_PWM_LOW_SHIFT 0 37 #define PWM_MISC_REG_AB 0x02 38 #define PWM_B_CLK_EN (1 << 23) 39 #define PWM_B_CLK_DIV_MASK (0x7f << 16) 40 #define PWM_B_CLK_DIV_SHIFT 16 41 #define PWM_B_CLK_DIV(x) ((((x) >> 16) & 0x7f) + 1) 42 #define PWM_A_CLK_EN (1 << 15) 43 #define PWM_A_CLK_DIV_MASK (0x7f << 8) 44 #define PWM_A_CLK_DIV_SHIFT 8 45 #define PWM_A_CLK_DIV(x) ((((x) >> 8) & 0x7f) + 1) 46 #define PWM_B_EN (1 << 1) 47 #define PWM_A_EN (1 << 0) 48 49 #define HREAD4(sc, reg) \ 50 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg) << 2)) 51 #define HWRITE4(sc, reg, val) \ 52 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg) << 2, (val)) 53 #define HSET4(sc, reg, bits) \ 54 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 55 #define HCLR4(sc, reg, bits) \ 56 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 57 58 struct amlpwm_softc { 59 struct device sc_dev; 60 bus_space_tag_t sc_iot; 61 bus_space_handle_t sc_ioh; 62 63 uint32_t sc_clkin[2]; 64 65 struct pwm_device sc_pd; 66 }; 67 68 int amlpwm_match(struct device *, void *, void *); 69 void amlpwm_attach(struct device *, struct device *, void *); 70 71 struct cfattach amlpwm_ca = { 72 sizeof (struct amlpwm_softc), amlpwm_match, amlpwm_attach 73 }; 74 75 struct cfdriver amlpwm_cd = { 76 NULL, "amlpwm", DV_DULL 77 }; 78 79 int amlpwm_get_state(void *, uint32_t *, struct pwm_state *); 80 int amlpwm_set_state(void *, uint32_t *, struct pwm_state *); 81 82 int 83 amlpwm_match(struct device *parent, void *match, void *aux) 84 { 85 struct fdt_attach_args *faa = aux; 86 int node = faa->fa_node; 87 88 return (OF_is_compatible(node, "amlogic,meson-g12a-ao-pwm-cd") || 89 OF_is_compatible(node, "amlogic,meson-g12a-ee-pwm")); 90 } 91 92 void 93 amlpwm_attach(struct device *parent, struct device *self, void *aux) 94 { 95 struct amlpwm_softc *sc = (struct amlpwm_softc *)self; 96 struct fdt_attach_args *faa = aux; 97 98 if (faa->fa_nreg < 1) { 99 printf(": no registers\n"); 100 return; 101 } 102 103 sc->sc_iot = faa->fa_iot; 104 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 105 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 106 printf(": can't map registers\n"); 107 return; 108 } 109 110 sc->sc_clkin[0] = clock_get_frequency(faa->fa_node, "clkin0"); 111 sc->sc_clkin[1] = clock_get_frequency(faa->fa_node, "clkin1"); 112 113 printf("\n"); 114 115 sc->sc_pd.pd_node = faa->fa_node; 116 sc->sc_pd.pd_cookie = sc; 117 sc->sc_pd.pd_get_state = amlpwm_get_state; 118 sc->sc_pd.pd_set_state = amlpwm_set_state; 119 pwm_register(&sc->sc_pd); 120 } 121 122 static inline uint32_t 123 cycles_to_ns(uint64_t clk_freq, uint32_t clk_div, uint32_t cycles) 124 { 125 return cycles * clk_div * 1000000000ULL / clk_freq; 126 } 127 128 static inline uint32_t 129 ns_to_cycles(uint64_t clk_freq, uint32_t clk_div, uint32_t ns) 130 { 131 return ns * clk_freq / (clk_div * 1000000000ULL); 132 } 133 134 int 135 amlpwm_get_state(void *cookie, uint32_t *cells, struct pwm_state *ps) 136 { 137 struct amlpwm_softc *sc = cookie; 138 uint32_t idx = cells[0]; 139 uint32_t pwm, misc; 140 uint32_t total, high; 141 uint32_t clk_div; 142 int enabled = 0; 143 144 if (idx > 1 || sc->sc_clkin[idx] == 0) 145 return EINVAL; 146 147 pwm = HREAD4(sc, idx == 0 ? PWM_PWM_A : PWM_PWM_B); 148 misc = HREAD4(sc, PWM_MISC_REG_AB); 149 150 if (idx == 0) { 151 if ((misc & PWM_A_CLK_EN) && (misc & PWM_A_EN)) 152 enabled = 1; 153 clk_div = PWM_A_CLK_DIV(misc); 154 } else { 155 if ((misc & PWM_B_CLK_EN) && (misc & PWM_B_EN)) 156 enabled = 1; 157 clk_div = PWM_B_CLK_DIV(misc); 158 } 159 160 total = PWM_PWM_LOW(pwm) + PWM_PWM_HIGH(pwm); 161 high = PWM_PWM_HIGH(pwm); 162 163 memset(ps, 0, sizeof(struct pwm_state)); 164 ps->ps_period = cycles_to_ns(sc->sc_clkin[idx], clk_div, total); 165 ps->ps_pulse_width = cycles_to_ns(sc->sc_clkin[idx], clk_div, high); 166 ps->ps_enabled = enabled; 167 168 return 0; 169 } 170 171 int 172 amlpwm_set_state(void *cookie, uint32_t *cells, struct pwm_state *ps) 173 { 174 struct amlpwm_softc *sc = cookie; 175 uint32_t idx = cells[0]; 176 uint32_t pwm, misc; 177 uint32_t total, high, low; 178 uint32_t clk_div = 1; 179 180 if (idx > 1 || sc->sc_clkin[idx] == 0) 181 return EINVAL; 182 183 /* Hardware doesn't support polarity inversion. */ 184 if (ps->ps_flags & PWM_POLARITY_INVERTED) 185 return EINVAL; 186 187 if (!ps->ps_enabled) { 188 HCLR4(sc, PWM_MISC_REG_AB, (idx == 0) ? PWM_A_EN : PWM_B_EN); 189 return 0; 190 } 191 192 total = ns_to_cycles(sc->sc_clkin[idx], clk_div, ps->ps_period); 193 while ((total / clk_div) > 0xffff) 194 clk_div++; 195 if (clk_div > 128) 196 return EINVAL; 197 198 total = ns_to_cycles(sc->sc_clkin[idx], clk_div, ps->ps_period); 199 high = ns_to_cycles(sc->sc_clkin[idx], clk_div, ps->ps_pulse_width); 200 low = total - high; 201 202 pwm = (high << PWM_PWM_HIGH_SHIFT) | (low << PWM_PWM_LOW_SHIFT); 203 misc = HREAD4(sc, PWM_MISC_REG_AB); 204 205 if (idx == 0) { 206 misc &= ~PWM_A_CLK_DIV_MASK; 207 misc |= (clk_div - 1) << PWM_A_CLK_DIV_SHIFT; 208 misc |= PWM_A_CLK_EN; 209 } else { 210 misc &= ~PWM_B_CLK_DIV_MASK; 211 misc |= (clk_div - 1) << PWM_B_CLK_DIV_SHIFT; 212 misc |= PWM_B_CLK_EN; 213 } 214 215 HWRITE4(sc, PWM_MISC_REG_AB, misc); 216 HWRITE4(sc, (idx == 0) ? PWM_PWM_A : PWM_PWM_B, pwm); 217 HSET4(sc, PWM_MISC_REG_AB, (idx == 0) ? PWM_A_EN : PWM_B_EN); 218 219 return 0; 220 } 221