1 /* $OpenBSD: dwmmc.c,v 1.21 2019/09/20 20:46:15 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2017 Mark Kettenis 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/kernel.h> 20 #include <sys/malloc.h> 21 #include <sys/systm.h> 22 23 #include <machine/bus.h> 24 #include <machine/fdt.h> 25 #include <machine/intr.h> 26 27 #include <dev/ofw/openfirm.h> 28 #include <dev/ofw/ofw_clock.h> 29 #include <dev/ofw/ofw_gpio.h> 30 #include <dev/ofw/ofw_pinctrl.h> 31 #include <dev/ofw/fdt.h> 32 33 #include <dev/sdmmc/sdmmcvar.h> 34 #include <dev/sdmmc/sdmmc_ioreg.h> 35 36 #define SDMMC_CTRL 0x0000 37 #define SDMMC_CTRL_USE_INTERNAL_DMAC (1 << 25) 38 #define SDMMC_CTRL_DMA_ENABLE (1 << 5) 39 #define SDMMC_CTRL_INT_ENABLE (1 << 4) 40 #define SDMMC_CTRL_DMA_RESET (1 << 2) 41 #define SDMMC_CTRL_FIFO_RESET (1 << 1) 42 #define SDMMC_CTRL_CONTROLLER_RESET (1 << 0) 43 #define SDMMC_CTRL_ALL_RESET (SDMMC_CTRL_CONTROLLER_RESET | \ 44 SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 45 #define SDMMC_PWREN 0x0004 46 #define SDMMC_CLKDIV 0x0008 47 #define SDMMC_CLKSRC 0x000c 48 #define SDMMC_CLKENA 0x0010 49 #define SDMMC_CLKENA_CCLK_LOW_POWER (1 << 16) 50 #define SDMMC_CLKENA_CCLK_ENABLE (1 << 0) 51 #define SDMMC_TMOUT 0x0014 52 #define SDMMC_CTYPE 0x0018 53 #define SDMMC_CTYPE_8BIT (1 << 16) 54 #define SDMMC_CTYPE_4BIT (1 << 0) 55 #define SDMMC_BLKSIZ 0x001c 56 #define SDMMC_BYTCNT 0x0020 57 #define SDMMC_INTMASK 0x0024 58 #define SDMMC_CMDARG 0x0028 59 #define SDMMC_CMD 0x002c 60 #define SDMMC_CMD_START_CMD (1U << 31) 61 #define SDMMC_CMD_USE_HOLD_REG (1 << 29) 62 #define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY (1 << 21) 63 #define SDMMC_CMD_SEND_INITIALIZATION (1 << 15) 64 #define SDMMC_CMD_STOP_ABORT_CMD (1 << 14) 65 #define SDMMC_CMD_WAIT_PRVDATA_COMPLETE (1 << 13) 66 #define SDMMC_CMD_SEND_AUTO_STOP (1 << 12) 67 #define SDMMC_CMD_WR (1 << 10) 68 #define SDMMC_CMD_DATA_EXPECTED (1 << 9) 69 #define SDMMC_CMD_CHECK_REPONSE_CRC (1 << 8) 70 #define SDMMC_CMD_RESPONSE_LENGTH (1 << 7) 71 #define SDMMC_CMD_RESPONSE_EXPECT (1 << 6) 72 #define SDMMC_RESP0 0x0030 73 #define SDMMC_RESP1 0x0034 74 #define SDMMC_RESP2 0x0038 75 #define SDMMC_RESP3 0x003c 76 #define SDMMC_MINTSTS 0x0040 77 #define SDMMC_RINTSTS 0x0044 78 #define SDMMC_RINTSTS_SDIO (1 << 24) 79 #define SDMMC_RINTSTS_EBE (1 << 15) 80 #define SDMMC_RINTSTS_ACD (1 << 14) 81 #define SDMMC_RINTSTS_SBE (1 << 13) 82 #define SDMMC_RINTSTS_HLE (1 << 12) 83 #define SDMMC_RINTSTS_FRUN (1 << 11) 84 #define SDMMC_RINTSTS_HTO (1 << 10) 85 #define SDMMC_RINTSTS_DRTO (1 << 9) 86 #define SDMMC_RINTSTS_RTO (1 << 8) 87 #define SDMMC_RINTSTS_DCRC (1 << 7) 88 #define SDMMC_RINTSTS_RCRC (1 << 6) 89 #define SDMMC_RINTSTS_RXDR (1 << 5) 90 #define SDMMC_RINTSTS_TXDR (1 << 4) 91 #define SDMMC_RINTSTS_DTO (1 << 3) 92 #define SDMMC_RINTSTS_CD (1 << 2) 93 #define SDMMC_RINTSTS_RE (1 << 1) 94 #define SDMMC_RINTSTS_CDT (1 << 0) 95 #define SDMMC_RINTSTS_DATA_ERR (SDMMC_RINTSTS_EBE | SDMMC_RINTSTS_SBE | \ 96 SDMMC_RINTSTS_HLE | SDMMC_RINTSTS_FRUN | SDMMC_RINTSTS_DCRC) 97 #define SDMMC_RINTSTS_DATA_TO (SDMMC_RINTSTS_HTO | SDMMC_RINTSTS_DRTO) 98 #define SDMMC_STATUS 0x0048 99 #define SDMMC_STATUS_FIFO_COUNT(x) (((x) >> 17) & 0x1fff) 100 #define SDMMC_STATUS_DATA_BUSY (1 << 9) 101 #define SDMMC_FIFOTH 0x004c 102 #define SDMMC_FIFOTH_MSIZE_SHIFT 28 103 #define SDMMC_FIFOTH_RXWM_SHIFT 16 104 #define SDMMC_FIFOTH_RXWM(x) (((x) >> 16) & 0xfff) 105 #define SDMMC_FIFOTH_TXWM_SHIFT 0 106 #define SDMMC_CDETECT 0x0050 107 #define SDMMC_CDETECT_CARD_DETECT_0 (1 << 0) 108 #define SDMMC_WRTPRT 0x0054 109 #define SDMMC_TCBCNT 0x005c 110 #define SDMMC_TBBCNT 0x0060 111 #define SDMMC_DEBNCE 0x0064 112 #define SDMMC_USRID 0x0068 113 #define SDMMC_VERID 0x006c 114 #define SDMMC_HCON 0x0070 115 #define SDMMC_HCON_DATA_WIDTH(x) (((x) >> 7) & 0x7) 116 #define SDMMC_HCON_DMA64 (1 << 27) 117 #define SDMMC_UHS_REG 0x0074 118 #define SDMMC_RST_n 0x0078 119 #define SDMMC_BMOD 0x0080 120 #define SDMMC_BMOD_DE (1 << 7) 121 #define SDMMC_BMOD_FB (1 << 1) 122 #define SDMMC_BMOD_SWR (1 << 0) 123 #define SDMMC_PLDMND 0x0084 124 #define SDMMC_DBADDR 0x0088 125 #define SDMMC_IDSTS32 0x008c 126 #define SDMMC_IDSTS_NIS (1 << 8) 127 #define SDMMC_IDSTS_RI (1 << 1) 128 #define SDMMC_IDSTS_TI (1 << 0) 129 #define SDMMC_IDINTEN32 0x0090 130 #define SDMMC_IDINTEN_NI (1 << 8) 131 #define SDMMC_IDINTEN_RI (1 << 1) 132 #define SDMMC_IDINTEN_TI (1 << 0) 133 #define SDMMC_DSCADDR 0x0094 134 #define SDMMC_BUFADDR 0x0098 135 #define SDMMC_CLKSEL 0x009c 136 #define SDMMC_CARDTHRCTL 0x0100 137 #define SDMMC_CARDTHRCTL_RDTHR_SHIFT 16 138 #define SDMMC_CARDTHRCTL_RDTHREN (1 << 0) 139 #define SDMMC_BACK_END_POWER 0x0104 140 #define SDMMC_EMMC_DDR_REG 0x0108 141 #define SDMMC_FIFO_BASE 0x0200 142 143 #define SDMMC_DBADDRL 0x0088 144 #define SDMMC_DBADDRH 0x008c 145 #define SDMMC_IDSTS64 0x0090 146 #define SDMMC_IDINTEN64 0x0094 147 #define SDMMC_DSCADDRL 0x0098 148 #define SDMMC_DSCADDRH 0x009c 149 #define SDMMC_BUFADDRL 0x00a0 150 #define SDMMC_BUFADDRH 0x00a4 151 152 #define SDMMC_IDSTS(sc) \ 153 ((sc)->sc_dma64 ? SDMMC_IDSTS64 : SDMMC_IDSTS32) 154 155 #define HREAD4(sc, reg) \ 156 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 157 #define HWRITE4(sc, reg, val) \ 158 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 159 #define HSET4(sc, reg, bits) \ 160 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 161 #define HCLR4(sc, reg, bits) \ 162 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 163 164 struct dwmmc_desc32 { 165 uint32_t des[4]; 166 }; 167 168 struct dwmmc_desc64 { 169 uint32_t des[8]; 170 }; 171 172 #define DWMMC_NDESC (PAGE_SIZE / sizeof(struct dwmmc_desc64)) 173 #define DWMMC_MAXSEGSZ 0x1000 174 175 #define DES0_OWN (1U << 31) 176 #define DES0_CES (1 << 30) 177 #define DES0_ER (1 << 5) 178 #define DES0_CH (1 << 4) 179 #define DES0_FS (1 << 3) 180 #define DES0_LD (1 << 2) 181 #define DES0_DIC (1 << 1) 182 183 #define DES1_BS2(sz) (((sz) & 0x1fff) << 13) 184 #define DES1_BS1(sz) (((sz) & 0x1fff) << 0) 185 #define DES2_BS2(sz) DES1_BS2(sz) 186 #define DES2_BS1(sz) DES1_BS1(sz) 187 188 struct dwmmc_softc { 189 struct device sc_dev; 190 bus_space_tag_t sc_iot; 191 bus_space_handle_t sc_ioh; 192 bus_size_t sc_size; 193 bus_dma_tag_t sc_dmat; 194 bus_dmamap_t sc_dmap; 195 int sc_node; 196 197 void *sc_ih; 198 199 uint32_t sc_clkbase; 200 uint32_t sc_fifo_depth; 201 uint32_t sc_fifo_width; 202 void (*sc_read_data)(struct dwmmc_softc *, u_char *, int); 203 void (*sc_write_data)(struct dwmmc_softc *, u_char *, int); 204 int sc_blklen; 205 206 bus_dmamap_t sc_desc_map; 207 bus_dma_segment_t sc_desc_segs[1]; 208 caddr_t sc_desc; 209 int sc_dma64; 210 int sc_dmamode; 211 uint32_t sc_idsts; 212 213 uint32_t sc_gpio[4]; 214 int sc_sdio_irq; 215 uint32_t sc_pwrseq; 216 uint32_t sc_vdd; 217 218 struct device *sc_sdmmc; 219 }; 220 221 int dwmmc_match(struct device *, void *, void *); 222 void dwmmc_attach(struct device *, struct device *, void *); 223 224 struct cfattach dwmmc_ca = { 225 sizeof(struct dwmmc_softc), dwmmc_match, dwmmc_attach 226 }; 227 228 struct cfdriver dwmmc_cd = { 229 NULL, "dwmmc", DV_DULL 230 }; 231 232 int dwmmc_intr(void *); 233 234 int dwmmc_host_reset(sdmmc_chipset_handle_t); 235 uint32_t dwmmc_host_ocr(sdmmc_chipset_handle_t); 236 int dwmmc_host_maxblklen(sdmmc_chipset_handle_t); 237 int dwmmc_card_detect(sdmmc_chipset_handle_t); 238 int dwmmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 239 int dwmmc_bus_clock(sdmmc_chipset_handle_t, int, int); 240 int dwmmc_bus_width(sdmmc_chipset_handle_t, int); 241 void dwmmc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 242 void dwmmc_card_intr_mask(sdmmc_chipset_handle_t, int); 243 void dwmmc_card_intr_ack(sdmmc_chipset_handle_t); 244 245 struct sdmmc_chip_functions dwmmc_chip_functions = { 246 .host_reset = dwmmc_host_reset, 247 .host_ocr = dwmmc_host_ocr, 248 .host_maxblklen = dwmmc_host_maxblklen, 249 .card_detect = dwmmc_card_detect, 250 .bus_power = dwmmc_bus_power, 251 .bus_clock = dwmmc_bus_clock, 252 .bus_width = dwmmc_bus_width, 253 .exec_command = dwmmc_exec_command, 254 .card_intr_mask = dwmmc_card_intr_mask, 255 .card_intr_ack = dwmmc_card_intr_ack, 256 }; 257 258 void dwmmc_pio_mode(struct dwmmc_softc *); 259 int dwmmc_alloc_descriptors(struct dwmmc_softc *); 260 void dwmmc_init_descriptors(struct dwmmc_softc *); 261 void dwmmc_transfer_data(struct dwmmc_softc *, struct sdmmc_command *); 262 void dwmmc_read_data32(struct dwmmc_softc *, u_char *, int); 263 void dwmmc_write_data32(struct dwmmc_softc *, u_char *, int); 264 void dwmmc_read_data64(struct dwmmc_softc *, u_char *, int); 265 void dwmmc_write_data64(struct dwmmc_softc *, u_char *, int); 266 void dwmmc_pwrseq_pre(uint32_t); 267 void dwmmc_pwrseq_post(uint32_t); 268 269 int 270 dwmmc_match(struct device *parent, void *match, void *aux) 271 { 272 struct fdt_attach_args *faa = aux; 273 274 return (OF_is_compatible(faa->fa_node, "hisilicon,hi3660-dw-mshc") || 275 OF_is_compatible(faa->fa_node, "hisilicon,hi3670-dw-mshc") || 276 OF_is_compatible(faa->fa_node, "rockchip,rk3288-dw-mshc") || 277 OF_is_compatible(faa->fa_node, "samsung,exynos5420-dw-mshc")); 278 } 279 280 void 281 dwmmc_attach(struct device *parent, struct device *self, void *aux) 282 { 283 struct dwmmc_softc *sc = (struct dwmmc_softc *)self; 284 struct fdt_attach_args *faa = aux; 285 struct sdmmcbus_attach_args saa; 286 uint32_t freq = 0, div = 0; 287 uint32_t hcon, width; 288 uint32_t fifoth; 289 int error, timeout; 290 291 if (faa->fa_nreg < 1) { 292 printf(": no registers\n"); 293 return; 294 } 295 296 sc->sc_node = faa->fa_node; 297 sc->sc_iot = faa->fa_iot; 298 sc->sc_size = faa->fa_reg[0].size; 299 300 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 301 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 302 printf(": can't map registers\n"); 303 return; 304 } 305 306 pinctrl_byname(faa->fa_node, "default"); 307 308 clock_enable_all(faa->fa_node); 309 reset_deassert_all(faa->fa_node); 310 311 /* 312 * Determine FIFO width from hardware configuration register. 313 * We only support 32-bit and 64-bit FIFOs. 314 */ 315 hcon = HREAD4(sc, SDMMC_HCON); 316 switch (SDMMC_HCON_DATA_WIDTH(hcon)) { 317 case 1: 318 sc->sc_fifo_width = 4; 319 sc->sc_read_data = dwmmc_read_data32; 320 sc->sc_write_data = dwmmc_write_data32; 321 break; 322 case 2: 323 sc->sc_fifo_width = 8; 324 sc->sc_read_data = dwmmc_read_data64; 325 sc->sc_write_data = dwmmc_write_data64; 326 break; 327 default: 328 printf(": unsupported FIFO width\n"); 329 return; 330 } 331 332 sc->sc_fifo_depth = OF_getpropint(faa->fa_node, "fifo-depth", 0); 333 if (sc->sc_fifo_depth == 0) { 334 fifoth = HREAD4(sc, SDMMC_FIFOTH); 335 sc->sc_fifo_depth = SDMMC_FIFOTH_RXWM(fifoth) + 1; 336 } 337 338 if (hcon & SDMMC_HCON_DMA64) 339 sc->sc_dma64 = 1; 340 341 /* Some SoCs pre-divide the clock. */ 342 if (OF_is_compatible(faa->fa_node, "rockchip,rk3288-dw-mshc")) 343 div = 1; 344 if (OF_is_compatible(faa->fa_node, "hisilicon,hi3660-dw-mshc") || 345 OF_is_compatible(faa->fa_node, "hisilicon,hi3670-dw-mshc")) 346 div = 7; 347 348 /* Force the base clock to 50MHz on Rockchip SoCs. */ 349 if (OF_is_compatible(faa->fa_node, "rockchip,rk3288-dw-mshc")) 350 freq = 50000000; 351 352 freq = OF_getpropint(faa->fa_node, "clock-frequency", freq); 353 if (freq > 0) 354 clock_set_frequency(faa->fa_node, "ciu", (div + 1) * freq); 355 356 sc->sc_clkbase = clock_get_frequency(faa->fa_node, "ciu"); 357 div = OF_getpropint(faa->fa_node, "samsung,dw-mshc-ciu-div", div); 358 sc->sc_clkbase /= (div + 1); 359 360 sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_BIO, 361 dwmmc_intr, sc, sc->sc_dev.dv_xname); 362 if (sc->sc_ih == NULL) { 363 printf(": can't establish interrupt\n"); 364 goto unmap; 365 } 366 367 OF_getpropintarray(faa->fa_node, "cd-gpios", sc->sc_gpio, 368 sizeof(sc->sc_gpio)); 369 if (sc->sc_gpio[0]) 370 gpio_controller_config_pin(sc->sc_gpio, GPIO_CONFIG_INPUT); 371 372 sc->sc_sdio_irq = (OF_getproplen(sc->sc_node, "cap-sdio-irq") == 0); 373 sc->sc_pwrseq = OF_getpropint(sc->sc_node, "mmc-pwrseq", 0); 374 375 printf(": %d MHz base clock\n", sc->sc_clkbase / 1000000); 376 377 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_ALL_RESET); 378 for (timeout = 5000; timeout > 0; timeout--) { 379 if ((HREAD4(sc, SDMMC_CTRL) & SDMMC_CTRL_ALL_RESET) == 0) 380 break; 381 delay(100); 382 } 383 if (timeout == 0) 384 printf("%s: reset failed\n", sc->sc_dev.dv_xname); 385 386 /* Enable interrupts, but mask them all. */ 387 HWRITE4(sc, SDMMC_INTMASK, 0); 388 HWRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 389 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE); 390 391 dwmmc_bus_width(sc, 1); 392 393 /* Start out in non-DMA mode. */ 394 dwmmc_pio_mode(sc); 395 396 sc->sc_dmat = faa->fa_dmat; 397 dwmmc_alloc_descriptors(sc); 398 dwmmc_init_descriptors(sc); 399 400 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, DWMMC_NDESC, 401 DWMMC_MAXSEGSZ, 0, BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &sc->sc_dmap); 402 if (error) { 403 printf(": can't create DMA map\n"); 404 goto unmap; 405 } 406 407 memset(&saa, 0, sizeof(saa)); 408 saa.saa_busname = "sdmmc"; 409 saa.sct = &dwmmc_chip_functions; 410 saa.sch = sc; 411 saa.dmat = sc->sc_dmat; 412 saa.dmap = sc->sc_dmap; 413 saa.caps |= SMC_CAPS_DMA; 414 415 if (OF_getproplen(sc->sc_node, "cap-mmc-highspeed") == 0) 416 saa.caps |= SMC_CAPS_MMC_HIGHSPEED; 417 if (OF_getproplen(sc->sc_node, "cap-sd-highspeed") == 0) 418 saa.caps |= SMC_CAPS_SD_HIGHSPEED; 419 420 width = OF_getpropint(faa->fa_node, "bus-width", 1); 421 if (width >= 8) 422 saa.caps |= SMC_CAPS_8BIT_MODE; 423 if (width >= 4) 424 saa.caps |= SMC_CAPS_4BIT_MODE; 425 426 sc->sc_sdmmc = config_found(self, &saa, NULL); 427 return; 428 429 unmap: 430 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 431 } 432 433 int 434 dwmmc_alloc_descriptors(struct dwmmc_softc *sc) 435 { 436 int error, rseg; 437 438 /* Allocate descriptor memory */ 439 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 440 PAGE_SIZE, sc->sc_desc_segs, 1, &rseg, 441 BUS_DMA_WAITOK | BUS_DMA_ZERO); 442 if (error) 443 return error; 444 error = bus_dmamem_map(sc->sc_dmat, sc->sc_desc_segs, rseg, 445 PAGE_SIZE, &sc->sc_desc, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 446 if (error) { 447 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 448 return error; 449 } 450 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 451 0, BUS_DMA_WAITOK, &sc->sc_desc_map); 452 if (error) { 453 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 454 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 455 return error; 456 } 457 error = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_map, 458 sc->sc_desc, PAGE_SIZE, NULL, BUS_DMA_WAITOK | BUS_DMA_WRITE); 459 if (error) { 460 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map); 461 bus_dmamem_unmap(sc->sc_dmat, sc->sc_desc, PAGE_SIZE); 462 bus_dmamem_free(sc->sc_dmat, sc->sc_desc_segs, rseg); 463 return error; 464 } 465 466 return 0; 467 } 468 469 void 470 dwmmc_init_descriptors32(struct dwmmc_softc *sc) 471 { 472 struct dwmmc_desc32 *desc; 473 bus_addr_t addr; 474 int i; 475 476 desc = (void *)sc->sc_desc; 477 addr = sc->sc_desc_map->dm_segs[0].ds_addr; 478 for (i = 0; i < DWMMC_NDESC; i++) { 479 addr += sizeof(struct dwmmc_desc32); 480 desc[i].des[3] = addr; 481 } 482 desc[DWMMC_NDESC - 1].des[3] = sc->sc_desc_map->dm_segs[0].ds_addr; 483 desc[DWMMC_NDESC - 1].des[0] = DES0_ER; 484 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 485 PAGE_SIZE, BUS_DMASYNC_PREWRITE); 486 487 HWRITE4(sc, SDMMC_IDSTS32, 0xffffffff); 488 HWRITE4(sc, SDMMC_IDINTEN32, 489 SDMMC_IDINTEN_NI | SDMMC_IDINTEN_RI | SDMMC_IDINTEN_TI); 490 HWRITE4(sc, SDMMC_DBADDR, sc->sc_desc_map->dm_segs[0].ds_addr); 491 } 492 493 void 494 dwmmc_init_descriptors64(struct dwmmc_softc *sc) 495 { 496 struct dwmmc_desc64 *desc; 497 bus_addr_t addr; 498 int i; 499 500 desc = (void *)sc->sc_desc; 501 addr = sc->sc_desc_map->dm_segs[0].ds_addr; 502 for (i = 0; i < DWMMC_NDESC; i++) { 503 addr += sizeof(struct dwmmc_desc64); 504 desc[i].des[6] = addr; 505 desc[i].des[7] = (uint64_t)addr >> 32; 506 } 507 desc[DWMMC_NDESC - 1].des[6] = sc->sc_desc_map->dm_segs[0].ds_addr; 508 desc[DWMMC_NDESC - 1].des[7] = 509 (uint64_t)sc->sc_desc_map->dm_segs[0].ds_addr >> 32; 510 desc[DWMMC_NDESC - 1].des[0] = DES0_ER; 511 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, 512 PAGE_SIZE, BUS_DMASYNC_PREWRITE); 513 514 HWRITE4(sc, SDMMC_IDSTS64, 0xffffffff); 515 HWRITE4(sc, SDMMC_IDINTEN64, 516 SDMMC_IDINTEN_NI | SDMMC_IDINTEN_RI | SDMMC_IDINTEN_TI); 517 HWRITE4(sc, SDMMC_DBADDRL, sc->sc_desc_map->dm_segs[0].ds_addr); 518 HWRITE4(sc, SDMMC_DBADDRH, 519 (uint64_t)sc->sc_desc_map->dm_segs[0].ds_addr >> 32); 520 } 521 522 void 523 dwmmc_init_descriptors(struct dwmmc_softc *sc) 524 { 525 if (sc->sc_dma64) 526 dwmmc_init_descriptors64(sc); 527 else 528 dwmmc_init_descriptors32(sc); 529 } 530 531 int 532 dwmmc_intr(void *arg) 533 { 534 struct dwmmc_softc *sc = arg; 535 uint32_t stat; 536 int handled = 0; 537 538 stat = HREAD4(sc, SDMMC_IDSTS(sc)); 539 if (stat) { 540 HWRITE4(sc, SDMMC_IDSTS(sc), stat); 541 sc->sc_idsts |= stat; 542 wakeup(&sc->sc_idsts); 543 handled = 1; 544 } 545 546 stat = HREAD4(sc, SDMMC_MINTSTS); 547 if (stat & SDMMC_RINTSTS_SDIO) { 548 HCLR4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 549 sdmmc_card_intr(sc->sc_sdmmc); 550 handled = 1; 551 } 552 553 return handled; 554 } 555 556 void 557 dwmmc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 558 { 559 struct dwmmc_softc *sc = sch; 560 561 if (enable) 562 HSET4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 563 else 564 HCLR4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 565 } 566 567 void 568 dwmmc_card_intr_ack(sdmmc_chipset_handle_t sch) 569 { 570 struct dwmmc_softc *sc = sch; 571 572 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_SDIO); 573 HSET4(sc, SDMMC_INTMASK, SDMMC_RINTSTS_SDIO); 574 } 575 576 int 577 dwmmc_host_reset(sdmmc_chipset_handle_t sch) 578 { 579 printf("%s\n", __func__); 580 return 0; 581 } 582 583 uint32_t 584 dwmmc_host_ocr(sdmmc_chipset_handle_t sch) 585 { 586 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 587 } 588 589 int 590 dwmmc_host_maxblklen(sdmmc_chipset_handle_t sch) 591 { 592 return 512; 593 } 594 595 int 596 dwmmc_card_detect(sdmmc_chipset_handle_t sch) 597 { 598 struct dwmmc_softc *sc = sch; 599 uint32_t cdetect; 600 601 if (OF_getproplen(sc->sc_node, "non-removable") == 0) 602 return 1; 603 604 if (sc->sc_gpio[0]) { 605 int inverted, val; 606 607 val = gpio_controller_get_pin(sc->sc_gpio); 608 609 inverted = (OF_getproplen(sc->sc_node, "cd-inverted") == 0); 610 return inverted ? !val : val; 611 } 612 613 cdetect = HREAD4(sc, SDMMC_CDETECT); 614 return !(cdetect & SDMMC_CDETECT_CARD_DETECT_0); 615 } 616 617 int 618 dwmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 619 { 620 struct dwmmc_softc *sc = sch; 621 uint32_t vdd = 0; 622 623 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 624 vdd = 3300000; 625 626 if (sc->sc_vdd == 0 && vdd > 0) 627 dwmmc_pwrseq_pre(sc->sc_pwrseq); 628 629 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 630 HSET4(sc, SDMMC_PWREN, 1); 631 else 632 HCLR4(sc, SDMMC_PWREN, 0); 633 634 if (sc->sc_vdd == 0 && vdd > 0) 635 dwmmc_pwrseq_post(sc->sc_pwrseq); 636 637 sc->sc_vdd = vdd; 638 return 0; 639 } 640 641 int 642 dwmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 643 { 644 struct dwmmc_softc *sc = sch; 645 int div = 0, timeout; 646 uint32_t clkena; 647 648 HWRITE4(sc, SDMMC_CLKENA, 0); 649 HWRITE4(sc, SDMMC_CLKSRC, 0); 650 651 if (freq == 0) 652 return 0; 653 654 if (sc->sc_clkbase / 1000 > freq) { 655 for (div = 1; div < 256; div++) 656 if (sc->sc_clkbase / (2 * 1000 * div) <= freq) 657 break; 658 } 659 HWRITE4(sc, SDMMC_CLKDIV, div); 660 661 /* Update clock. */ 662 HWRITE4(sc, SDMMC_CMD, SDMMC_CMD_START_CMD | 663 SDMMC_CMD_WAIT_PRVDATA_COMPLETE | 664 SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY); 665 for (timeout = 1000; timeout > 0; timeout--) { 666 if ((HREAD4(sc, SDMMC_CMD) & SDMMC_CMD_START_CMD) == 0) 667 break; 668 } 669 if (timeout == 0) { 670 printf("%s: timeout\n", __func__); 671 return ETIMEDOUT; 672 } 673 674 /* Enable clock; low power mode only for memory mode. */ 675 clkena = SDMMC_CLKENA_CCLK_ENABLE; 676 if (!sc->sc_sdio_irq) 677 clkena |= SDMMC_CLKENA_CCLK_LOW_POWER; 678 HWRITE4(sc, SDMMC_CLKENA, clkena); 679 680 /* Update clock again. */ 681 HWRITE4(sc, SDMMC_CMD, SDMMC_CMD_START_CMD | 682 SDMMC_CMD_WAIT_PRVDATA_COMPLETE | 683 SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY); 684 for (timeout = 1000; timeout > 0; timeout--) { 685 if ((HREAD4(sc, SDMMC_CMD) & SDMMC_CMD_START_CMD) == 0) 686 break; 687 } 688 if (timeout == 0) { 689 printf("%s: timeout\n", __func__); 690 return ETIMEDOUT; 691 } 692 693 delay(1000000); 694 695 return 0; 696 } 697 698 int 699 dwmmc_bus_width(sdmmc_chipset_handle_t sch, int width) 700 { 701 struct dwmmc_softc *sc = sch; 702 703 switch (width) { 704 case 1: 705 HCLR4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT|SDMMC_CTYPE_4BIT); 706 break; 707 case 4: 708 HSET4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT); 709 HCLR4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 710 break; 711 case 8: 712 HSET4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 713 break; 714 default: 715 return EINVAL; 716 } 717 718 return 0; 719 } 720 721 void 722 dwmmc_pio_mode(struct dwmmc_softc *sc) 723 { 724 /* Disable DMA. */ 725 HCLR4(sc, SDMMC_CTRL, SDMMC_CTRL_USE_INTERNAL_DMAC | 726 SDMMC_CTRL_DMA_ENABLE); 727 728 /* Set FIFO thresholds. */ 729 HWRITE4(sc, SDMMC_FIFOTH, 2 << SDMMC_FIFOTH_MSIZE_SHIFT | 730 (sc->sc_fifo_depth / 2 - 1) << SDMMC_FIFOTH_RXWM_SHIFT | 731 (sc->sc_fifo_depth / 2) << SDMMC_FIFOTH_TXWM_SHIFT); 732 733 sc->sc_dmamode = 0; 734 sc->sc_blklen = 0; 735 } 736 737 void 738 dwmmc_dma_mode(struct dwmmc_softc *sc) 739 { 740 int timeout; 741 742 /* Reset DMA. */ 743 HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_SWR); 744 for (timeout = 1000; timeout > 0; timeout--) { 745 if ((HREAD4(sc, SDMMC_BMOD) & SDMMC_BMOD_SWR) == 0) 746 break; 747 delay(100); 748 } 749 if (timeout == 0) 750 printf("%s: DMA reset failed\n", sc->sc_dev.dv_xname); 751 752 /* Enable DMA. */ 753 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_USE_INTERNAL_DMAC | 754 SDMMC_CTRL_DMA_ENABLE); 755 HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_FB | SDMMC_BMOD_DE); 756 757 sc->sc_dmamode = 1; 758 } 759 760 void 761 dwmmc_dma_setup32(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 762 { 763 struct dwmmc_desc32 *desc = (void *)sc->sc_desc; 764 uint32_t flags; 765 int seg; 766 767 flags = DES0_OWN | DES0_FS | DES0_CH | DES0_DIC; 768 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 769 bus_addr_t addr = cmd->c_dmamap->dm_segs[seg].ds_addr; 770 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 771 772 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 773 flags |= DES0_LD; 774 flags &= ~DES0_DIC; 775 } 776 777 KASSERT((desc[seg].des[0] & DES0_OWN) == 0); 778 desc[seg].des[0] = flags; 779 desc[seg].des[1] = DES1_BS1(len); 780 desc[seg].des[2] = addr; 781 flags &= ~DES0_FS; 782 } 783 } 784 785 void 786 dwmmc_dma_setup64(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 787 { 788 struct dwmmc_desc64 *desc = (void *)sc->sc_desc; 789 uint32_t flags; 790 int seg; 791 792 flags = DES0_OWN | DES0_FS | DES0_CH | DES0_DIC; 793 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 794 bus_addr_t addr = cmd->c_dmamap->dm_segs[seg].ds_addr; 795 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 796 797 if (seg == cmd->c_dmamap->dm_nsegs - 1) { 798 flags |= DES0_LD; 799 flags &= ~DES0_DIC; 800 } 801 802 KASSERT((desc[seg].des[0] & DES0_OWN) == 0); 803 desc[seg].des[0] = flags; 804 desc[seg].des[2] = DES2_BS1(len); 805 desc[seg].des[4] = addr; 806 desc[seg].des[5] = (uint64_t)addr >> 32; 807 flags &= ~DES0_FS; 808 } 809 } 810 811 void 812 dwmmc_dma_setup(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 813 { 814 if (sc->sc_dma64) 815 dwmmc_dma_setup64(sc, cmd); 816 else 817 dwmmc_dma_setup32(sc, cmd); 818 819 bus_dmamap_sync(sc->sc_dmat, sc->sc_desc_map, 0, PAGE_SIZE, 820 BUS_DMASYNC_PREWRITE); 821 822 sc->sc_idsts = 0; 823 } 824 825 void 826 dwmmc_dma_reset(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 827 { 828 int timeout; 829 830 /* Reset DMA unit. */ 831 HSET4(sc, SDMMC_BMOD, SDMMC_BMOD_SWR); 832 for (timeout = 1000; timeout > 0; timeout--) { 833 if ((HREAD4(sc, SDMMC_BMOD) & 834 SDMMC_BMOD_SWR) == 0) 835 break; 836 delay(100); 837 } 838 839 dwmmc_pio_mode(sc); 840 841 /* Clear descriptors that were in use, */ 842 memset(sc->sc_desc, 0, PAGE_SIZE); 843 dwmmc_init_descriptors(sc); 844 } 845 846 void 847 dwmmc_fifo_setup(struct dwmmc_softc *sc, int blklen) 848 { 849 int blkdepth = blklen / sc->sc_fifo_width; 850 int txwm = sc->sc_fifo_depth / 2; 851 int rxwm, msize = 0; 852 853 /* 854 * Bursting is only possible of the block size is a multiple of 855 * the FIFO width. 856 */ 857 if (blklen % sc->sc_fifo_width == 0) 858 msize = 7; 859 860 /* Magic to calculate the maximum burst size. */ 861 while (msize > 0) { 862 if (blkdepth % (2 << msize) == 0 && 863 (sc->sc_fifo_depth - txwm) % (2 << msize) == 0) 864 break; 865 msize--; 866 } 867 rxwm = (2 << msize) - 1; 868 869 HWRITE4(sc, SDMMC_FIFOTH, 870 msize << SDMMC_FIFOTH_MSIZE_SHIFT | 871 rxwm << SDMMC_FIFOTH_RXWM_SHIFT | 872 txwm << SDMMC_FIFOTH_TXWM_SHIFT); 873 874 sc->sc_blklen = blklen; 875 } 876 877 void 878 dwmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 879 { 880 struct dwmmc_softc *sc = sch; 881 uint32_t cmdval = SDMMC_CMD_START_CMD | SDMMC_CMD_USE_HOLD_REG; 882 uint32_t status; 883 int error, timeout; 884 int s; 885 886 #if 0 887 printf("%s: cmd %d arg 0x%x flags 0x%x data %p datalen %d blklen %d\n", 888 sc->sc_dev.dv_xname, cmd->c_opcode, cmd->c_arg, cmd->c_flags, 889 cmd->c_data, cmd->c_datalen, cmd->c_blklen); 890 #endif 891 892 s = splbio(); 893 894 for (timeout = 10000; timeout > 0; timeout--) { 895 status = HREAD4(sc, SDMMC_STATUS); 896 if ((status & SDMMC_STATUS_DATA_BUSY) == 0) 897 break; 898 delay(100); 899 } 900 if (timeout == 0) { 901 printf("%s: timeout on data busy\n", sc->sc_dev.dv_xname); 902 goto done; 903 } 904 905 if (cmd->c_opcode == MMC_STOP_TRANSMISSION) 906 cmdval |= SDMMC_CMD_STOP_ABORT_CMD; 907 else if (cmd->c_opcode != MMC_SEND_STATUS) 908 cmdval |= SDMMC_CMD_WAIT_PRVDATA_COMPLETE; 909 910 if (cmd->c_opcode == 0) 911 cmdval |= SDMMC_CMD_SEND_INITIALIZATION; 912 if (cmd->c_flags & SCF_RSP_PRESENT) 913 cmdval |= SDMMC_CMD_RESPONSE_EXPECT; 914 if (cmd->c_flags & SCF_RSP_136) 915 cmdval |= SDMMC_CMD_RESPONSE_LENGTH; 916 if (cmd->c_flags & SCF_RSP_CRC) 917 cmdval |= SDMMC_CMD_CHECK_REPONSE_CRC; 918 919 if (cmd->c_datalen > 0) { 920 HWRITE4(sc, SDMMC_TMOUT, 0xffffffff); 921 HWRITE4(sc, SDMMC_BYTCNT, cmd->c_datalen); 922 HWRITE4(sc, SDMMC_BLKSIZ, cmd->c_blklen); 923 924 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 925 /* Set card read threshold to the size of a block. */ 926 HWRITE4(sc, SDMMC_CARDTHRCTL, 927 cmd->c_blklen << SDMMC_CARDTHRCTL_RDTHR_SHIFT | 928 SDMMC_CARDTHRCTL_RDTHREN); 929 } 930 931 cmdval |= SDMMC_CMD_DATA_EXPECTED; 932 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 933 cmdval |= SDMMC_CMD_WR; 934 if (cmd->c_datalen > cmd->c_blklen && 935 cmd->c_opcode != SD_IO_RW_EXTENDED) 936 cmdval |= SDMMC_CMD_SEND_AUTO_STOP; 937 } 938 939 if (cmd->c_datalen > 0 && !cmd->c_dmamap) { 940 HSET4(sc, SDMMC_CTRL, SDMMC_CTRL_FIFO_RESET); 941 for (timeout = 1000; timeout > 0; timeout--) { 942 if ((HREAD4(sc, SDMMC_CTRL) & 943 SDMMC_CTRL_FIFO_RESET) == 0) 944 break; 945 delay(100); 946 } 947 if (timeout == 0) 948 printf("%s: FIFO reset failed\n", sc->sc_dev.dv_xname); 949 950 /* Disable DMA if we are switching back to PIO. */ 951 if (sc->sc_dmamode) 952 dwmmc_pio_mode(sc); 953 } 954 955 if (cmd->c_datalen > 0 && cmd->c_dmamap) { 956 dwmmc_dma_setup(sc, cmd); 957 HWRITE4(sc, SDMMC_PLDMND, 1); 958 959 /* Ennable DMA if we did PIO before. */ 960 if (!sc->sc_dmamode) 961 dwmmc_dma_mode(sc); 962 963 /* Reconfigure FIFO thresholds if block size changed. */ 964 if (cmd->c_blklen != sc->sc_blklen) 965 dwmmc_fifo_setup(sc, cmd->c_blklen); 966 } 967 968 HWRITE4(sc, SDMMC_RINTSTS, ~SDMMC_RINTSTS_SDIO); 969 970 HWRITE4(sc, SDMMC_CMDARG, cmd->c_arg); 971 HWRITE4(sc, SDMMC_CMD, cmdval | cmd->c_opcode); 972 973 for (timeout = 1000; timeout > 0; timeout--) { 974 status = HREAD4(sc, SDMMC_RINTSTS); 975 if (status & SDMMC_RINTSTS_CD) 976 break; 977 delay(100); 978 } 979 if (timeout == 0 || status & SDMMC_RINTSTS_RTO) { 980 cmd->c_error = ETIMEDOUT; 981 dwmmc_dma_reset(sc, cmd); 982 goto done; 983 } 984 985 if (cmd->c_flags & SCF_RSP_PRESENT) { 986 if (cmd->c_flags & SCF_RSP_136) { 987 cmd->c_resp[0] = HREAD4(sc, SDMMC_RESP0); 988 cmd->c_resp[1] = HREAD4(sc, SDMMC_RESP1); 989 cmd->c_resp[2] = HREAD4(sc, SDMMC_RESP2); 990 cmd->c_resp[3] = HREAD4(sc, SDMMC_RESP3); 991 if (cmd->c_flags & SCF_RSP_CRC) { 992 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 993 (cmd->c_resp[1] << 24); 994 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 995 (cmd->c_resp[2] << 24); 996 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 997 (cmd->c_resp[3] << 24); 998 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 999 } 1000 } else { 1001 cmd->c_resp[0] = HREAD4(sc, SDMMC_RESP0); 1002 } 1003 } 1004 1005 if (cmd->c_datalen > 0 && !cmd->c_dmamap) 1006 dwmmc_transfer_data(sc, cmd); 1007 1008 if (cmd->c_datalen > 0 && cmd->c_dmamap) { 1009 while (sc->sc_idsts == 0) { 1010 error = tsleep(&sc->sc_idsts, PWAIT, "idsts", hz); 1011 if (error) { 1012 cmd->c_error = error; 1013 dwmmc_dma_reset(sc, cmd); 1014 goto done; 1015 } 1016 } 1017 1018 for (timeout = 10000; timeout > 0; timeout--) { 1019 status = HREAD4(sc, SDMMC_RINTSTS); 1020 if (status & SDMMC_RINTSTS_DTO) 1021 break; 1022 delay(100); 1023 } 1024 if (timeout == 0) { 1025 cmd->c_error = ETIMEDOUT; 1026 dwmmc_dma_reset(sc, cmd); 1027 goto done; 1028 } 1029 } 1030 1031 if (cmdval & SDMMC_CMD_SEND_AUTO_STOP) { 1032 for (timeout = 10000; timeout > 0; timeout--) { 1033 status = HREAD4(sc, SDMMC_RINTSTS); 1034 if (status & SDMMC_RINTSTS_ACD) 1035 break; 1036 delay(10); 1037 } 1038 if (timeout == 0) { 1039 cmd->c_error = ETIMEDOUT; 1040 dwmmc_dma_reset(sc, cmd); 1041 goto done; 1042 } 1043 } 1044 1045 done: 1046 cmd->c_flags |= SCF_ITSDONE; 1047 #if 0 1048 printf("%s: err %d rintsts 0x%x\n", sc->sc_dev.dv_xname, cmd->c_error, 1049 HREAD4(sc, SDMMC_RINTSTS)); 1050 #endif 1051 splx(s); 1052 } 1053 1054 void 1055 dwmmc_transfer_data(struct dwmmc_softc *sc, struct sdmmc_command *cmd) 1056 { 1057 int datalen = cmd->c_datalen; 1058 u_char *datap = cmd->c_data; 1059 uint32_t status; 1060 int count, timeout; 1061 int fifodr = SDMMC_RINTSTS_DTO | SDMMC_RINTSTS_HTO; 1062 1063 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1064 fifodr |= SDMMC_RINTSTS_RXDR; 1065 else 1066 fifodr |= SDMMC_RINTSTS_TXDR; 1067 1068 while (datalen > 0) { 1069 status = HREAD4(sc, SDMMC_RINTSTS); 1070 if (status & SDMMC_RINTSTS_DATA_ERR) { 1071 cmd->c_error = EIO; 1072 return; 1073 } 1074 if (status & SDMMC_RINTSTS_DRTO) { 1075 cmd->c_error = ETIMEDOUT; 1076 return; 1077 } 1078 1079 for (timeout = 10000; timeout > 0; timeout--) { 1080 status = HREAD4(sc, SDMMC_RINTSTS); 1081 if (status & fifodr) 1082 break; 1083 delay(100); 1084 } 1085 if (timeout == 0) { 1086 cmd->c_error = ETIMEDOUT; 1087 return; 1088 } 1089 1090 count = SDMMC_STATUS_FIFO_COUNT(HREAD4(sc, SDMMC_STATUS)); 1091 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 1092 count = sc->sc_fifo_depth - count; 1093 1094 count = MIN(datalen, count * sc->sc_fifo_width); 1095 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1096 sc->sc_read_data(sc, datap, count); 1097 else 1098 sc->sc_write_data(sc, datap, count); 1099 1100 datap += count; 1101 datalen -= count; 1102 } 1103 1104 for (timeout = 10000; timeout > 0; timeout--) { 1105 status = HREAD4(sc, SDMMC_RINTSTS); 1106 if (status & SDMMC_RINTSTS_DTO) 1107 break; 1108 delay(100); 1109 } 1110 if (timeout == 0) 1111 cmd->c_error = ETIMEDOUT; 1112 } 1113 1114 void 1115 dwmmc_read_data32(struct dwmmc_softc *sc, u_char *datap, int datalen) 1116 { 1117 while (datalen > 3) { 1118 *(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE); 1119 datap += 4; 1120 datalen -= 4; 1121 } 1122 if (datalen > 0) { 1123 uint32_t rv = HREAD4(sc, SDMMC_FIFO_BASE); 1124 do { 1125 *datap++ = rv & 0xff; 1126 rv = rv >> 8; 1127 } while (--datalen > 0); 1128 } 1129 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_RXDR); 1130 } 1131 1132 void 1133 dwmmc_write_data32(struct dwmmc_softc *sc, u_char *datap, int datalen) 1134 { 1135 while (datalen > 3) { 1136 HWRITE4(sc, SDMMC_FIFO_BASE, *((uint32_t *)datap)); 1137 datap += 4; 1138 datalen -= 4; 1139 } 1140 if (datalen > 0) { 1141 uint32_t rv = *datap++; 1142 if (datalen > 1) 1143 rv |= *datap++ << 8; 1144 if (datalen > 2) 1145 rv |= *datap++ << 16; 1146 HWRITE4(sc, SDMMC_FIFO_BASE, rv); 1147 } 1148 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_TXDR); 1149 } 1150 1151 void 1152 dwmmc_read_data64(struct dwmmc_softc *sc, u_char *datap, int datalen) 1153 { 1154 while (datalen > 7) { 1155 *(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE); 1156 datap += 4; 1157 datalen -= 4; 1158 *(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE + 4); 1159 datap += 4; 1160 datalen -= 4; 1161 } 1162 if (datalen > 0) { 1163 uint64_t rv = HREAD4(sc, SDMMC_FIFO_BASE) | 1164 ((uint64_t)HREAD4(sc, SDMMC_FIFO_BASE + 4) << 32); 1165 do { 1166 *datap++ = rv & 0xff; 1167 rv = rv >> 8; 1168 } while (--datalen > 0); 1169 } 1170 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_RXDR); 1171 } 1172 1173 void 1174 dwmmc_write_data64(struct dwmmc_softc *sc, u_char *datap, int datalen) 1175 { 1176 while (datalen > 7) { 1177 HWRITE4(sc, SDMMC_FIFO_BASE, *((uint32_t *)datap)); 1178 datap += 4; 1179 datalen -= 4; 1180 HWRITE4(sc, SDMMC_FIFO_BASE + 4, *((uint32_t *)datap)); 1181 datap += 4; 1182 datalen -= 4; 1183 } 1184 if (datalen > 0) { 1185 uint32_t rv = *datap++; 1186 if (datalen > 1) 1187 rv |= *datap++ << 8; 1188 if (datalen > 2) 1189 rv |= *datap++ << 16; 1190 if (datalen > 3) 1191 rv |= *datap++ << 24; 1192 HWRITE4(sc, SDMMC_FIFO_BASE, rv); 1193 if (datalen > 4) 1194 rv = *datap++; 1195 if (datalen > 5) 1196 rv |= *datap++ << 8; 1197 if (datalen > 6) 1198 rv |= *datap++ << 16; 1199 HWRITE4(sc, SDMMC_FIFO_BASE + 4, rv); 1200 } 1201 HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_TXDR); 1202 } 1203 1204 void 1205 dwmmc_pwrseq_pre(uint32_t phandle) 1206 { 1207 uint32_t *gpios, *gpio; 1208 int node; 1209 int len; 1210 1211 node = OF_getnodebyphandle(phandle); 1212 if (node == 0) 1213 return; 1214 1215 if (!OF_is_compatible(node, "mmc-pwrseq-simple")) 1216 return; 1217 1218 pinctrl_byname(node, "default"); 1219 1220 clock_enable(node, "ext_clock"); 1221 1222 len = OF_getproplen(node, "reset-gpios"); 1223 if (len <= 0) 1224 return; 1225 1226 gpios = malloc(len, M_TEMP, M_WAITOK); 1227 OF_getpropintarray(node, "reset-gpios", gpios, len); 1228 1229 gpio = gpios; 1230 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) { 1231 gpio_controller_config_pin(gpio, GPIO_CONFIG_OUTPUT); 1232 gpio_controller_set_pin(gpio, 1); 1233 gpio = gpio_controller_next_pin(gpio); 1234 } 1235 1236 free(gpios, M_TEMP, len); 1237 } 1238 1239 void 1240 dwmmc_pwrseq_post(uint32_t phandle) 1241 { 1242 uint32_t *gpios, *gpio; 1243 int node; 1244 int len; 1245 1246 node = OF_getnodebyphandle(phandle); 1247 if (node == 0) 1248 return; 1249 1250 if (!OF_is_compatible(node, "mmc-pwrseq-simple")) 1251 return; 1252 1253 len = OF_getproplen(node, "reset-gpios"); 1254 if (len <= 0) 1255 return; 1256 1257 gpios = malloc(len, M_TEMP, M_WAITOK); 1258 OF_getpropintarray(node, "reset-gpios", gpios, len); 1259 1260 gpio = gpios; 1261 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) { 1262 gpio_controller_set_pin(gpio, 0); 1263 gpio = gpio_controller_next_pin(gpio); 1264 } 1265 1266 free(gpios, M_TEMP, len); 1267 } 1268