1 /* $OpenBSD: imxesdhc.c,v 1.11 2018/12/29 11:37:54 patrick Exp $ */ 2 /* 3 * Copyright (c) 2009 Dale Rahn <drahn@openbsd.org> 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* i.MX SD/MMC support derived from /sys/dev/sdmmc/sdhc.c */ 21 22 #include <sys/param.h> 23 #include <sys/device.h> 24 #include <sys/kernel.h> 25 #include <sys/kthread.h> 26 #include <sys/malloc.h> 27 #include <sys/systm.h> 28 #include <machine/bus.h> 29 #include <machine/fdt.h> 30 31 #include <dev/sdmmc/sdmmcchip.h> 32 #include <dev/sdmmc/sdmmcvar.h> 33 #include <dev/sdmmc/sdmmc_ioreg.h> 34 35 #include <dev/ofw/openfirm.h> 36 #include <dev/ofw/ofw_clock.h> 37 #include <dev/ofw/ofw_gpio.h> 38 #include <dev/ofw/ofw_pinctrl.h> 39 #include <dev/ofw/ofw_regulator.h> 40 #include <dev/ofw/fdt.h> 41 42 /* registers */ 43 #define SDHC_DS_ADDR 0x00 44 #define SDHC_BLK_ATT 0x04 45 #define SDHC_CMD_ARG 0x08 46 #define SDHC_CMD_XFR_TYP 0x0c 47 #define SDHC_CMD_RSP0 0x10 48 #define SDHC_CMD_RSP1 0x14 49 #define SDHC_CMD_RSP2 0x18 50 #define SDHC_CMD_RSP3 0x1c 51 #define SDHC_DATA_BUFF_ACC_PORT 0x20 52 #define SDHC_PRES_STATE 0x24 53 #define SDHC_PROT_CTRL 0x28 54 #define SDHC_SYS_CTRL 0x2c 55 #define SDHC_INT_STATUS 0x30 56 #define SDHC_INT_STATUS_EN 0x34 57 #define SDHC_INT_SIGNAL_EN 0x38 58 #define SDHC_AUTOCMD12_ERR_STATUS 0x3c 59 #define SDHC_HOST_CTRL_CAP 0x40 60 #define SDHC_WTMK_LVL 0x44 61 #define SDHC_MIX_CTRL 0x48 62 #define SDHC_FORCE_EVENT 0x50 63 #define SDHC_ADMA_ERR_STATUS 0x54 64 #define SDHC_ADMA_SYS_ADDR 0x58 65 #define SDHC_DLL_CTRL 0x60 66 #define SDHC_DLL_STATUS 0x64 67 #define SDHC_CLK_TUNE_CTRL_STATUS 0x68 68 #define SDHC_VEND_SPEC 0xc0 69 #define SDHC_MMC_BOOT 0xc4 70 #define SDHC_VEND_SPEC2 0xc8 71 #define SDHC_HOST_CTRL_VER 0xfc 72 73 /* bits and bytes */ 74 #define SDHC_BLK_ATT_BLKCNT_MAX 0xffff 75 #define SDHC_BLK_ATT_BLKCNT_SHIFT 16 76 #define SDHC_BLK_ATT_BLKSIZE_SHIFT 0 77 #define SDHC_CMD_XFR_TYP_CMDINDX_SHIFT 24 78 #define SDHC_CMD_XFR_TYP_CMDINDX_SHIFT_MASK (0x3f << SDHC_CMD_XFR_TYP_CMDINDX_SHIFT) 79 #define SDHC_CMD_XFR_TYP_CMDTYP_SHIFT 22 80 #define SDHC_CMD_XFR_TYP_DPSEL_SHIFT 21 81 #define SDHC_CMD_XFR_TYP_DPSEL (1 << SDHC_CMD_XFR_TYP_DPSEL_SHIFT) 82 #define SDHC_CMD_XFR_TYP_CICEN_SHIFT 20 83 #define SDHC_CMD_XFR_TYP_CICEN (1 << SDHC_CMD_XFR_TYP_CICEN_SHIFT) 84 #define SDHC_CMD_XFR_TYP_CCCEN_SHIFT 19 85 #define SDHC_CMD_XFR_TYP_CCCEN (1 << SDHC_CMD_XFR_TYP_CCCEN_SHIFT) 86 #define SDHC_CMD_XFR_TYP_RSPTYP_SHIFT 16 87 #define SDHC_CMD_XFR_TYP_RSP_NONE (0x0 << SDHC_CMD_XFR_TYP_RSPTYP_SHIFT) 88 #define SDHC_CMD_XFR_TYP_RSP136 (0x1 << SDHC_CMD_XFR_TYP_RSPTYP_SHIFT) 89 #define SDHC_CMD_XFR_TYP_RSP48 (0x2 << SDHC_CMD_XFR_TYP_RSPTYP_SHIFT) 90 #define SDHC_CMD_XFR_TYP_RSP48B (0x3 << SDHC_CMD_XFR_TYP_RSPTYP_SHIFT) 91 #define SDHC_PRES_STATE_WPSPL (1 << 19) 92 #define SDHC_PRES_STATE_BREN (1 << 11) 93 #define SDHC_PRES_STATE_BWEN (1 << 10) 94 #define SDHC_PRES_STATE_SDSTB (1 << 3) 95 #define SDHC_PRES_STATE_DLA (1 << 2) 96 #define SDHC_PRES_STATE_CDIHB (1 << 1) 97 #define SDHC_PRES_STATE_CIHB (1 << 0) 98 #define SDHC_SYS_CTRL_RSTA (1 << 24) 99 #define SDHC_SYS_CTRL_RSTC (1 << 25) 100 #define SDHC_SYS_CTRL_RSTD (1 << 26) 101 #define SDHC_SYS_CTRL_CLOCK_MASK (0xfff << 4) 102 #define SDHC_SYS_CTRL_CLOCK_DIV_SHIFT 4 103 #define SDHC_SYS_CTRL_CLOCK_PRE_SHIFT 8 104 #define SDHC_SYS_CTRL_DTOCV_SHIFT 16 105 #define SDHC_INT_STATUS_CC (1 << 0) 106 #define SDHC_INT_STATUS_TC (1 << 1) 107 #define SDHC_INT_STATUS_BGE (1 << 2) 108 #define SDHC_INT_STATUS_DINT (1 << 3) 109 #define SDHC_INT_STATUS_BWR (1 << 4) 110 #define SDHC_INT_STATUS_BRR (1 << 5) 111 #define SDHC_INT_STATUS_CINS (1 << 6) 112 #define SDHC_INT_STATUS_CRM (1 << 7) 113 #define SDHC_INT_STATUS_CINT (1 << 8) 114 #define SDHC_INT_STATUS_CTOE (1 << 16) 115 #define SDHC_INT_STATUS_CCE (1 << 17) 116 #define SDHC_INT_STATUS_CEBE (1 << 18) 117 #define SDHC_INT_STATUS_CIC (1 << 19) 118 #define SDHC_INT_STATUS_DTOE (1 << 20) 119 #define SDHC_INT_STATUS_DCE (1 << 21) 120 #define SDHC_INT_STATUS_DEBE (1 << 22) 121 #define SDHC_INT_STATUS_DMAE (1 << 28) 122 #define SDHC_INT_STATUS_CMD_ERR (SDHC_INT_STATUS_CIC | SDHC_INT_STATUS_CEBE | SDHC_INT_STATUS_CCE) 123 #define SDHC_INT_STATUS_ERR (SDHC_INT_STATUS_CTOE | SDHC_INT_STATUS_CCE | SDHC_INT_STATUS_CEBE | \ 124 SDHC_INT_STATUS_CIC | SDHC_INT_STATUS_DTOE | SDHC_INT_STATUS_DCE | \ 125 SDHC_INT_STATUS_DEBE | SDHC_INT_STATUS_DMAE) 126 #define SDHC_MIX_CTRL_DMAEN (1 << 0) 127 #define SDHC_MIX_CTRL_BCEN (1 << 1) 128 #define SDHC_MIX_CTRL_AC12EN (1 << 2) 129 #define SDHC_MIX_CTRL_DTDSEL (1 << 4) 130 #define SDHC_MIX_CTRL_MSBSEL (1 << 5) 131 #define SDHC_PROT_CTRL_DTW_MASK (0x3 << 1) 132 #define SDHC_PROT_CTRL_DTW_4BIT (1 << 1) 133 #define SDHC_PROT_CTRL_DTW_8BIT (1 << 2) 134 #define SDHC_PROT_CTRL_DMASEL_MASK (0x3 << 8) 135 #define SDHC_PROT_CTRL_DMASEL_SDMA (0x0 << 8) 136 #define SDHC_PROT_CTRL_DMASEL_ADMA1 (0x1 << 8) 137 #define SDHC_PROT_CTRL_DMASEL_ADMA2 (0x2 << 8) 138 #define SDHC_HOST_CTRL_CAP_MBL_SHIFT 16 139 #define SDHC_HOST_CTRL_CAP_MBL_MASK 0x7 140 #define SDHC_HOST_CTRL_CAP_ADMAS (1 << 20) 141 #define SDHC_HOST_CTRL_CAP_HSS (1 << 21) 142 #define SDHC_HOST_CTRL_CAP_VS33 (1 << 24) 143 #define SDHC_HOST_CTRL_CAP_VS30 (1 << 25) 144 #define SDHC_HOST_CTRL_CAP_VS18 (1 << 26) 145 #define SDHC_VEND_SPEC_FRC_SDCLK_ON (1 << 8) 146 #define SDHC_WTMK_LVL_RD_WML_SHIFT 0 147 #define SDHC_WTMK_LVL_RD_BRST_LEN_SHIFT 8 148 #define SDHC_WTMK_LVL_WR_WML_SHIFT 16 149 #define SDHC_WTMK_LVL_WR_BRST_LEN_SHIFT 24 150 151 #define SDHC_COMMAND_TIMEOUT hz 152 #define SDHC_BUFFER_TIMEOUT hz 153 #define SDHC_TRANSFER_TIMEOUT hz 154 #define SDHC_DMA_TIMEOUT (3 * hz) 155 156 #define SDHC_ADMA2_VALID (1 << 0) 157 #define SDHC_ADMA2_END (1 << 1) 158 #define SDHC_ADMA2_INT (1 << 2) 159 #define SDHC_ADMA2_ACT (3 << 4) 160 #define SDHC_ADMA2_ACT_NOP (0 << 4) 161 #define SDHC_ADMA2_ACT_TRANS (2 << 4) 162 #define SDHC_ADMA2_ACT_LINK (3 << 4) 163 164 struct sdhc_adma2_descriptor32 { 165 uint16_t attribute; 166 uint16_t length; 167 uint32_t address; 168 } __packed; 169 170 171 int imxesdhc_match(struct device *, void *, void *); 172 void imxesdhc_attach(struct device *, struct device *, void *); 173 174 struct imxesdhc_softc { 175 struct device sc_dev; 176 bus_space_tag_t sc_iot; 177 bus_space_handle_t sc_ioh; 178 bus_dma_tag_t sc_dmat; 179 void *sc_ih; /* interrupt handler */ 180 int sc_node; 181 uint32_t sc_gpio[3]; 182 uint32_t sc_vmmc; 183 uint32_t sc_pwrseq; 184 uint32_t sc_vdd; 185 int sc_cookies[SDMMC_MAX_FUNCTIONS]; 186 u_int sc_flags; 187 188 struct device *sdmmc; /* generic SD/MMC device */ 189 int clockbit; /* clock control bit */ 190 u_int clkbase; /* base clock freq. in KHz */ 191 int maxblklen; /* maximum block length */ 192 int flags; /* flags for this host */ 193 uint32_t ocr; /* OCR value from caps */ 194 uint32_t intr_status; /* soft interrupt status */ 195 uint32_t intr_error_status; 196 197 bus_dmamap_t adma_map; 198 bus_dma_segment_t adma_segs[1]; 199 caddr_t adma2; 200 }; 201 202 /* Host controller functions called by the attachment driver. */ 203 int imxesdhc_intr(void *); 204 205 void imxesdhc_clock_enable(uint32_t); 206 void imxesdhc_pwrseq_pre(uint32_t); 207 void imxesdhc_pwrseq_post(uint32_t); 208 209 /* RESET MODES */ 210 #define MMC_RESET_DAT 1 211 #define MMC_RESET_CMD 2 212 #define MMC_RESET_ALL (MMC_RESET_CMD|MMC_RESET_DAT) 213 214 #define HDEVNAME(sc) ((sc)->sc_dev.dv_xname) 215 216 /* flag values */ 217 #define SHF_USE_DMA 0x0001 218 219 /* SDHC should only be accessed with 4 byte reads or writes. */ 220 #define HREAD4(sc, reg) \ 221 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 222 #define HWRITE4(sc, reg, val) \ 223 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 224 #define HSET4(sc, reg, bits) \ 225 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 226 #define HCLR4(sc, reg, bits) \ 227 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 228 229 int imxesdhc_host_reset(sdmmc_chipset_handle_t); 230 uint32_t imxesdhc_host_ocr(sdmmc_chipset_handle_t); 231 int imxesdhc_host_maxblklen(sdmmc_chipset_handle_t); 232 int imxesdhc_card_detect(sdmmc_chipset_handle_t); 233 int imxesdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 234 int imxesdhc_bus_clock(sdmmc_chipset_handle_t, int, int); 235 int imxesdhc_bus_width(sdmmc_chipset_handle_t, int); 236 void imxesdhc_card_intr_mask(sdmmc_chipset_handle_t, int); 237 void imxesdhc_card_intr_ack(sdmmc_chipset_handle_t); 238 void imxesdhc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 239 int imxesdhc_start_command(struct imxesdhc_softc *, struct sdmmc_command *); 240 int imxesdhc_wait_state(struct imxesdhc_softc *, uint32_t, uint32_t); 241 int imxesdhc_soft_reset(struct imxesdhc_softc *, int); 242 int imxesdhc_wait_intr(struct imxesdhc_softc *, int, int); 243 void imxesdhc_transfer_data(struct imxesdhc_softc *, struct sdmmc_command *); 244 void imxesdhc_read_data(struct imxesdhc_softc *, u_char *, int); 245 void imxesdhc_write_data(struct imxesdhc_softc *, u_char *, int); 246 247 //#define SDHC_DEBUG 248 #ifdef SDHC_DEBUG 249 int imxesdhcdebug = 20; 250 #define DPRINTF(n,s) do { if ((n) <= imxesdhcdebug) printf s; } while (0) 251 #else 252 #define DPRINTF(n,s) do {} while(0) 253 #endif 254 255 struct sdmmc_chip_functions imxesdhc_functions = { 256 /* host controller reset */ 257 imxesdhc_host_reset, 258 /* host controller capabilities */ 259 imxesdhc_host_ocr, 260 imxesdhc_host_maxblklen, 261 /* card detection */ 262 imxesdhc_card_detect, 263 /* bus power and clock frequency */ 264 imxesdhc_bus_power, 265 imxesdhc_bus_clock, 266 imxesdhc_bus_width, 267 /* command execution */ 268 imxesdhc_exec_command, 269 /* card interrupt */ 270 imxesdhc_card_intr_mask, 271 imxesdhc_card_intr_ack 272 }; 273 274 struct cfdriver imxesdhc_cd = { 275 NULL, "imxesdhc", DV_DULL 276 }; 277 278 struct cfattach imxesdhc_ca = { 279 sizeof(struct imxesdhc_softc), imxesdhc_match, imxesdhc_attach 280 }; 281 282 int 283 imxesdhc_match(struct device *parent, void *match, void *aux) 284 { 285 struct fdt_attach_args *faa = aux; 286 287 return OF_is_compatible(faa->fa_node, "fsl,imx6q-usdhc") || 288 OF_is_compatible(faa->fa_node, "fsl,imx6sl-usdhc") || 289 OF_is_compatible(faa->fa_node, "fsl,imx6sx-usdhc") || 290 OF_is_compatible(faa->fa_node, "fsl,imx8mq-usdhc"); 291 } 292 293 void 294 imxesdhc_attach(struct device *parent, struct device *self, void *aux) 295 { 296 struct imxesdhc_softc *sc = (struct imxesdhc_softc *) self; 297 struct fdt_attach_args *faa = aux; 298 struct sdmmcbus_attach_args saa; 299 int error = 1, node, reg; 300 uint32_t caps; 301 uint32_t width; 302 303 if (faa->fa_nreg < 1) 304 return; 305 306 sc->sc_node = faa->fa_node; 307 sc->sc_dmat = faa->fa_dmat; 308 sc->sc_iot = faa->fa_iot; 309 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 310 faa->fa_reg[0].size, 0, &sc->sc_ioh)) 311 panic("imxesdhc_attach: bus_space_map failed!"); 312 313 printf("\n"); 314 315 pinctrl_byname(faa->fa_node, "default"); 316 317 clock_set_assigned(faa->fa_node); 318 319 sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_SDMMC, 320 imxesdhc_intr, sc, sc->sc_dev.dv_xname); 321 322 OF_getpropintarray(sc->sc_node, "cd-gpios", sc->sc_gpio, 323 sizeof(sc->sc_gpio)); 324 gpio_controller_config_pin(sc->sc_gpio, GPIO_CONFIG_INPUT); 325 326 sc->sc_vmmc = OF_getpropint(sc->sc_node, "vmmc-supply", 0); 327 sc->sc_pwrseq = OF_getpropint(sc->sc_node, "mmc-pwrseq", 0); 328 329 /* 330 * Reset the host controller and enable interrupts. 331 */ 332 if (imxesdhc_host_reset(sc)) 333 return; 334 335 /* Determine host capabilities. */ 336 caps = HREAD4(sc, SDHC_HOST_CTRL_CAP); 337 if (OF_is_compatible(sc->sc_node, "fsl,imx6sl-usdhc") || 338 OF_is_compatible(sc->sc_node, "fsl,imx6sx-usdhc") || 339 OF_is_compatible(sc->sc_node, "fsl,imx8mq-usdhc")) 340 caps &= 0xffff0000; 341 342 /* Use DMA if the host system and the controller support it. */ 343 if (ISSET(caps, SDHC_HOST_CTRL_CAP_ADMAS)) 344 SET(sc->flags, SHF_USE_DMA); 345 346 /* 347 * Determine the base clock frequency. (2.2.24) 348 */ 349 sc->clkbase = clock_get_frequency(faa->fa_node, "per") / 1000; 350 351 printf("%s: %d MHz base clock\n", DEVNAME(sc), sc->clkbase / 1000); 352 353 /* 354 * Determine SD bus voltage levels supported by the controller. 355 */ 356 if (caps & SDHC_HOST_CTRL_CAP_VS18) 357 SET(sc->ocr, MMC_OCR_1_65V_1_95V); 358 if (caps & SDHC_HOST_CTRL_CAP_VS30) 359 SET(sc->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 360 if (caps & SDHC_HOST_CTRL_CAP_VS33) 361 SET(sc->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 362 363 /* 364 * Determine max block size. 365 */ 366 switch ((caps >> SDHC_HOST_CTRL_CAP_MBL_SHIFT) 367 & SDHC_HOST_CTRL_CAP_MBL_MASK) { 368 case 0: 369 sc->maxblklen = 512; 370 break; 371 case 1: 372 sc->maxblklen = 1024; 373 break; 374 case 2: 375 sc->maxblklen = 2048; 376 break; 377 case 3: 378 sc->maxblklen = 4096; 379 break; 380 default: 381 sc->maxblklen = 512; 382 printf("invalid capability blocksize in capa %08x," 383 " trying 512\n", caps); 384 } 385 386 /* somewhere this blksize might be used instead of the device's */ 387 sc->maxblklen = 512; 388 389 if (ISSET(sc->flags, SHF_USE_DMA)) { 390 int rseg; 391 392 /* Allocate ADMA2 descriptor memory */ 393 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 394 PAGE_SIZE, sc->adma_segs, 1, &rseg, 395 BUS_DMA_WAITOK | BUS_DMA_ZERO); 396 if (error) 397 goto adma_done; 398 error = bus_dmamem_map(sc->sc_dmat, sc->adma_segs, rseg, 399 PAGE_SIZE, &sc->adma2, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 400 if (error) { 401 bus_dmamem_free(sc->sc_dmat, sc->adma_segs, rseg); 402 goto adma_done; 403 } 404 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 405 0, BUS_DMA_WAITOK, &sc->adma_map); 406 if (error) { 407 bus_dmamem_unmap(sc->sc_dmat, sc->adma2, PAGE_SIZE); 408 bus_dmamem_free(sc->sc_dmat, sc->adma_segs, rseg); 409 goto adma_done; 410 } 411 error = bus_dmamap_load(sc->sc_dmat, sc->adma_map, 412 sc->adma2, PAGE_SIZE, NULL, 413 BUS_DMA_WAITOK | BUS_DMA_WRITE); 414 if (error) { 415 bus_dmamap_destroy(sc->sc_dmat, sc->adma_map); 416 bus_dmamem_unmap(sc->sc_dmat, sc->adma2, PAGE_SIZE); 417 bus_dmamem_free(sc->sc_dmat, sc->adma_segs, rseg); 418 goto adma_done; 419 } 420 421 adma_done: 422 if (error) { 423 printf("%s: can't allocate DMA descriptor table\n", 424 DEVNAME(sc)); 425 CLR(sc->flags, SHF_USE_DMA); 426 } 427 } 428 429 /* 430 * Attach the generic SD/MMC bus driver. (The bus driver must 431 * not invoke any chipset functions before it is attached.) 432 */ 433 bzero(&saa, sizeof(saa)); 434 saa.saa_busname = "sdmmc"; 435 saa.sct = &imxesdhc_functions; 436 saa.sch = sc; 437 saa.dmat = sc->sc_dmat; 438 if (ISSET(sc->flags, SHF_USE_DMA)) { 439 saa.caps |= SMC_CAPS_DMA; 440 saa.max_seg = 65535; 441 } 442 443 if (caps & SDHC_HOST_CTRL_CAP_HSS) 444 saa.caps |= SMC_CAPS_MMC_HIGHSPEED | SMC_CAPS_SD_HIGHSPEED; 445 446 width = OF_getpropint(sc->sc_node, "bus-width", 1); 447 if (width >= 8) 448 saa.caps |= SMC_CAPS_8BIT_MODE; 449 if (width >= 4) 450 saa.caps |= SMC_CAPS_4BIT_MODE; 451 452 for (node = OF_child(sc->sc_node); node; node = OF_peer(node)) { 453 reg = OF_getpropint(node, "reg", -1); 454 if (reg < 0 || reg >= SDMMC_MAX_FUNCTIONS) 455 continue; 456 sc->sc_cookies[reg] = node; 457 saa.cookies[reg] = &sc->sc_cookies[reg]; 458 } 459 460 sc->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 461 if (sc->sdmmc == NULL) { 462 error = 0; 463 return; 464 } 465 } 466 467 void 468 imxesdhc_clock_enable(uint32_t phandle) 469 { 470 uint32_t gpios[3]; 471 int node; 472 473 node = OF_getnodebyphandle(phandle); 474 if (node == 0) 475 return; 476 477 if (!OF_is_compatible(node, "gpio-gate-clock")) 478 return; 479 480 pinctrl_byname(node, "default"); 481 482 OF_getpropintarray(node, "enable-gpios", gpios, sizeof(gpios)); 483 gpio_controller_config_pin(&gpios[0], GPIO_CONFIG_OUTPUT); 484 gpio_controller_set_pin(&gpios[0], 1); 485 } 486 487 void 488 imxesdhc_pwrseq_pre(uint32_t phandle) 489 { 490 uint32_t *gpios, *gpio; 491 uint32_t clocks; 492 int node; 493 int len; 494 495 node = OF_getnodebyphandle(phandle); 496 if (node == 0) 497 return; 498 499 if (!OF_is_compatible(node, "mmc-pwrseq-simple")) 500 return; 501 502 pinctrl_byname(node, "default"); 503 504 clocks = OF_getpropint(node, "clocks", 0); 505 if (clocks) 506 imxesdhc_clock_enable(clocks); 507 508 len = OF_getproplen(node, "reset-gpios"); 509 if (len <= 0) 510 return; 511 512 gpios = malloc(len, M_TEMP, M_WAITOK); 513 OF_getpropintarray(node, "reset-gpios", gpios, len); 514 515 gpio = gpios; 516 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) { 517 gpio_controller_config_pin(gpio, GPIO_CONFIG_OUTPUT); 518 gpio_controller_set_pin(gpio, 1); 519 gpio = gpio_controller_next_pin(gpio); 520 } 521 522 free(gpios, M_TEMP, len); 523 } 524 525 void 526 imxesdhc_pwrseq_post(uint32_t phandle) 527 { 528 uint32_t *gpios, *gpio; 529 int node; 530 int len; 531 532 node = OF_getnodebyphandle(phandle); 533 if (node == 0) 534 return; 535 536 if (!OF_is_compatible(node, "mmc-pwrseq-simple")) 537 return; 538 539 len = OF_getproplen(node, "reset-gpios"); 540 if (len <= 0) 541 return; 542 543 gpios = malloc(len, M_TEMP, M_WAITOK); 544 OF_getpropintarray(node, "reset-gpios", gpios, len); 545 546 gpio = gpios; 547 while (gpio && gpio < gpios + (len / sizeof(uint32_t))) { 548 gpio_controller_set_pin(gpio, 0); 549 gpio = gpio_controller_next_pin(gpio); 550 } 551 552 free(gpios, M_TEMP, len); 553 } 554 555 /* 556 * Reset the host controller. Called during initialization, when 557 * cards are removed, upon resume, and during error recovery. 558 */ 559 int 560 imxesdhc_host_reset(sdmmc_chipset_handle_t sch) 561 { 562 struct imxesdhc_softc *sc = sch; 563 u_int32_t imask; 564 int error; 565 int s; 566 567 s = splsdmmc(); 568 569 /* Disable all interrupts. */ 570 HWRITE4(sc, SDHC_INT_STATUS_EN, 0); 571 HWRITE4(sc, SDHC_INT_SIGNAL_EN, 0); 572 573 /* 574 * Reset the entire host controller and wait up to 100ms for 575 * the controller to clear the reset bit. 576 */ 577 if ((error = imxesdhc_soft_reset(sc, SDHC_SYS_CTRL_RSTA)) != 0) { 578 splx(s); 579 return (error); 580 } 581 582 /* Set data timeout counter value to max for now. */ 583 HSET4(sc, SDHC_SYS_CTRL, 0xe << SDHC_SYS_CTRL_DTOCV_SHIFT); 584 585 /* Enable interrupts. */ 586 imask = SDHC_INT_STATUS_CC | SDHC_INT_STATUS_TC | 587 SDHC_INT_STATUS_BGE | SDHC_INT_STATUS_DINT | 588 SDHC_INT_STATUS_BRR | SDHC_INT_STATUS_BWR; 589 590 imask |= SDHC_INT_STATUS_CTOE | SDHC_INT_STATUS_CCE | 591 SDHC_INT_STATUS_CEBE | SDHC_INT_STATUS_CIC | 592 SDHC_INT_STATUS_DTOE | SDHC_INT_STATUS_DCE | 593 SDHC_INT_STATUS_DEBE | SDHC_INT_STATUS_DMAE; 594 595 HWRITE4(sc, SDHC_INT_STATUS_EN, imask); 596 HWRITE4(sc, SDHC_INT_SIGNAL_EN, imask); 597 598 /* Switch back to no-DMA/SDMA. */ 599 HCLR4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DMASEL_MASK); 600 601 /* Switch back to 1-bit bus. */ 602 HCLR4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DTW_MASK); 603 604 /* Set watermarks and burst lengths to something sane. */ 605 HWRITE4(sc, SDHC_WTMK_LVL, 606 (64 << SDHC_WTMK_LVL_RD_WML_SHIFT) | 607 (16 << SDHC_WTMK_LVL_RD_BRST_LEN_SHIFT) | 608 (64 << SDHC_WTMK_LVL_WR_WML_SHIFT) | 609 (16 << SDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)); 610 611 splx(s); 612 return 0; 613 } 614 615 uint32_t 616 imxesdhc_host_ocr(sdmmc_chipset_handle_t sch) 617 { 618 struct imxesdhc_softc *sc = sch; 619 620 return sc->ocr; 621 } 622 623 int 624 imxesdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 625 { 626 struct imxesdhc_softc *sc = sch; 627 628 return sc->maxblklen; 629 } 630 631 /* 632 * Return non-zero if the card is currently inserted. 633 */ 634 int 635 imxesdhc_card_detect(sdmmc_chipset_handle_t sch) 636 { 637 struct imxesdhc_softc *sc = sch; 638 639 if (OF_getproplen(sc->sc_node, "non-removable") == 0) 640 return 1; 641 642 return gpio_controller_get_pin(sc->sc_gpio); 643 } 644 645 /* 646 * Set or change SD bus voltage and enable or disable SD bus power. 647 * Return zero on success. 648 */ 649 int 650 imxesdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 651 { 652 struct imxesdhc_softc *sc = sch; 653 uint32_t vdd = 0; 654 655 ocr &= sc->ocr; 656 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) 657 vdd = 3300000; 658 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) 659 vdd = 3000000; 660 else if (ISSET(ocr, MMC_OCR_1_65V_1_95V)) 661 vdd = 1800000; 662 663 if (sc->sc_vdd == 0 && vdd > 0) 664 imxesdhc_pwrseq_pre(sc->sc_pwrseq); 665 666 /* enable mmc power */ 667 if (sc->sc_vmmc && vdd > 0) 668 regulator_enable(sc->sc_vmmc); 669 670 if (sc->sc_vdd == 0 && vdd > 0) 671 imxesdhc_pwrseq_post(sc->sc_pwrseq); 672 673 sc->sc_vdd = vdd; 674 return 0; 675 } 676 677 /* 678 * Set or change SDCLK frequency or disable the SD clock. 679 * Return zero on success. 680 */ 681 int 682 imxesdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) 683 { 684 struct imxesdhc_softc *sc = sch; 685 int div, pre_div, cur_freq, s; 686 int error = 0; 687 688 s = splsdmmc(); 689 690 if (sc->clkbase / 16 > freq) { 691 for (pre_div = 2; pre_div < 256; pre_div *= 2) 692 if ((sc->clkbase / pre_div) <= (freq * 16)) 693 break; 694 } else 695 pre_div = 2; 696 697 if (sc->clkbase == freq) 698 pre_div = 1; 699 700 for (div = 1; div <= 16; div++) 701 if ((sc->clkbase / (div * pre_div)) <= freq) 702 break; 703 704 div -= 1; 705 pre_div >>= 1; 706 707 cur_freq = sc->clkbase / (pre_div * 2) / (div + 1); 708 709 /* disable force CLK ouput active */ 710 HCLR4(sc, SDHC_VEND_SPEC, SDHC_VEND_SPEC_FRC_SDCLK_ON); 711 712 /* wait while clock is unstable */ 713 if ((error = imxesdhc_wait_state(sc, 714 SDHC_PRES_STATE_SDSTB, SDHC_PRES_STATE_SDSTB)) != 0) 715 goto ret; 716 717 HCLR4(sc, SDHC_SYS_CTRL, SDHC_SYS_CTRL_CLOCK_MASK); 718 HSET4(sc, SDHC_SYS_CTRL, 719 (div << SDHC_SYS_CTRL_CLOCK_DIV_SHIFT) | 720 (pre_div << SDHC_SYS_CTRL_CLOCK_PRE_SHIFT)); 721 722 /* wait while clock is unstable */ 723 if ((error = imxesdhc_wait_state(sc, 724 SDHC_PRES_STATE_SDSTB, SDHC_PRES_STATE_SDSTB)) != 0) 725 goto ret; 726 727 ret: 728 splx(s); 729 return error; 730 } 731 732 int 733 imxesdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 734 { 735 struct imxesdhc_softc *sc = sch; 736 uint32_t reg; 737 int s; 738 739 if (width != 1 && width != 4 && width != 8) 740 return (1); 741 742 s = splsdmmc(); 743 744 reg = HREAD4(sc, SDHC_PROT_CTRL) & ~SDHC_PROT_CTRL_DTW_MASK; 745 if (width == 4) 746 reg |= SDHC_PROT_CTRL_DTW_4BIT; 747 else if (width == 8) 748 reg |= SDHC_PROT_CTRL_DTW_8BIT; 749 HWRITE4(sc, SDHC_PROT_CTRL, reg); 750 751 splx(s); 752 753 return (0); 754 } 755 756 void 757 imxesdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable) 758 { 759 struct imxesdhc_softc *sc = sch; 760 761 if (enable) { 762 HSET4(sc, SDHC_INT_STATUS_EN, SDHC_INT_STATUS_CINT); 763 HSET4(sc, SDHC_INT_SIGNAL_EN, SDHC_INT_STATUS_CINT); 764 } else { 765 HCLR4(sc, SDHC_INT_STATUS_EN, SDHC_INT_STATUS_CINT); 766 HCLR4(sc, SDHC_INT_SIGNAL_EN, SDHC_INT_STATUS_CINT); 767 } 768 } 769 770 void 771 imxesdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 772 { 773 struct imxesdhc_softc *sc = sch; 774 775 HSET4(sc, SDHC_INT_STATUS_EN, SDHC_INT_STATUS_CINT); 776 } 777 778 int 779 imxesdhc_wait_state(struct imxesdhc_softc *sc, uint32_t mask, uint32_t value) 780 { 781 uint32_t state; 782 int timeout; 783 784 state = HREAD4(sc, SDHC_PRES_STATE); 785 DPRINTF(3,("%s: wait_state %x %x %x)\n", 786 HDEVNAME(sc), mask, value, state)); 787 for (timeout = 1000; timeout > 0; timeout--) { 788 if (((state = HREAD4(sc, SDHC_PRES_STATE)) & mask) == value) 789 return 0; 790 delay(10); 791 } 792 DPRINTF(0,("%s: timeout waiting for %x, state %x\n", 793 HDEVNAME(sc), value, state)); 794 795 return ETIMEDOUT; 796 } 797 798 void 799 imxesdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 800 { 801 struct imxesdhc_softc *sc = sch; 802 int error; 803 804 /* 805 * Start the command, or mark `cmd' as failed and return. 806 */ 807 error = imxesdhc_start_command(sc, cmd); 808 if (error != 0) { 809 cmd->c_error = error; 810 SET(cmd->c_flags, SCF_ITSDONE); 811 return; 812 } 813 814 /* 815 * Wait until the command phase is done, or until the command 816 * is marked done for any other reason. 817 */ 818 if (!imxesdhc_wait_intr(sc, SDHC_INT_STATUS_CC, SDHC_COMMAND_TIMEOUT)) { 819 cmd->c_error = ETIMEDOUT; 820 SET(cmd->c_flags, SCF_ITSDONE); 821 return; 822 } 823 824 /* 825 * The host controller removes bits [0:7] from the response 826 * data (CRC) and we pass the data up unchanged to the bus 827 * driver (without padding). 828 */ 829 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 830 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 831 cmd->c_resp[0] = HREAD4(sc, SDHC_CMD_RSP0); 832 cmd->c_resp[1] = HREAD4(sc, SDHC_CMD_RSP1); 833 cmd->c_resp[2] = HREAD4(sc, SDHC_CMD_RSP2); 834 cmd->c_resp[3] = HREAD4(sc, SDHC_CMD_RSP3); 835 #ifdef SDHC_DEBUG 836 printf("resp[0] 0x%08x\nresp[1] 0x%08x\n" 837 "resp[2] 0x%08x\nresp[3] 0x%08x\n", 838 cmd->c_resp[0], 839 cmd->c_resp[1], 840 cmd->c_resp[2], 841 cmd->c_resp[3]); 842 #endif 843 } else { 844 cmd->c_resp[0] = HREAD4(sc, SDHC_CMD_RSP0); 845 #ifdef SDHC_DEBUG 846 printf("resp[0] 0x%08x\n", cmd->c_resp[0]); 847 #endif 848 } 849 } 850 851 /* 852 * If the command has data to transfer in any direction, 853 * execute the transfer now. 854 */ 855 if (cmd->c_error == 0 && cmd->c_data) 856 imxesdhc_transfer_data(sc, cmd); 857 858 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n", 859 HDEVNAME(sc), cmd->c_opcode, cmd->c_flags, cmd->c_error)); 860 SET(cmd->c_flags, SCF_ITSDONE); 861 } 862 863 int 864 imxesdhc_start_command(struct imxesdhc_softc *sc, struct sdmmc_command *cmd) 865 { 866 struct sdhc_adma2_descriptor32 *desc = (void *)sc->adma2; 867 u_int32_t blksize = 0; 868 u_int32_t blkcount = 0; 869 u_int32_t command; 870 int error; 871 int seg; 872 int s; 873 874 DPRINTF(1,("%s: start cmd %u arg=%#x data=%p dlen=%d flags=%#x " 875 "proc=\"%s\"\n", HDEVNAME(sc), cmd->c_opcode, cmd->c_arg, 876 cmd->c_data, cmd->c_datalen, cmd->c_flags, curproc ? 877 curproc->p_p->ps_comm : "")); 878 879 /* 880 * The maximum block length for commands should be the minimum 881 * of the host buffer size and the card buffer size. (1.7.2) 882 */ 883 884 /* Fragment the data into proper blocks. */ 885 if (cmd->c_datalen > 0) { 886 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 887 blkcount = cmd->c_datalen / blksize; 888 if (cmd->c_datalen % blksize > 0) { 889 /* XXX: Split this command. (1.7.4) */ 890 printf("%s: data not a multiple of %d bytes\n", 891 HDEVNAME(sc), blksize); 892 return EINVAL; 893 } 894 } 895 896 /* Check limit imposed by 9-bit block count. (1.7.2) */ 897 if (blkcount > SDHC_BLK_ATT_BLKCNT_MAX) { 898 printf("%s: too much data\n", HDEVNAME(sc)); 899 return EINVAL; 900 } 901 902 /* Check for write protection. */ 903 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 904 if (!(HREAD4(sc, SDHC_PRES_STATE) & SDHC_PRES_STATE_WPSPL)) { 905 printf("%s: card is write protected\n", 906 HDEVNAME(sc)); 907 return EINVAL; 908 } 909 } 910 911 /* Prepare transfer mode register value. (2.2.5) */ 912 command = 0; 913 914 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 915 command |= SDHC_MIX_CTRL_DTDSEL; 916 if (blkcount > 0) { 917 command |= SDHC_MIX_CTRL_BCEN; 918 if (blkcount > 1) { 919 command |= SDHC_MIX_CTRL_MSBSEL; 920 if (cmd->c_opcode != SD_IO_RW_EXTENDED) 921 command |= SDHC_MIX_CTRL_AC12EN; 922 } 923 } 924 if (cmd->c_dmamap && cmd->c_datalen > 0 && 925 ISSET(sc->flags, SHF_USE_DMA)) 926 command |= SDHC_MIX_CTRL_DMAEN; 927 928 command |= (cmd->c_opcode << SDHC_CMD_XFR_TYP_CMDINDX_SHIFT) & 929 SDHC_CMD_XFR_TYP_CMDINDX_SHIFT_MASK; 930 931 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 932 command |= SDHC_CMD_XFR_TYP_CCCEN; 933 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 934 command |= SDHC_CMD_XFR_TYP_CICEN; 935 if (cmd->c_data != NULL) 936 command |= SDHC_CMD_XFR_TYP_DPSEL; 937 938 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 939 command |= SDHC_CMD_XFR_TYP_RSP_NONE; 940 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 941 command |= SDHC_CMD_XFR_TYP_RSP136; 942 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 943 command |= SDHC_CMD_XFR_TYP_RSP48B; 944 else 945 command |= SDHC_CMD_XFR_TYP_RSP48; 946 947 /* Wait until command and data inhibit bits are clear. (1.5) */ 948 if ((error = imxesdhc_wait_state(sc, SDHC_PRES_STATE_CIHB, 0)) != 0) 949 return error; 950 951 s = splsdmmc(); 952 953 /* Set DMA start address if SHF_USE_DMA is set. */ 954 if (cmd->c_dmamap && ISSET(sc->flags, SHF_USE_DMA)) { 955 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 956 bus_addr_t paddr = 957 cmd->c_dmamap->dm_segs[seg].ds_addr; 958 uint16_t len = 959 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ? 960 0 : cmd->c_dmamap->dm_segs[seg].ds_len; 961 uint16_t attr; 962 963 attr = SDHC_ADMA2_VALID | SDHC_ADMA2_ACT_TRANS; 964 if (seg == cmd->c_dmamap->dm_nsegs - 1) 965 attr |= SDHC_ADMA2_END; 966 967 desc[seg].attribute = htole16(attr); 968 desc[seg].length = htole16(len); 969 desc[seg].address = htole32(paddr); 970 } 971 972 desc[cmd->c_dmamap->dm_nsegs].attribute = htole16(0); 973 974 bus_dmamap_sync(sc->sc_dmat, sc->adma_map, 0, PAGE_SIZE, 975 BUS_DMASYNC_PREWRITE); 976 977 HCLR4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DMASEL_MASK); 978 HSET4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DMASEL_ADMA2); 979 980 HWRITE4(sc, SDHC_ADMA_SYS_ADDR, 981 sc->adma_map->dm_segs[0].ds_addr); 982 } else 983 HCLR4(sc, SDHC_PROT_CTRL, SDHC_PROT_CTRL_DMASEL_MASK); 984 985 /* 986 * Start a CPU data transfer. Writing to the high order byte 987 * of the SDHC_COMMAND register triggers the SD command. (1.5) 988 */ 989 HWRITE4(sc, SDHC_BLK_ATT, blkcount << SDHC_BLK_ATT_BLKCNT_SHIFT | 990 blksize << SDHC_BLK_ATT_BLKSIZE_SHIFT); 991 HWRITE4(sc, SDHC_CMD_ARG, cmd->c_arg); 992 HWRITE4(sc, SDHC_MIX_CTRL, 993 (HREAD4(sc, SDHC_MIX_CTRL) & (0xf << 22)) | (command & 0xffff)); 994 HWRITE4(sc, SDHC_CMD_XFR_TYP, command); 995 996 splx(s); 997 return 0; 998 } 999 1000 void 1001 imxesdhc_transfer_data(struct imxesdhc_softc *sc, struct sdmmc_command *cmd) 1002 { 1003 u_char *datap = cmd->c_data; 1004 int i, datalen; 1005 int mask; 1006 int error; 1007 1008 if (cmd->c_dmamap) { 1009 int status; 1010 1011 error = 0; 1012 for (;;) { 1013 status = imxesdhc_wait_intr(sc, 1014 SDHC_INT_STATUS_DINT|SDHC_INT_STATUS_TC, 1015 SDHC_DMA_TIMEOUT); 1016 if (status & SDHC_INT_STATUS_TC) 1017 break; 1018 if (!status) { 1019 error = ETIMEDOUT; 1020 break; 1021 } 1022 } 1023 1024 bus_dmamap_sync(sc->sc_dmat, sc->adma_map, 0, PAGE_SIZE, 1025 BUS_DMASYNC_POSTWRITE); 1026 goto done; 1027 } 1028 1029 mask = ISSET(cmd->c_flags, SCF_CMD_READ) ? 1030 SDHC_PRES_STATE_BREN : SDHC_PRES_STATE_BWEN; 1031 error = 0; 1032 datalen = cmd->c_datalen; 1033 1034 DPRINTF(1,("%s: resp=%#x datalen=%d\n", 1035 HDEVNAME(sc), MMC_R1(cmd->c_resp), datalen)); 1036 1037 while (datalen > 0) { 1038 if (!imxesdhc_wait_intr(sc, 1039 SDHC_INT_STATUS_BRR | SDHC_INT_STATUS_BWR, 1040 SDHC_BUFFER_TIMEOUT)) { 1041 error = ETIMEDOUT; 1042 break; 1043 } 1044 1045 if ((error = imxesdhc_wait_state(sc, mask, mask)) != 0) 1046 break; 1047 1048 /* FIXME: wait a bit, else it fails */ 1049 delay(100); 1050 i = MIN(datalen, cmd->c_blklen); 1051 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1052 imxesdhc_read_data(sc, datap, i); 1053 else 1054 imxesdhc_write_data(sc, datap, i); 1055 1056 datap += i; 1057 datalen -= i; 1058 } 1059 1060 if (error == 0 && !imxesdhc_wait_intr(sc, SDHC_INT_STATUS_TC, 1061 SDHC_TRANSFER_TIMEOUT)) 1062 error = ETIMEDOUT; 1063 1064 done: 1065 if (error != 0) 1066 cmd->c_error = error; 1067 SET(cmd->c_flags, SCF_ITSDONE); 1068 1069 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1070 HDEVNAME(sc), cmd->c_error)); 1071 } 1072 1073 void 1074 imxesdhc_read_data(struct imxesdhc_softc *sc, u_char *datap, int datalen) 1075 { 1076 while (datalen > 3) { 1077 *(uint32_t *)datap = HREAD4(sc, SDHC_DATA_BUFF_ACC_PORT); 1078 datap += 4; 1079 datalen -= 4; 1080 } 1081 if (datalen > 0) { 1082 uint32_t rv = HREAD4(sc, SDHC_DATA_BUFF_ACC_PORT); 1083 do { 1084 *datap++ = rv & 0xff; 1085 rv = rv >> 8; 1086 } while (--datalen > 0); 1087 } 1088 } 1089 1090 void 1091 imxesdhc_write_data(struct imxesdhc_softc *sc, u_char *datap, int datalen) 1092 { 1093 while (datalen > 3) { 1094 DPRINTF(3,("%08x\n", *(uint32_t *)datap)); 1095 HWRITE4(sc, SDHC_DATA_BUFF_ACC_PORT, *((uint32_t *)datap)); 1096 datap += 4; 1097 datalen -= 4; 1098 } 1099 if (datalen > 0) { 1100 uint32_t rv = *datap++; 1101 if (datalen > 1) 1102 rv |= *datap++ << 8; 1103 if (datalen > 2) 1104 rv |= *datap++ << 16; 1105 DPRINTF(3,("rv %08x\n", rv)); 1106 HWRITE4(sc, SDHC_DATA_BUFF_ACC_PORT, rv); 1107 } 1108 } 1109 1110 /* Prepare for another command. */ 1111 int 1112 imxesdhc_soft_reset(struct imxesdhc_softc *sc, int mask) 1113 { 1114 int timo; 1115 1116 DPRINTF(1,("%s: software reset reg=%#x\n", HDEVNAME(sc), mask)); 1117 1118 /* disable force CLK ouput active */ 1119 HCLR4(sc, SDHC_VEND_SPEC, SDHC_VEND_SPEC_FRC_SDCLK_ON); 1120 1121 /* reset */ 1122 HSET4(sc, SDHC_SYS_CTRL, mask); 1123 delay(10); 1124 1125 for (timo = 1000; timo > 0; timo--) { 1126 if (!ISSET(HREAD4(sc, SDHC_SYS_CTRL), mask)) 1127 break; 1128 delay(10); 1129 } 1130 if (timo == 0) { 1131 DPRINTF(1,("%s: timeout reg=%#x\n", HDEVNAME(sc), 1132 HREAD4(sc, SDHC_SYS_CTRL))); 1133 return ETIMEDOUT; 1134 } 1135 1136 return 0; 1137 } 1138 1139 int 1140 imxesdhc_wait_intr(struct imxesdhc_softc *sc, int mask, int timo) 1141 { 1142 int status; 1143 int s; 1144 1145 mask |= SDHC_INT_STATUS_ERR; 1146 s = splsdmmc(); 1147 1148 /* enable interrupts for brr and bwr */ 1149 if (mask & (SDHC_INT_STATUS_BRR | SDHC_INT_STATUS_BWR)) 1150 HSET4(sc, SDHC_INT_SIGNAL_EN, 1151 (SDHC_INT_STATUS_BRR | SDHC_INT_STATUS_BWR)); 1152 1153 status = sc->intr_status & mask; 1154 while (status == 0) { 1155 if (tsleep(&sc->intr_status, PWAIT, "hcintr", timo) 1156 == EWOULDBLOCK) { 1157 status |= SDHC_INT_STATUS_ERR; 1158 break; 1159 } 1160 status = sc->intr_status & mask; 1161 } 1162 sc->intr_status &= ~status; 1163 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(sc), status, 1164 sc->intr_error_status)); 1165 1166 /* Command timeout has higher priority than command complete. */ 1167 if (ISSET(status, SDHC_INT_STATUS_ERR)) { 1168 sc->intr_error_status = 0; 1169 (void)imxesdhc_soft_reset(sc, 1170 SDHC_SYS_CTRL_RSTC | SDHC_SYS_CTRL_RSTD); 1171 status = 0; 1172 } 1173 1174 splx(s); 1175 return status; 1176 } 1177 1178 /* 1179 * Established by attachment driver at interrupt priority IPL_SDMMC. 1180 */ 1181 int 1182 imxesdhc_intr(void *arg) 1183 { 1184 struct imxesdhc_softc *sc = arg; 1185 1186 u_int32_t status; 1187 1188 /* Find out which interrupts are pending. */ 1189 status = HREAD4(sc, SDHC_INT_STATUS); 1190 1191 /* disable interrupts for brr and bwr, else we get flooded */ 1192 if (status & (SDHC_INT_STATUS_BRR | SDHC_INT_STATUS_BWR)) 1193 HCLR4(sc, SDHC_INT_SIGNAL_EN, 1194 (SDHC_INT_STATUS_BRR | SDHC_INT_STATUS_BWR)); 1195 1196 /* Acknowledge the interrupts we are about to handle. */ 1197 HWRITE4(sc, SDHC_INT_STATUS, status); 1198 DPRINTF(2,("%s: interrupt status=0x%08x\n", HDEVNAME(sc), status)); 1199 1200 /* 1201 * Service error interrupts. 1202 */ 1203 if (ISSET(status, SDHC_INT_STATUS_CMD_ERR | 1204 SDHC_INT_STATUS_CTOE | SDHC_INT_STATUS_DTOE)) { 1205 sc->intr_status |= status; 1206 sc->intr_error_status |= status & 0xffff0000; 1207 wakeup(&sc->intr_status); 1208 } 1209 1210 /* 1211 * Wake up the blocking process to service command 1212 * related interrupt(s). 1213 */ 1214 if (ISSET(status, SDHC_INT_STATUS_BRR | SDHC_INT_STATUS_BWR | 1215 SDHC_INT_STATUS_TC | SDHC_INT_STATUS_CC)) { 1216 sc->intr_status |= status; 1217 wakeup(&sc->intr_status); 1218 } 1219 1220 /* 1221 * Service SD card interrupts. 1222 */ 1223 if (ISSET(status, SDHC_INT_STATUS_CINT)) { 1224 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(sc))); 1225 HCLR4(sc, SDHC_INT_STATUS_EN, SDHC_INT_STATUS_CINT); 1226 sdmmc_card_intr(sc->sdmmc); 1227 } 1228 1229 return 1; 1230 } 1231